Burr Brown Products
from Texas Instruments
FEATURES
DESCRIPTION
APPLICATIONS
Shift Register
16
DAC Register
16
16!Bit DAC
Ref (+)
Resistor
Networ
k
V
DD
GND
V
OUT
V
FB
SYNC
V
REF
SCLK
D
IN
PWB Control
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
Relative Accuracy: 8 LSB (Max)
The DAC8550 is a small, low-power, voltage output,
16-bit
digital-to-analog
converter
(DAC).
It
is
Glitch Energy: 0.1 nV-s
monotonic, provides good linearity, and minimizes
Settling Time: 10 s to 0.003% FSR
undesired code to code transient voltages. The
Power Supply: +2.7 V to +5.5 V
DAC8550 uses a versatile 3-wire serial interface that
16-Bit Monotonic Over Temperature
operates at clock rates of up to 30 MHz and is
compatible
with
standard
SPITM,
QSPITM,
MicroPower Operation: 200 A at 5 V
MicrowireTM, and digital signal processor (DSP)
Rail-to-Rail Output Amplifier
interfaces.
Power-On Reset to Midscale
The DAC8550 requires an external reference voltage
Power-Down Capability
to set its output range. The DAC8550 incorporates a
Schmitt-Triggered Digital Inputs
power-on reset circuit that ensures that the DAC
output powers up at midscale and remain there until a
SYNC Interrupt Facility
valid write takes place to the device. The DAC8550
2's Complement Input and Reset to Midscale
contains a power-down feature, accessed over the
Operating Temperature Range: -40C to 105C
serial interface, that reduces the current consumption
of the device to 200 nA at 5 V.
Available Packages:
3 mm 5 mm MSOP-8
The low-power consumption of this device in normal
operation makes it ideal for portable battery-operated
equipment. Power consumption is 1 mW at 5 V,
reducing to 1 W in power-down mode.
Process Control
The DAC8550 is available in a MSOP-8 package.
Data Acquisition Systems
Closed-Loop Servo-Control
Also see the DAC8551 binary coded counterpart of
PC Peripherals
the DAC8550.
Portable Instrumentation
Programmable Attenuation
FUNCTIONAL BLOCK DIAGRAM
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola.
Microwire is a trademark of National Semiconductor.
PRODUCTION DATA information is current as of publication date.
Copyright 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
ELECTRICAL CHARACTERISTICS
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION
RELATIVE
DIFFERENTIAL
SPECIFICATION
TRANSPORT
PACKAGE
PACKAGE
PACKAGE
ORDERING
PRODUCT
ACCURACY
NONLINEARITY
TEMPERATURE
MEDIA,
LEAD
DESIGNATOR
(1)
MARKING
NUMBER
(LSB)
(LSB)
RANGE
QUANTITY
DAC8550IDGKT
Tape and Reel, 250
DAC8550
12
1
MSOP-8
DGK
40C TO 105C
D80
DAC8550IDGKR
Tape and Reel, 2500
DAC8550IBDGKT
Tape and Reel, 250
DAC8550B
8
1
MSOP-8
DGK
40C TO 105C
D80
DAC8550IBDGKR
Tape and Reel, 2500
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document or see the TI
website at
www.ti.com
.
UNIT
Supply voltage, V
DD
to GND
0.3 V to 6 V
Digital input voltage range, V
I
to GND
0.3 V to +V
DD
+ 0.3 V
Output voltage, V
OUT
to GND
0.3 V to +V
DD
+ 0.3 V
Operating free-air temperature range, T
A
40C to 105C
Storage temperature range, T
STG
65C to 150C
Junction temperature range, T
J(max)
150C
Power dissipation (DGK package)
(T
J
max T
A
)/
JA
Thermal impedance,
JA
206C/W
Thermal impedance,
JC
44C/W
(1)
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
V
DD
= 2.7 V to 5.5 V, 40C to 105C range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
(1)
Resolution
16
Bits
Measured by line passing
DAC8550
5
12
LSB
E
L
Relative accuracy
through codes -32283 and
3
8
LSB
DAC8550B
32063
E
D
Differential nonlinearity
16-bit Monotonic
0.25
1
LSB
E
O
Zero-code error
2
12
mV
Measured by line passing through codes -32283
E
FS
Full-scale error
0.05
0.5
% of FSR
and 32063.
E
G
Gain error
0.02
0.2
% of FSR
Zero-code error drift
5
V/C
Gain temperature coefficient
1
ppm of
FSR/C
PSRR
Power supply rejection ratio
R
L
= 2 k
, C
L
= 200 pF
0.75
mV/V
OUTPUT CHARACTERISTICS
(2)
V
O
Output voltage range
0
V
REF
V
(1)
Linearity calculated using a reduced code range of -32283 to 32063; output unloaded.
(2)
Specified by design and characterization, not production tested.
2
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DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= 2.7 V to 5.5 V, 40C to 105C range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
To 0.003% FSR, 1200
H
to 8D00
H
, R
L
= 2 k
, 0
8
10
s
pF < C
L
< 200 pF
t
sd
Output voltage settling time
R
L
= 2 k
, C
L
= 500 pF
12
s
SR
Slew rate
1.8
V/s
R
L
=
470
pF
Capacitive load stability
R
L
= 2 k
1000
pF
Code change glitch impulse
1 LSB change around major carry
0.1
nV-s
Digital feedthrough
SCLK toggling, FSYNC high
0.1
z
o
DC output impedance
At mid-code input
1
V
DD
= 5 V
50
I
OS
Short-circuit current
mA
V
DD
= 3 V
20
Coming out of power-down mode V
DD
= 5 V
2.5
t
on
Power-up time
s
Coming out of power-down mode V
DD
= 3 V
5
AC PERFORMANCE
Signal-to-noise ratio (1st 19
95
SNR
harmonics removed)
THD
Total harmonic distortion
85
BW = 20 kHz, V
DD
= 5 V, f
OUT
= 1 kHz
dB
SFDR
Spurious-free dynamic range
87
SINAD
Signal-to-noise and distortion
84
REFERENCE INPUT
V
ref
Reference voltage
0
V
DD
V
V
REF
= V
DD
= 5 V
50
75
A
I
I(ref)
Reference current input range
V
REF
= V
DD
= 3.6 V
30
45
A
z
I(ref)
Reference input impedance
125
k
LOGIC INPUTS
(3)
Input current
1
A
V
DD
= 5 V
0.8
V
IL
Low-level input voltage
V
V
DD
= 3 V
0.6
V
DD
= 5 V
2.4
V
IH
High-level input voltage
V
V
DD
= 3 V
2.1
Pin capacitance
3
pF
POWER REQUIREMENTS
V
DD
2.7
5.5
V
I
DD
(normal mode)
Input code equals mid-scale, reference current
included, no load
V
DD
= 3.6 V to 5.5 V
200
250
V
IH
= V
DD
and V
IL
= GND
A
V
DD
= 2.7 V to 3.6 V
180
240
I
DD
(all power-down modes)
V
DD
= 3.6 V to 5.5 V
V
IH
= V
DD
and V
IL
= GND
0.2
2
A
V
DD
= 2.7 V to 3.6 V
0.05
2
POWER EFFICIENCY
I
OUT
/I
DD
I
LOAD
= 2 mA, V
DD
= 5 V
89%
TEMPERATURE RANGE
Specified performance
40
105
C
(3)
Specified by design and characterization, not production tested.
3
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PIN CONFIGURATION
V
DD
V
REF
V
FB
V
OUT
GND
D
IN
SCLK
SYNC
1
2
3
4
8
7
6
5
DAC8550
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
MSOP-8
(Top View)
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
1
V
DD
Power supply input, 2.7 V to 5.5 V.
2
V
REF
Reference voltage input.
3
V
FB
Feedback connection for the output amplifier.
4
V
OUT
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is
5
SYNC
updated following the 24th clock (unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts
as an interrupt and the write sequence is ignored by the DAC8550).
6
SCLK
Serial clock input. Data can be transferred at rates up to 30 MHz.
7
D
IN
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input.
8
GND
Ground reference point for all circuitry on the part.
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TIMING REQUIREMENTS
(1) (2)
SERIAL WRITE OPERATION
SCLK
SYNC
D
IN
DB23
t
3
t
2
t
1
t
f
t
su1
t
su2
t
h
t
c
DB0
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
V
DD
= 2.7 V to 5.5 V, all specifications 40C to 105C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
DD
= 2.7 V to 3.6 V
20
t
c
(3)
SCLK cycle time
ns
V
DD
= 3.6 V to 5.5 V
20
V
DD
= 2.7 V to 3.6 V
13
t
1
SCLK HIGH time
ns
V
DD
= 3.6 V to 5.5 V
13
V
DD
= 2.7 V to 3.6 V
22.5
t
2
SCLK LOW time
ns
V
DD
= 3.6 V to 5.5 V
13
V
DD
= 2.7 V to 3.6 V
0
t
su1
SYNC to SCLK rising edge setup time
ns
V
DD
= 3.6 V to 5.5 V
0
V
DD
= 2.7 V to 3.6 V
5
t
su2
Data setup time
ns
V
DD
= 3.6 V to 5.5 V
5
V
DD
= 2.7 V to 3.6 V
4.5
t
h
Data hold time
ns
V
DD
= 3.6 V to 5.5 V
4.5
V
DD
= 2.7 V to 3.6 V
0
t
f
SCLK falling edge to SYNC rising edge
ns
V
DD
= 3.6 V to 5.5 V
0
V
DD
= 2.7 V to 3.6 V
50
t
3
Minimum SYNC HIGH time
ns
V
DD
= 3.6 V to 5.5 V
33
(1)
All input signals are specified with t
R
= t
F
= 3 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2)
See Serial Write Operation timing diagram.
(3)
Maximum SCLK frequency is 30 MHz at V
DD
= 3.6 V to 5.5 V and 20 MHz at V
DD
= 2.7 V to 3.6 V.
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TYPICAL CHARACTERISTICS: V
DD
= 5 V
-6
-4
-2
0
2
4
6
LE - (LSB)
-1
-0.5
0
0.5
1
0
8192
16384
24576 32768
40960
49152 57344 65536
Digital Input Code
DLE - (LSB)
V
DD
= 5 V, V
REF
= 4.99 V
-6
-4
-2
0
2
4
6
LE - (LSB)
-1
-0.5
0
0.5
1
0
8192
16384
24576
32768 40960 49152
57344 65536
Digital Input Code
DLE - (LSB)
V
DD
= 5 V, V
REF
= 4.99 V
-6
-4
-2
0
2
4
6
LE - (LSB)
-1
-0.5
0
0.5
1
0
8192
16384 24576
32768
40960
49152 57344 65536
Digital Input Code
DLE - (LSB)
V
DD
= 5 V, V
REF
= 4.99 V
-5
0
5
10
-40
0
40
80
120
Temperature -
5
C
Error (mV)
V
DD
= 5 V, V
REF
= 4.99 V
0
200
400
600
800
1000
120
140
160
180
200
220
240
260
280
300
I
DD
- Supply Current -
m
A
f - Frequency - Hz
V
DD
= V
REF
= 5.5 V,
Reference Current Included
-10
-5
0
-40
0
40
80
120
Temperature -
5
C
Error (mV)
V
DD
= 5 V, V
REF
= 4.99 V
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
At T
A
= 25C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
CODE
CODE
(-40C)
(25C)
Figure 1.
Figure 2.
LINEARITY ERROR AND
ZERO-SCALE ERROR
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
vs
CODE
TEMPERATURE
(105C)
Figure 3.
Figure 4.
FULL-SCALE ERROR
I
DD
HISTOGRAM
vs
TEMPERATURE
Figure 5.
Figure 6.
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I
(SOURCE/SINK)
- mA
0
1
2
3
4
5
6
0
3
5
8
10
- Output V
oltage - V
V
OUT
DAC Loaded With 0000
H
DAC Loaded With FFFF
H
V
DD
= 5.5 V
V
REF
= V
DD
-10 mV
0
50
100
150
200
250
300
0
8192
16384 24576
32768 40960
49152 57344 65536
Digital Input Code
DDI
Supply Current -
-
A
V
DD
= V
REF
= 5.5 V
Reference Current Included
Quiescent Current -
A
0
50
100
150
200
250
-40
-10
20
50
80
110
Temperature -
5
C
V
DD
= V
REF
= 5.5 V
Reference Current Included
100
120
140
160
180
200
220
240
260
280
300
2.7
3.1
3.4
3.8
4.1
4.5
4.8
5.2
5.5
DDI
Supply Current -
-
A
V
DD
- Supply Voltage - V
V
REF
= V
DD
Reference Current Include, No Load
0
0.3
0.5
0.8
1
2.7
3.1
3.4
3.8
4.1
4.5
4.8
5.2
5.5
I
A
V
DD
- Supply Voltage - V
V
REF
= V
DD
DD
- Supply Current -
100
500
900
1300
1700
0
1
2
3
4
5
DDI
Supply Current -
-
A
V
DD
= V
REF
= 5.5 V
T
A
= 25
C, SCL Input (All Other Inputs = GND)
V
(LOGIC)
- V
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
TYPICAL CHARACTERISTICS: V
DD
= 5 V (continued)
At T
A
= 25C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
SOURCE AND SINK CURRENT CAPABILITY
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
Figure 7.
Figure 8.
POWER-SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
TEMPERATURE
SUPPLY VOLTAGE
Figure 9.
Figure 10.
POWER-DOWN CURRENT
SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
LOGIC INPUT VOLTAGE
Figure 11.
Figure 12.
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Time (2
s/div)
V
DD
= 5 V,
V
REF
= 4.096 V,
From Code: FFFF
To Code: 0000
Zoomed Falling Edge
1 mV/div
Trigger Pulse
5 V/div
Falling
Edge
1 V/div
Time (2
s/div)
V
DD
= 5 V,
V
REF
= 4.096 V,
From Code: 0000
To Code: FFFF
Zoomed Rising Edge
1 mV/div
Trigger Pulse
5 V/div
Rising Edge
1 V/div
Time (2
s/div)
V
DD
= 5 V,
V
REF
= 4.096 V,
From Code: 4000
To Code: CFFF
Zoomed Rising Edge
1 mV/div
Trigger Pulse
5 V/div
Rising
Edge
1 V/div
Time (2
s/div)
V
DD
= 5 V,
V
REF
= 4.096 V,
From Code: CFFF
To Code: 4000
Zoomed Falling Edge
1 mV/div
Trigger Pulse
5 V/div
Falling
Edge
1 V/div
V
DD
= 5 V,
V
REF
= 4.096 V
From Code: 8000
To Code: 7FFF
Glitch: 0.16 nV-s
Measured Worst Case
Time 400 ns/div
V
OUT
(500
m
V/div)
V
DD
= 5 V,
V
REF
= 4.096 V
From Code: 7FFF
To Code: 8000
Glitch: 0.08 nV-s
Time 400 ns/div
V
OUT
(500
m
V/div)
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
TYPICAL CHARACTERISTICS: V
DD
= 5 V (continued)
At T
A
= 25C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
FULL-SCALE SETTLING TIME: 5-V RISING EDGE
FULL-SCALE SETTLING TIME: 5-V FALLING EDGE
Figure 13.
Figure 14.
HALF-SCALE SETTLING TIME: 5-V RISING EDGE
HALF-SCALE SETTLING TIME: 5-V FALLING EDGE
Figure 15.
Figure 16.
GLITCH ENERGY: 5-V, 1-LSB STEP, RISING EDGE
GLITCH ENERGY: 5-V, 1-LSB STEP, FALLING EDGE
Figure 17.
Figure 18.
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V
DD
= 5 V,
V
REF
= 4.096 V
From Code: 8010
To Code: 8000
Glitch: 0.08 nV-s
Time 400 ns/div
V
OUT
(500
V/div)
m
V
DD
= 5 V,
V
REF
= 4.096 V
From Code: 8000
To Code: 8010
Glitch: 0.04 nV-s
Time 400 ns/div
V
OUT
(500
m
V/div)
V
DD
= 5 V,
V
REF
= 4.096 V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
Time 400 ns/div
V
OUT
(5 mV/div)
V
DD
= 5 V,
V
REF
= 4.096 V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time 400 ns/div
V
OUT
(5 mV/div)
84
86
88
90
92
94
96
98
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
SNR - Signal-to-Noise Ratio - dB
f - Output Frequency - kHz
V
DD
= V
REF
= 5 V
-1 dB FSR Digital Input, Fs = 1 MSPS
Measurement Bandwidth = 20 kHz
-100
-90
-80
-70
-60
-50
-40
0
1
2
3
4
5
THD - T
otal Harmonic Distortion - dB
Output Tone - kHz
THD
2nd Harmonic
3rd Harmonic
-1dB FSR Digital Input, Fs = 1 MSPS
Measurement Bandwidth = 20 kHz
V
DD
= 5 V, V
REF
= 4.9 V
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
TYPICAL CHARACTERISTICS: V
DD
= 5 V (continued)
At T
A
= 25C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
GLITCH ENERGY: 5-V, 16-LSB STEP, RISING EDGE
GLITCH ENERGY: 5-V, 16-LSB STEP, FALLING EDGE
Figure 19.
Figure 20.
GLITCH ENERGY: 5-V, 256-LSB STEP, RISING EDGE
GLITCH ENERGY: 5-V, 256-LSB STEP, FALLING EDGE
Figure 21.
Figure 22.
TOTAL HARMONIC DISTORTION
SIGNAL-TO-NOISE RATIO
vs
vs
OUTPUT FREQUENCY
OUTPUT FREQUENCY
Figure 23.
Figure 24.
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100
150
200
250
300
350
100
1000
10000
100000
V
DD
= 5 V
V
REF
= 4.096
Code = 7FFF
No Load
nV/
Hz
- V
oltage Noise -
V
n
f - Frequency - Hz
-130
-110
-90
-70
-50
-30
-10
0
5000
10000
15000
20000
V
DD
= 5.0 V, V
REF
= 4.096 V
f
OUT
= 1 kHz
f
CLK
=
1 MSPS
f - Frequency - Hz
Gain - dB
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
TYPICAL CHARACTERISTICS: V
DD
= 5 V (continued)
At T
A
= 25C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
POWER SPECTRAL DENSITY
OUTPUT NOISE DENSITY
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS: V
DD
= 2.7 V
-6
-4
-2
0
2
4
6
LE - (LSB)
-1
-0.5
0
0.5
1
0
8192
16384
24576
32768 40960
49152 57344 65536
Digital Input Code
DLE - (LSB)
V
DD
= 2.7 V, V
REF
= 2.69 V
-6
-4
-2
0
2
4
6
LE - (LSB)
DLE - (LSB)
V
DD
= 2.7 V, V
REF
= 2.69 V
-1
-0.5
0
0.5
1
0
8192
16384
24576 32768 40960
49152 57344 65536
Digital Input Code
-6
-4
-2
0
2
4
6
LE - (LSB)
V
DD
= 2.7 V, V
REF
= 2.69 V
-1
-0.5
0
0.5
1
0
8192
16384
24576
32768
40960
49152 57344 65536
Digital Input Code
DLE - (LSB)
-5
0
5
10
-40
0
40
80
120
Temperature -
5
C
Error (mV)
V
DD
= 2.7 V, V
REF
= 2.69 V
0
300
600
900
1200
1500
120
140
160
180
200
220
240
260
280
300
I
DD
- Supply Current -
m
A
f - Frequency - Hz
V
DD
= V
REF
= 2.7 V
Reference Current Included
-10
-5
0
5
-40
0
40
80
120
Temperature -
5
C
Error (mV)
V
DD
= 2.7 V, V
REF
= 2.69 V
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
At T
A
= 25C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL
DIFFERENTIAL LINEARITY ERROR vs DIGITAL
INPUT CODE
INPUT CODE
(-40C)
(25C)
Figure 27.
Figure 28.
LINEARITY ERROR AND
ZERO-SCALE ERROR
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
vs
CODE
TEMPERATURE
(105C)
Figure 29.
Figure 30.
FULL-SCALE ERROR
I
DD
HISTOGRAM
vs
TEMPERATURE
Figure 31.
Figure 32.
11
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0
0.5
1
1.5
2
2.5
3
0
3
5
8
10
I
(SOURCE/SINK)
- mA
- Output V
oltage - V
V
OUT
DAC Loaded With 0000
H
DAC Loaded With FFFF
H
V
DD
= 2.7 V
V
REF
= V
DD
- 10 mV
0
20
40
60
80
100
120
140
160
180
0
8192
16384
24576 32768
40960
49152
57344
65536
Digital Input Code
DDI
Supply Current -
-
A
V
DD
= V
REF
= 2.7 V
Reference Current Included
100
300
500
700
0
0.5
1
1.5
2
2.5
DDI
Supply Current -
-
A
V
DD
= V
REF
= 2.7 V
T
A
= 25
C, SCL Input (All Other Inputs = GND)
V
(LOGIC)
- V
0
50
100
150
200
250
-40
-10
20
50
80
110
Quiescent Current -
A
Temperature -
5
C
V
DD
= V
REF
= 2.7 V
Reference Current Included
Time (2
s/div)
V
DD
= 2.7 V,
V
REF
= 2.5 V,
From Code: 0000
To Code: FFFF
Zoomed Rising Edge
1 mV/div
Trigger Pulse
2.7 V/div
Rising
Edge
0.5 V/div
V
DD
= 2.7 V,
V
REF
= 2.5 V,
From Code: FFFF
To Code: 0000
Zoomed Falling Edge
1 mV/div
Trigger Pulse
2.7 V/div
Falling
Edge
0.5 V/div
Time (2
s/div)
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
TYPICAL CHARACTERISTICS: V
DD
= 2.7 V (continued)
At T
A
= 25C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
SOURCE AND SINK CURRENT CAPABILITY
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
Figure 33.
Figure 34.
POWER-SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
TEMPERATURE
LOGIC INPUT VOLTAGE
Figure 35.
Figure 36.
FULL-SCALE SETTLING TIME: 2.7-V RISING EDGE
FULL-SCALE SETTLING TIME: 2.7-V FALLING EDGE
Figure 37.
Figure 38.
12
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Trigger Pulse
2.7 V/div
Zoomed Rising Edge
1 mV / div
V
DD
= 2.7 V
V
REF
= 2.5 V
From code; 4000
To code: CFFF
Rising
Edge
0.5 V/div
Time - 2
m
s/div
V
DD
= 2.7 V,
V
REF
= 2.5 V,
From Code: CFFF
To Code: 4000
Zoomed Falling Edge
1 mV/div
Trigger Pulse
2.7 V/div
Falling
Edge
0.5 V/div
Time (2
s/div)
V
DD
= 2.7 V,
V
REF
= 2.5 V
From Code: 7FFF
To Code: 8000
Glitch: 0.08 nV-s
Time 400 ns/div
V
OUT
(200
m
V/div)
V
DD
= 2.7 V,
V
REF
= 2.5 V
From Code: 8000
To Code: 7FFF
Glitch: 0.16 nV-s
Measured Worst Case
Time 400 ns/div
V
OUT
(200
m
V/div)
V
DD
= 2.7 V,
V
REF
= 2.5 V
From Code: 8000
To Code: 8010
Glitch: 0.04 nV-s
Time 400 ns/div
V
OUT
(200 uV/div)
V
DD
= 2.7 V,
V
REF
= 2.5 V
From Code: 8010
To Code: 8000
Glitch: 0.12 nV-s
Time 400 ns/div
V/div)
V
OUT
(200 uV/div)
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
TYPICAL CHARACTERISTICS: V
DD
= 2.7 V (continued)
At T
A
= 25C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
HALF-SCALE SETTLING TIME: 2.7-V RISING EDGE
HALF-SCALE SETTLING TIME: 2.7-V FALLING EDGE
Figure 39.
Figure 40.
GLITCH ENERGY: 2.7-V, 1-LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7-V, 1-LSB STEP, FALLING EDGE
Figure 41.
Figure 42.
GLITCH ENERGY: 2.7-V, 16-LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7-V, 16-LSB STEP, FALLING EDGE
Figure 43.
Figure 44.
13
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V
DD
= 2.7 V,
V
REF
= 2.5 V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
Time 400 ns/div
V
OUT
(5 mV/div)
AV
DD
= 2.7 V,
V
ref
= 2.5 V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time 400 ns/div
V
OUT
(5 mV/div)
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
TYPICAL CHARACTERISTICS: V
DD
= 2.7 V (continued)
At T
A
= 25C, unless otherwise noted. Unsigned binary equivalent inputs are shown in all figures.
GLITCH ENERGY: 2.7-V, 256-LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7-V, 256-LSB STEP, FALLING EDGE
Figure 45.
Figure 46.
14
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THEORY OF OPERATION
DAC SECTION
62
V
FB
GND
V
OUT
*
V
REF
2
)
V
REF
D
65536
(1)
To Output
Amplifier
R
R
R
R
R
RESISTOR STRING
SERIAL INTERFACE
OUTPUT AMPLIFIER
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
The architecture consists of a string DAC followed by
an output buffer amplifier.
Figure 47
shows the block
diagram of the DAC architecture.
Figure 47. DAC8550 Architecture
The input coding to the DAC8550 is 2's complement,
so the ideal output voltage is given by:
where D = decimal equivalent of the 2's complement
code that is loaded to the DAC register; D ranges
from -32768 to +32767 where D = 0 is centered at
V
REF
/2.
Figure 48. Resistor String
The resistor string section is shown in
Figure 48
. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
The DAC8550 has a 3-wire serial interface ( SYNC,
be fed into the output amplifier by closing one of the
SCLK, and D
IN
), which is compatible with SPITM,
switches connecting the string to the amplifier.
QSPITM, and MicrowireTM interface standards, as well
Monotonicity is ensured due to the string resistor
as most DSP interfaces. See the Serial Write
architecture.
Operation timing diagram for an example of a typical
write sequence.
The write sequence begins by bringing the SYNC line
The output buffer amplifier is capable of generating
LOW. Data from the D
IN
line is clocked into the 24-bit
rail-to-rail output voltages with a range of 0 V to V
DD
.
shift register on each falling edge of SCLK. The serial
It is capable of driving a load of 2
k in parallel with
clock frequency can be as high as 30 MHz, making
1000 pF to GND. The source and sink capabilities of
the DAC8550 compatible with high-speed DSPs. On
the output amplifier can be seen in the typical curves.
the 24th falling edge of the serial clock, the last data
The slewrate is 1.8 V/s with a full-scale setting time
bit is clocked in and the programmed function is
of 8 s with the output unloaded.
excuted (i.e., a change in DAC register contents
The inverting input of the output amplifier is brought
and/or a change in the mode of operation).
out to the V
FB
pin. This allows for better accuracy in
At this point, the SYNC line may be kept LOW or
critical applications by tying the V
FB
point and the
brought HIGH. In either case, it must be brought
amplifier output together directly at the load. Other
HIGH for a minimum of 33 ns before the next write
signal conditioning circuitry may also be connected
sequence so that a falling edge of SYNC can initiate
between these points for specific applications.
the next write sequence. Since the SYNC buffer
draws more current when the SYNC signal is HIGH
15
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SYNC INTERRUPT
INPUT SHIFT REGISTER
POWER-ON RESET
CLK
SYNC
D
IN
Valid Write Sequence: Output Updates
on the 24th Falling Edge
24th Falling Edge
24th Falling Edge
DB23
DB80
DB23
DB80
POWER-DOWN MODES
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
than it does when it is LOW, SYNC should be idled
LOW between write sequences for lowest power
In a normal write sequence, the SYNC line is kept
operation of the part. As mentioned above, it must be
LOW for at least 24 falling edges of SCLK and the
brought HIGH again just before the next write
DAC is updated on the 24th falling edge. However, if
sequence.
SYNC is brought HIGH before the 24th falling edge, it
acts as an interrupt to the write sequence. The shift
register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register
The input shift register is 24 bits wide, as shown in
contents nor a change in the operating mode occurs,
Figure 49
. The first six bits are don't care bits. The
as shown in
Figure 50
.
next two bits (PD1 andPD0) are control bits that
control which mode of operation the part is in (normal
mode or any one of three power-down modes). For a
more complete description of the various modes see
The DAC8550 contains a power-on reset circuit that
the Power-Down Modes section. The next 16 bits are
controls the output voltage during power-up. On
the data bits. These are transferred to the DAC
power-up, the output voltages are set to midscale; it
register on the 24th falling edge of SCLK.
remains there until a valid write sequence is made to
the DAC. This is useful in applications where it is
important to know the state of the output of the DAC
while it is in the process of powering up.
DB23
DB0
X
X
X
X
X
X
PD1
PD0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 49. DAC8550 Data Input Register Format
Figure 50. SYNC Interrupt Facility
at 5 V. However, for the three power-down modes,
the supply current falls to 200 nA at 5 V (50 nA at 3
V). Not only does the supply current fall, but the
The DAC8550 supports four seperate modes of
output stage is also internally switched from the
operation. These modes are programmable by setting
output of the amplifier to a resistor network of known
two bits (PD1 and PD0) in control register.
Table 1
values. The advantage with this is that the output
shows how the state of the bits corresponds to the
impedance
of
the
device
is
known
while
in
mode of operation of the device.
power-down mode. There are three different options.
The output is connected internally to GND through a
Table 1. Modes of Operation for the DAC8550
1-k
resistor,
a
100-k
resistor,
or
it
is
left
open-circuited (High-Z). The output stage is illustrated
PD1
PD0
OPERATING MODE
(DB17)
(DB16)
in
Figure 51
.
0
0
Normal operation
All
analog
circuitry
is
shut
down
when
the
--
--
Power-down modes
power-down
mode
is
activated.
However,
the
0
1
Output typically 1 k
to GND
contents of the DAC register are unaffected when in
power-down. The time to exit power-down is typically
1
0
Output typically 100 k
to GND
2.5 s for V
DD
= 5 V, and 5 s for V
DD
= 3 V. See the
1
1
High-Z
Typical Characteristics for more information.
When both bits are set to 0, the device works
normally with a typical current consumption of 200 A
16
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DAC8550 to Microwire Interface
Amplifier
Power-Down
Circuitry
Resistor
Network
V
OUT
V
FB
Resistor
String DAC
SYNC
SCLK
D
IN
Microwire
TM
CS
SK
SO
DAC8550
(1)
NOTE: (1) Additional pins omitted for clarity.
MICROPROCESSOR INTERFACING
DAC8550 TO 8051 Interface
DAC8550 to 68HC11 Interface
68HC11
(1)
PC7
SCK
MOSI
SYNC
SCLK
D
IN
(1)
NOTE: (1) Additional pins omitted for clarity.
DAC8550
80C51/80L51
(1)
P3.3
TXD
RXD
(1)
SYNC
SCLK
D
IN
DAC8550
NOTE: (1) Additional pins omitted for clarity.
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
Figure 53
shows an interface between the DAC8550
and any Microwire compatible device. Serial data is
shifted out on the falling edge of the serial clock and
is clocked into the DAC8550 on the rising edge of the
SK signal.
Figure 51. Output Stage During Power-Down
Figure 53. DAC8550 to Microwire Interface
See
Figure 52
for a serial interface between the
Figure 54
shows a serial interface between the
DAC8550 and a typical 8051-type microcontroller.
DAC8550 and the 68HC11 microcontroller. SCK of
The setup for the interface is as follows: TXD of the
the 68HC11 drives the SCLK of the DAC8550, while
8051 drives SCLK of the DAC8550, while RXD drives
the MOSI output drives the serial data line of the
the serial data line of the device. The SYNC signal is
DAC. The SYNC signal is derived from a port line
derived from a bit-programmable pin on the port of
(PC7), similar to the 8051 diagram.
the 8051. In this case, port line P3.3 is used. When
data is to be transmitted to the DAC8550, P3.3 is
taken LOW. The 8051 transmits data in 8-bit bytes;
thus only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
LOW after the first eight bits are transmitted, then a
second write cycle is initiated to transmit the second
byte of data. P3.3 is taken HIGH following the
completion of the third write cycle. The 8051 outputs
Figure 54. DAC8550 to 68HC11 Interface
the serial data in a format which has the LSB first.
The DAC8550 requires its data with the MSB as the
first bit received. The 8051 transmit routine must
The 68HC11 should be configured so that its CPOL
therefore take this into account, and mirror the data
bit is 0 and its CPHA bit is 1. This configuration
as needed.
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data is being
transmitted to the DAC, the SYNC line is held LOW
(PC7). Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. (Data is transmitted
MSB first.) In order to load data to the DAC8550,
PC7 is left LOW after the first eight bits are
transferred, then a second and third serial write
Figure 52. DAC8550 to 80C51/80L51 Interface
operation is performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
17
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APPLICATION INFORMATION
USING THE REF02 AS A POWER SUPPLY
V
O
V
REF
2
)
V
REF
D
65536
R1
)
R2
R1
*
V
REF
R2
R1
V
O
)
10
D
65536
(4)
LAYOUT
REF02
Three-Wire
+5V
285
A
m
V
OUT
= 0 V to 5 V
SYNC
SCLK
D
IN
+15
Serial
Interface
DAC8550
200
m
A
5 V
5 k
W
)
1.2 mA
(2)
BIPOLAR OPERATION USING THE DAC8550
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
FOR THE DAC8550
where D represents the input code in 2's complement
Due to the extremely low supply current required by
(-32768 to +32767).
the DAC8550, an alternative option is to use a REF02
+5 V precision voltage reference to supply the
With V
REF
= 5 V, R1 = R2 = 10 k
.
required voltage to the device, as shown in
Figure 55
.
This is an output voltage range of 5 V with 8000
H
corresponding
to
a
5
V
output
and
8FFF
H
corresponding to a 5 V output. Similarly, using V
REF
=
2.5 V a 2.5 V output voltage range can be achieved.
A precision analog component requires careful layout,
adequate bypassing, and clean, well-regulated power
supplies.
The DAC8550 offers single-supply operation and is
used often in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
Figure 55. REF02 as a Power Supply to the
design and the higher the switching speed the more
DAC8550
difficult it is to keep digital noise from appearing at
the output.
This is especially useful if the power supply is quite
Due to the single ground pin of the DAC8550 all
noisy or if the system supply voltages are at some
return currents, including digital and analog return
value other than 5 V. The REF02 outputs a steady
currents for the DAC, must flow through a single
supply voltage for the DAC8550. If the REF02 is
point. Ideally, GND would be connected directly to an
used, the current it needs to supply to the DAC8550
analog ground plane. This plane would be separate
is 250 A. This is with no load on the output of the
from
the
ground
connection
for
the
digital
DAC. When a DAC output is loaded, the REF02 also
components
until
they
were
connected
at
the
needs to supply the current to the load. The total
power-entry point of the system.
typical current required (with a 5 k
load on the DAC
output) is:
The power applied to V
DD
should be well regulated
and have low noise. Switching power supplies and
DC/DC converters often has high-frequency glitches
or spikes riding on the output voltage. In addition,
The load regulation of the REF02 is typically
digital components can create similar high-frequency
0.005%/mA, which results in an error of 299 V for
spikes as their internal logic switches states. This
the 1.2 mA current drawn from it. This corresponds to
noise can easily couple into the DAC output voltage
a 8.9 LSB error.
through
various
paths
between
the
power
connections and analog output.
As
with
the
GND
connection,
V
DD
should
be
The DAC8550 has been designed for single-supply
connected to a 5 V power-supply plane or trace that
operation, but a bipolar output range is also possible
is separate from the connection for digital logic until
using the circuit in
Figure 56
. The circuit shown gives
they are connected at the power-entry point. In
an
output
voltage
range
of
V
REF
.
Rail-to-rail
addition, a 1 F to 10 F capacitor and 0.1 F bypass
operation at the amplifier output is achievable using
capacitor
are
strongly
recommended.
In
some
an OPA703 as the output amplifier.
situations, additional bypassing may be required,
such as a 100 F electrolytic capacitor or even a Pi
The output voltage for any input code can be
filter made up of inductors and capacitors, all
calculated as follows:
designed to essentially low-pass filter the 5 V supply,
removing the high-frequency noise.
18
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DAC8550
V
REF
V
OUT
V
FB
R1
R2
10 kW
10 kW
V
REF
10
F
m
0.1
F
m
5 V
5 V
+5 V
OPA703
Three-Wire
Serial Interface
DAC8550
SLAS476C MARCH 2006 REVISED MARCH 2006
Figure 56. Bipolar Output Range
19
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
DAC8550IBDGKR
ACTIVE
MSOP
DGK
8
2500
TBD
Call TI
Call TI
DAC8550IBDGKT
ACTIVE
MSOP
DGK
8
250
TBD
Call TI
Call TI
DAC8550IDGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DAC8550IDGKT
ACTIVE
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Apr-2006
Addendum-Page 1
IMPORTANT NOTICE
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amplifier.ti.com
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interface.ti.com
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logic.ti.com
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power.ti.com
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microcontroller.ti.com
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