DAC
858
1
Burr Brown Products
from Texas Instruments
FEATURES
DESCRIPTION
APPLICATIONS
Serial Interface
Shift Register
Control
Logic
SCLK
DAC
Latch
DAC
SDIN
AV
SS
DV
DD
GND
V
REF
V
OUT
AV
DD
DAC8581
CS
CLR
DAC8581
SLAS481A AUGUST 2005 REVISED AUGUST 2005
16-BIT, HIGH-SPEED, LOW-NOISE, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
16-Bit Monotonic
DAC8581 is a 16-bit, high-speed, low-noise DAC
operating from dual
5-V power supplies. DAC8581 is
5-V Rail-to-Rail Output
monotonic, has exceptionally low noise and excep-
Very Low Glitch: 0.5 nV-s
tionally low glitch. The DAC8581's high-performance,
Fast Settling: 0.65
s
rail-to-rail output buffer is capable of settling within
Fast Slew Rate: 35 V/
s
0.65
s for a 10-V step. Small-signal settling time is
well under 0.3
s, supporting data update rates up to
Low Noise: 20 nV/
Hz
3 MSPS. A power-on-reset circuit sets the output at
25-mA Load Drive
midscale voltage on power up.
5-V Dual Power Supply
The DAC8581 is simple to use, with a single external
Single External Reference
reference and a standard 3-wire SPI interface that
Power-On Reset to Midscale
allows clock rates up to 50 MHz.
3-MSPS Update Rate
Also see the DAC8580, a member of the same
family. The DAC8580 combines DAC8581 perform-
SPI Interface, Up to 50 MHz
ance with an on-chip, 16X over-sampling digital filter.
1.8 V5 V Logic Compatible
The DAC8581 is specified over 40
C-to-85
C tem-
2s Complement Data Format
perature range.
Hardware Reset to Midscale
TSSOP-16 Package
Industrial Process Control
CRT Projection TV Digital Convergence
Waveform Generation
Automated Test Equipment
Ultrasound
FUNCTIONAL BLOCK DIAGRAM OF DAC8581
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
DAC8581
SLAS481A AUGUST 2005 REVISED AUGUST 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications. This device is rated at 1500 V HBM and 1000
V CDM.
PACKAGE/ORDERING INFORMATION
(1)
PACKAGE
SPECIFICATION
PACKAGE
ORDERING
PRODUCT
PACKAGE
DRAWING
TEMPERATURE
ORDERING
TRANSPORT MEDIA
NUMBER
NUMBER
RANGE
MARKING
DAC8581IPW
90-Piece Tube
DAC8581
16-TSSOP
PW
40
C to 85
C
D8581I
DAC8581IPWR
2000-Piece Tape and Reel
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at
www.ti.com
.
UNIT
AV
DD
or DV
DD
to AV
SS
0.3 V to 12 V
Digital iput voltage to AV
SS
0.3 V to 12 V
V
OUT
or V
REF
to AV
SS
0.3 V to 12 V
DGND and AGND to AV
SS
0.3 V to 6 V
Operating temperature range
40
C to 85
C
Storage temperature range
65
C to 150
C
Junction temperature range (T
J
max)
150
C
Thermal impedance (
JA
)
118
C/W
Power dissipation
Thermal impedance (
JC
)
29
C/W
Vapor phase (60s)
215
C
Lead temperature, soldering
Infrared (15s)
220
C
(1)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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ELECTRICAL CHARACTERISTICS
DAC8581
SLAS481A AUGUST 2005 REVISED AUGUST 2005
All specifications at T
A
= T
MIN
to T
MAX
, +AV
DD
= +5 V, AV
DD
= 5 V, DV
DD
= +5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
Resolution
16
Bits
Linearity error
V
REF
= 4.096 V
0.03
0.1
%FS
Differential linearity error
0.25
0.5
LSB
Gain error
1
2
3
%FS
Gain drift
5
ppm/
C
Bipolar zero error
5
25
mV
Bipolar zero drift
20
V/
C
Total drift
10
ppm/
C
OUTPUT CHARACTERISTICS
Voltage output
(1)
V
REF
up to 6 V, when AV
DD
= 6 V, AV
SS
= 6 V
V
REF
V
REF
V
Output impedance
1
Maximum output current
25
mA
C
L
<200 pF, R
L
= 2 k
, to 0.1% FS, 8-V step
0.65
Settling time
s
To 0.003% FS
1
Slew rate
(2)
35
V/
s
Code change glitch
1 LSB change around major carry
0.5
nV-S
Overshoot
Full-scale change
50
mV
Digital feedthrough
(3)
0.5
nV-S
SNR
Digital sine wave input, Fout = 1 kHz,
108
dB
BW = 10 kHz, 2 MSPS update rate
THD
Digital sine wave input, Fout = 20 kHz,
72
dB
8-Vpp output, 2-MSPS update rate
0.1 Hz to 10 Hz
25
Vpp
Output voltage noise
At 10-kHz offset frequency
25
nV/rtHz
At 100-kHz offset frequency
20
nV/rtHz
Power supply rejection
VDD varies
10%
0.75
mV/V
REFERENCE
Large signal: 2-Vpp sine wave on 4 V DC
3
MHz
Reference input bandwidth
Small signal: 100-mVpp sine wave on 4 V DC
10
MHz
Reference input voltage range
3
AV
DD
V
Reference input impedance
5
k
Reference input capacitance
5
pF
DIGITAL INPUTS
V
IH
0.7 x DV
DD
V
V
IL
GND
0.3 x DV
DD
Input current
1
A
Input capacitance
10
pF
Power-on delay
From V
DD
high to CS low
20
s
(1)
Output can reach
V
DD
unloaded, can reach
(V
DD
0.2 V) for 600-
loading.
(2)
Slew rate is measure from 10% to 90% of transition when the output changes from 0 to full scale.
(3)
Digital feedthrough is defined as the impulse injected into the analog output from the digital input. It is measured when the DAC output
does not change, CS is held high, and while SCLK and SDIN signals are toggled.
3
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PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
REF
V
OUT
AV
SS
AV
DD
AGND
DGND
DGND
DGND
DV
DD
DGND
CLR
DV
DD
DGND
CS
SCLK
SDIN
(TOP VIEW)
DAC8581
SLAS481A AUGUST 2005 REVISED AUGUST 2005
ELECTRICAL CHARACTERISTICS (continued)
All specifications at T
A
= T
MIN
to T
MAX
, +AV
DD
= +5 V, AV
DD
= 5 V, DV
DD
= +5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
+AV
DD
4.0
5
6.0
V
AV
DD
4.0
5
6.0
V
DV
DD
1.8
AV
DD
V
I
DVDD
10
20
A
I
DD
Iref and IDV
DD
included
17
24
mA
I
SS
23
32
mA
TEMPERATURE RANGE
Specified performance
40
85
C
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
V
REF
1
Reference input voltage.
VOUT
2
DAC output voltage. Output swing is
V
REF
AV
SS
3
Negative analog supply voltage, tie to 5 V
AV
DD
4
Positive analog supply voltage, tie to +5 V
AGND
5
The ground reference point of all analog circuitry of the device. Tie to 0 V.
DGND
6, 7, 8, 15
Tie to DGND to ensure correct operation.
SDIN
9
Digital input, serial data. Ignored when CS is high.
SCLK
10
Digital input, serial bit clock. Ignored when CS is high.
Digital input. Chip Select (CS) signal. Active low. When CS is high, SCLK and SDI are ignored. When CS is low,
CS
11
data can be transferred into the device.
DGND
12
Ground reference for digital circuitry. Tie to 0 V.
DV
DD
13
Positive digital supply, 1.8 V5.5 V compatible
Digital input for forcing the output to midscale. Active low. When pin CLR is low during 16
th
SCLK following the
falling edge of CS, the falling edge of 16
th
SCLK sets DAC Latch to midcode, and the DAC output to 0 V. When
CLR
14
pin CLR is High, the falling edge of 16th SCLK updates DAC latch with the value of input shift register, and
changes DAC output to corresponding level.
DV
DD
16
Tie to DV
DD
to ensure correct operation.
4
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TIMING REQUIREMENTS
(1)
SCLK
t
Lead
t
wsck
t
wsck
t
r
t
f
-- Don"t Care
BIT-14
BIT-13, !, 1
BIT-15 (MSB)
BIT-0
SDIN
t
hi
t
su
DAC Updated
t
UPDAC
1st
2nd
15th
16th
t
td
CS
t
sck
t
WAIT
TYPICAL CHARACTERISTICS
-20
-15
-10
-5
0
5
10
15
20
0
8192
16384
24576
32768
40960
49152
57344
65536
Input Code
LE - LSBs
-0.5
-0.25
0
0.25
0.5
0
8192
16384
24576
32768
40960
49152
57344
65536
Input Code
DLE - LSBs
DAC8581
SLAS481A AUGUST 2005 REVISED AUGUST 2005
PARAMETER
MIN
MAX
UNIT
t
sck
SCLK period
20
ns
t
wsck
SCLK high or low time
10
ns
t
Lead
Delay from falling CS to first rising SCLK
20
ns
t
td
CS High between two active Periods
20
ns
t
su
Data setup time (Input)
5
ns
t
h
i
Data hold time (input)
5
ns
t
r
Rise time
30
ns
t
f
Fall time
30
ns
t
wait
Delay from 16
th
falling edge of SCLK to CS low
100
ns
t
UPDAC
Delay from 16
th
falling edge of SCLK to DAC output
1
s
V
DD
High to CS Low (power-up delay)
100
s
(1)
Assured by design. Not production tested.
Figure 1. DAC8581 Timing Diagram
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
INPUT CODE
INPUT CODE
Figure 2.
Figure 3.
5
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-30
-20
-10
0
10
20
30
3
3.5
4
4.5
5
5.5
INL - LSBs
V
REF
- Reference Voltage - V
INL max
INL min
AV
DD
= 6 V,
AV
SS
= -6 V
-30
-20
-10
0
10
20
30
3
3.5
4
4.5
5
5.5
6
INL - LSBs
INL max
INL min
AV
SS
= -AV
DD
,
V
REF
= AV
DD
-0.3 V
AV
DD
- Supply Voltage - V
185
187
189
191
193
-40
-20
0
20
40
60
80
T
A
- Free-Air Temperature -
5
C
Gain Error - mV
AV
DD
= 5 V,
AV
SS
= 5 V,
V
REF
= 4.096 V
-4
-2
0
2
4
-40
-20
0
20
40
60
80
T
A
- Free-Air Temperature -
5
C
Offset Error - mV
AV
DD
= 5 V,
AV
SS
= 5 V,
V
REF
= 4.096 V
10
15
20
25
-40
-20
0
20
40
60
80
T
A
- Free-Air Temperature -
C
I DD
- Supply Current - mA
-25
-23
-21
-19
-17
-15
-13
-11
-40
-20
0
20
40
60
80
T
A
- Free-Air Temperature -
C
I SS
- Supply Current - mA
DAC8581
SLAS481A AUGUST 2005 REVISED AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
INTEGRAL NONLINEARITY ERROR
INTEGRAL NONLINEARITY ERROR
vs
vs
VREF
SUPPLY VOLTAGE
Figure 4.
Figure 5.
OFFSET ERROR
GAIN ERROR
vs
vs
TEMPERATURE
TEMPERATURE
Figure 6.
Figure 7.
POSITIVE SUPPLY CURRENT - I
DD
NEGATIVE SUPPLY CURRENT - I
SS
vs
vs
TEMPERATURE
TEMPERATURE
Figure 8.
Figure 9.
6
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-21
-20.5
-20
-19.5
-32768
-16384
0
16384
32768
Code
I SS
- Supply Current - mA
13
13.5
14
14.5
15
-32768
-16384
0
16384
32768
Code
I DD
- Supply Current - mA
t - Time - 50 ns
mV - 50 mV/div
t - Time - 1
s
V - 2 V/div
t - Time - 1
s
Feedthrough
FSYNC
Glitch
mV - 10 mV/div
1
10
100
1 k
100 k
10
100
1 k
10 k
100 k
10 k
- Output Noise V
oltage -
V
n
nV/
Hz
f - Frequency - Hz
DAC8581
SLAS481A AUGUST 2005 REVISED AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
POSITIVE SUPPLY CURRENT - I
DD
NEGATIVE SUPPLY CURRENT - I
SS
vs
vs
CODE
CODE
Figure 10.
Figure 11.
LARGE-SIGNAL SETTLING
SMALL-SIGNAL SETTLING
Figure 12.
Figure 13.
DIGITAL FEEDTHROUGH AND MIDCODE GLITCH
OUTPUT VOLTAGE NOISE
Figure 14.
Figure 15.
7
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-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0
2000
4000
6000
Gain - dB
f - Frequency - Hz
Fo = 1 kHz,
Fclk = 192 KSPS,
OSR = 1,
THD = -71 dB,
SNR = 113 dBFS,
Digitizer = Delta-Sigma
-140
-120
-100
-80
-60
-40
-20
0
0
1000
2000
3000
4000
5000
6000
f - Frequency - Hz
Code - dB
Fo = 1 kHz,
Fs = 192 KSPS
-4
-3
-2
-1
0
1
2
3
4
0
16384
32768
49152
65536
Input Code
LE - LSBs
DAC8581
SLAS481A AUGUST 2005 REVISED AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
POWER SPECTRAL DENSITY
SOFTWARE-TRIMMED UNIT
FROM DC TO 6 kHz
POWER SPECTRAL DENSITY
Figure 16.
Figure 17.
SOFTWARE-TRIMMED UNIT
LINEARITY ERROR
vs
INPUT CODE
Figure 18.
8
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THEORY OF OPERATION
Supply Pins
Reference Input Voltage
Output Voltage
DAC8581
SLAS481A AUGUST 2005 REVISED AUGUST 2005
DAC8581 uses proprietary, monotonic, high-speed resistor string architecture. The 16-bit input data is coded in
twos complement, MSB-first format and transmitted using a 3-wire serial interface. The serial interface sends the
input data to the DAC latch. The digital data is then decoded to select a tap voltage of the resistor string. The
resistor string output is sent to a high-performance output amplifier. The output buffer has rail-to-rail (
5 V) swing
capability on a 600-
, 200-pF load. The resistor string DAC architecture provides exceptional differential linearity
and temperature stability whereas the output buffer provides fast-settling, low-glitch, and exceptionally low
idle-channel noise. The DAC8581 settles within 1
s for large input signals. Exceptionally low glitch (0.5 nV-s) is
attainable
for
small-signal,
code-to-code
output
changes.
Resistor
string
architecture
also
provides
code-independent power consumption and code-independent settling time. The DAC8581 resistor string needs
an external reference voltage to set the output voltage range of the DAC. To aid fast settling, VREF input is
internally buffered.
DAC8581 uses
5-V analog power supplies (AV
DD
, AV
SS
) and a 1.8 V5.5 V digital supply (DV
DD
). Analog and
digital ground pins (AGND and DGND) are also provided. For low-noise operation, analog and digital power and
ground pins should be separated. Sufficient bypass capacitors, at least 1
F, should be placed between AV
DD
and AV
SS
, AV
SS
and DGND, and DV
DD
and DGND pins. Series inductors are not recommended on the supply
paths. The digital input pins should not exceed the ground potential during power up. During power up, AGND
and DGND are first applied with all digital inputs and the reference input kept zero volts. Then, AV
DD
, DV
DD
,
AV
SS
, and V
REF
should be applied together. Care should be taken to avoid applying V
REF
before AV
DD
and AV
SS
.
All digital pins must be kept at ground potential before power up.
The reference input pin V
REF
is typically tied to a +3.3 V, +4.096 V, or +5.0 V external reference. A bypass
capacitor 0.1
F or less is recommended depending on the load-driving capability of the voltage reference. To
reduce crosstalk and improve settling time, the V
REF
pin is internally buffered by a high-performance amplifier.
The V
REF
pin has constant 5-k
impedance to AGND. The output range of the DAC8581 is equal to
V
REF
voltage. The V
REF
pin should be powered at the same time, or after the supply pins. REF3133 and REF3140 are
recommended to set the DAC8581 output range to
3.3 V and
4.096 V, respectively.
The input data format is in twos-complement format as shown in
Table 1
. DAC8581 uses a high-performance,
rail-to-rail output buffer capable of driving a 600-
, 200-pF load with fast 0.65-
s settling. The buffer has
exceptional noise performance (20 nV/
Hz) and fast slew rate (35 V/
s). The small-signal settling time is under
300 ns, allowing update rates up to 3 MSPS. Loads of 50
or 75
could be driven as long as output current
does not exceed
25 mA continuously. Long cables, up to 1 nF in capacitance, can be driven without the use of
external buffers. To aid stability under large capacitive loads (>1 nF), a small series resistor can be used at the
output.
Table 1. Data Format
DIGITAL CODE
DAC OUTPUT
BINARY
HEX
+Vref
0111111111111111
7FFF
+Vref/2
0100000000000000
4FFF
0
0000000000000000
0000
Vref/2
1011111111111111
BFFF
Vref
1000000000000000
8000
9
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SERIAL INTERFACE
Pin CLR
SCLK
CS
SDIN
DAC8581
SLAS481A AUGUST 2005 REVISED AUGUST 2005
Glitch area is low at 0.5 nV-s, with peak glitch amplitude under 10 mV, and the glitch duration under 100 ns. Low
glitch is obtained for code-to-code (small signal) changes across the entire transfer function of the device. For
large signals, settling characteristics of the reference and output amplifiers are observed in terms of overshoot
and undershoot.
Combined with
5-V output range, and extremely good noise performance, the outstanding differential linearity
performance of this device becomes significant. That is, each DAC step can be clearly observed at the DAC
output, without being corrupted by wideband noise.
The DAC8581 serial interface consists of the serial data input pin SDIN, bit clock pin SCLK, and chip-select pin
CS. The serial interface is designed to support the industry standard SPI interface up to 50 MHz. The serial
inputs are 1.8-V to 5.5-V logic compatible.
CS operates as an active-low, chip-select signal. The falling edge of CS initiates the data transfer. Each rising
edge of SCLK following the falling edge of CS shifts the SDIN data into a 16-bit shift register, MSB-first. At the
16
th
rising edge of SCLK, the shift register becomes full and the DAC data updates on the falling edge that
follows the 16
th
rising edge. After the data update, further clocking gets ignored. The sequence restarts at the
next falling edge of CS. If the CS is brought high before the DAC data is updated, the data is ignored. See the
Figure 1
timing diagram for details.
Pin CLR is implemented to set the DAC output to 0 V. When the CS pin is low during the 16th SCLK cycle
following the falling edge of CS, the falling edge of 16
th
SCLK sets the DAC latch to midcode, and the DAC
output to 0 V. If the CLR pin is high during the 16
th
clock, the falling edge of 16th clock updates the DAC latch
with the input data. Therefore, if the CLR pin is brought back to High from Low during serial communication, the
DAC output stays at 0 V until the falling edge of the next 16th clock is received. The CLR pin is active low. The
CLR low does not affect the serial data transfer. The serial data input does not get interrupted or lost while the
output is set at midscale.
This digital input pin is the serial bit-clock. Data is clocked in the device at the rising edge of SCLK.
This digital input pin is the chip-select signal. When CS is low, the serial port is enabled and data can be
transferred into the device. When CS is high, all SCLK and SDIN signals are ignored.
This digital input is the serial data input. Serial data is shifted on the rising edge of the SCLK when CS is low.
10
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APPLICATION INFORMATION
IMPROVING DAC8581 LINEARITY USING EXTERNAL CALIBRATION
MCU
DAC8581
Lookup
Table
(FLASH)
MCU
DAC8581
Lookup
Table
(FLASH)
DVM
Board
Tester
Computer
Board
Tester (ATE)
DAC8581
SLAS481A AUGUST 2005 REVISED AUGUST 2005
At output frequencies up to 50 kHz, DAC8581 linearity error and total harmonic distortion are dominated by
resistor mismatches in the string. These resistor mismatches are fairly insensitive to temperature and aging
effects and also to reference voltage changes. Therefore, it is possible to use a piece-wise linear (PWL)
approximation to cancel linearity errors, and the calibration will remain effective for different supply and Vref
voltages, etc. The cancellation of linearity errors also improves the total harmonic distortion (THD) performance.
It is possible to improve the integral linearity errors from
25 LSB to
1 LSB and the THD from 70 dB to almost
98 dB (see
Figure 17
and
Figure 18
). The improvements are at the expense of ~2X DNL deterioration, which is
not critical for the generation of large-signal waveforms.
Figure 19. A Simple Printed-Circuit Board Scheme for Calibrated Use of DAC8581
Figure 20. Production Test Setup for a DAC8581 Board With Calibration
The PWL calibration scheme uses a DAC8581 and a microcontroller unit (MCU) with flash memory, on a
printed-circuit board as seen in
Figure 19
. Calibration is done during board test, and the calibration coefficients
are stored permanently in flash memory as seen in
Figure 20
. An automated board tester is assumed to have a
precision digital voltmeter (DVM) and a tester computer. The test flow for a 1024-segment, piece-wise linear
calibration is as follows:
1. Use the tester computer to load software into the MCU to ramp the DAC8581 and
take a reading at each step after a short wait time
store 65,536 readings in tester computer's volatile memory
2. Use the tester computer to
search the 65,536-point capture data and find the actual DAC8581 codes which would generate ideal
DAC outputs for DAC input codes 0, 64, 128, 192,
...
.
store these actual codes in the onboard microcontroller's flash memory in a 1025-point array called
COEFF[].
3. Use the tester computer to program the MCU such that, when the end-user provides new 16-bit input data
D0 to the MCU
The 10 MSBs of D0 directly index the array COEFF[].
The content of indexed memory of COEFF and the content of the next higher memory location are
placed in variables I1 and I2.
The 6 LSBs of the user data D0 with two variables I1 and I2 are used for computing
Equation 1
(See
Figure 21
).
Instead of D0, I0 is loaded to DAC8581
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VI1
VI0
VI2
I1
I0
I2
Main !DAC Transfer Curve
VI0B
PWL Segment
I0B
Ideal!DAC Transfer Curve
I0
+
I1
)
(I2
*
I1)(D0
*
VI1)
VI2
*
VI1
(1)
DAC8581
SLAS481A AUGUST 2005 REVISED AUGUST 2005
APPLICATION INFORMATION (continued)
Figure 21. The Geometry Behind the PWL Calibration
Where both x-axis and y-axis are normalized from 0 to 65535, and,
VI0: Desired ideal DAC voltage corresponding to input code D0.
VI0B: DAC8581 output voltage, which approximates VI0 after PWL calibration. This is the actual DAC8581
output for input code D0 after PWL calibration.
I0: DAC8581 code generating VI0B, an approximation to the desired voltage VI0. This is actual code
loaded into DAC latch for input code D0, after PWL calibration.
I0B: DAC8581 code, which generates output VI0. This code is approximated by the N-segment PWL
calibration.
I1: Contents of memory COEFF, addressed by the 10 MSBs of user input code D0.
I2: Contents of the next memory location in COEFF.
VI1: DAC8581 output voltage corresponding to code I1. Notice that (D0VI1) is nothing but the 6 LSBs of
the input code D0, given that the y-axis is normalized from 0 to 65,536.
VI2: DAC8581 output voltage corresponding to code I2. Notice that (VI2VI1) is always equal to number 64,
given that the y-axis is normalized from 0 to 65,536. Division becomes a 6-bit arithmetic right shift.
Other similar PWL calibration implementations exist. This particular algorithm does not need digital division, and
it does not accumulate measurement errors at each segment.
12
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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