Burr Brown Products
from Texas Instruments
FEATURES
DESCRIPTION
APPLICATIONS
D/A
Converter
DAC
Register
Shift
Register
14
14
R
FB
I
OUT
GND
V
DD
V
REF
CS
CLK
SDI
DAC8801
DAC8801
SLAS403A NOVEMBER 2004 REVISED DECEMBER 2004
14-Bit, Serial Input Multiplying Digital-to-Analog Converter
14-Bit Monotonic
The DAC8801 multiplying digital-to-analog converter
is designed to operate from a single 2.7-V to 5.5-V
1 LSB INL
supply.
0.5 LSB DNL
The applied external reference input voltage V
REF
Low Noise: 12 nV/
Hz
determines the full-scale output current. An internal
Low Power: I
DD
= 2 A
feedback resistor (R
FB
) provides temperature tracking
+2.7 V to +5.5 V Analog Power Supply
for the full-scale output when combined with an
external I-to-V precision amplifier.
2 mA Full-Scale Current
20%
with V
REF
= 10 V
A serial-data interface offers high-speed, three-wire
0.5 s Settling Time
microcontroller compatible inputs using data-in (SDI),
clock (CLK), and chip select (CS).
4-Quadrant Multiplying Reference-Input
Reference Bandwidth: 10 MHz
The DAC8801 is packaged in space-saving 8-lead
SON and MSOP packages.
10 V Reference Input
Reference Dynamics: -105 THD
3-Wire 50-MHz Serial Interface
Tiny 8-Lead 3 x 3 mm SON and 3 x 5 mm
MSOP Packages
Industry-Standard Pin Configuration
Automatic Test Equipment
Instrumentation
Digitally Controlled Calibration
Industrial Control PLCs
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
DAC8801
SLAS403A NOVEMBER 2004 REVISED DECEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
(1)
MINIMUM
RELATIVE
DIFFERENTIAL
SPECIFIED
TRANSPORT
ACCURACY
NONLINEARITY
PACKAGE-
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
MEDIA,
PRODUCT
(LSB)
(LSB)
LEAD
DESIGNATOR
RANGE
MARKING
NUMBER
QUANTITY
Tape and Reel,
DAC8801
1
0.5
MSOP-8
DGK
-40
C to +85
C
F01
DAC8801IDGKT
250
Tape and Reel,
DAC8801
1
0.5
MSOP-8
DGK
-40
C to +85
C
F01
DAC8801IDGKR
2500
Tape and Reel,
DAC8801
1
0.5
SON-8
DRB
-40
C to +85
C
E01
DAC8801IDRBT
250
Tape and Reel,
DAC8801
1
0.5
SON-8
DRB
-40
C to +85
C
E01
DAC8801IDRBR
2500
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our
web site at www.ti.com.
over operating free-air temperature range (unless otherwise noted)
DAC8801
UNITS
V
DD
to GND
-0.3 to +7
V
Digital Input voltage to GND
-0.3 to +V
DD
+ 0.3
V
V
OUT
to GND
-0.3 to +V
DD
+ 0.3
V
Operating temperature range
-40 to +105
C
Storage temperature range
-65 to +150
C
Junction temperature range (T
J
max)
+125
C
Power dissipation
(T
J
max - T
A
) / R
JA
W
Thermal impedance, R
JA
+55
C/W
Lead temperature, soldering
Vapor phase (60s)
+215
C
Lead temperature, soldering
Infrared (15s)
+220
C
ESD rating, HBM
1500
V
ESD rating, CDM
1000
V
(1)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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ELECTRICAL CHARACTERISTICS
DAC8801
SLAS403A NOVEMBER 2004 REVISED DECEMBER 2004
V
DD
= +2.7 V to +5.5 V; I
OUT
= Virtual GND, GND = 0 V; V
REF
= 10 V; T
A
= Full Operating Temperature; all specifications
-40
C to +85
C unless otherwise noted.
DAC8801
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
14
Bits
Relative accuracy
1
LSB
Differential nonlinearity
0.5
LSB
Output leakage current
Data = 0000h, T
A
= 25
C
10
nA
Output leakage current
Data = 0000h, T
A
= T
MAX
10
nA
Full-scale gain error
All ones loaded to DAC register
1
4
mV
Full-scale tempco
3
ppm of FSR/
C
OUTPUT CHARACTERISTICS
(1)
Output current
2
mA
Output capacitance
Code dependent
50
pF
REFERENCE INPUT
VREF Range
-15
15
V
Input resistance
5
k
Input capacitance
5
pF
LOGIC INPUTS AND OUTPUT
(1)
Input low voltage
V
IL
V
DD
= +2.7V
0.6
V
Input low voltage
V
IL
V
DD
= +5V
0.8
V
Input high voltage
V
IH
V
DD
= +2.7V
2.1
V
Input high voltage
V
IH
V
DD
= +5V
2.4
V
Input leakage current
I
IL
10
A
Input capacitance
C
IL
10
pF
INTERFACE TIMING
Clock input frequency
f
CLK
50
MHz
Clock pulse width high
10
ns
Clock pulse width low
10
ns
CS to Clock setup time
0
ns
Clock to CS hold time
10
ns
Data setup time
5
ns
Data hold time
10
ns
POWER REQUIREMENTS
V
DD
2.7
5.5
V
I
DD
(normal operation)
Logic inputs = 0 V
5
A
V
DD
= +4.5V to +5.5V
V
IH
= V
DD
and V
IL
= GND
3
5
A
V
DD
= +2.7V to +3.6V
V
IH
= V
DD
and V
IL
= GND
1
2.5
A
AC CHARACTERISTICS
Output voltage settling time
0.5
s
Reference multiplying BW
V
REF
= 5 V
PP
, Data = 3FFFh
10
MHz
DAC glitch impulse
V
REF
= 0 V, Data = 3FFFh to 2000h
2
nV/s
Feedthrough error
V
REF
= 100 mV
RMS
, 100kHz, Data = 0000h
-70
dB
Digital feedthrough
2
nV/s
Total harmonic distortion
100Hz to 20kHz
-105
dB
Output spot noise voltage
f = 1 kHz, BW = 1 Hz
12
nV/
Hz
(1)
Specified by design and characterization, not production tested.
3
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PIN ASSIGNMENTS
1
8
CLK
CS
DRB PACKAGE
(TOP VIEW)
V
DD
4
CLK
DGK PACKAGE
(TOP VIEW)
SDI
R
FB
V
REF
V
DD
I
OUT
GND
R
FB
SDI
V
REF
CS
I
OUT
GND
3
2
1
5
6
7
8
7
6
5
2
3
4
DAC8801
SLAS403A NOVEMBER 2004 REVISED DECEMBER 2004
TERMINAL FUNCTIONS
PIN
NAME
DESCRIPTION
1
CLK
Clock input, positive edge triggered clocks data into shift register
Serial register input, data loads directly into the shift register MSB first. Extra leading
2
SDI
bits are ignored.
3
R
FB
Internal matching feedback resistor. Connect to external op amp output.
DAC reference input pin. Establishes DAC full-scale voltage. Constant input resistance
4
V
REF
versus code.
5
I
OUT
DAC current output. Connects to inverting terminal of external precision I to V op amp.
6
GND
Analog and digital ground
7
V
DD
Posiitve power supply input. Specified range of operation 2.7 V to 5.5 V.
Chip select, active low digital input. Transfers shift register data to DAC register on
8
CS
rising edge. See Table 1 for operation.
4
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TYPICAL CHARACTERISTICS: V
DD
= +5 V
1.0
0.8
0.6
0.4
0.2
0
-
0.2
-
0.4
-
0.6
-
0.8
-
1.0
0
2048
4096
6144
8192 10240 12288 14336 16384
I
N
L
(
L
S
B
)
Digital Input Code
T
A
= +25
_
C
0
2048
4096
6144
8192 10240 12288 14336 16384
Digital Input Code
T
A
= +25
_
C
1.0
0.8
0.6
0.4
0.2
0
-
0.2
-
0.4
-
0.6
-
0.8
-
1.0
D
N
L
(
L
S
B
)
1.0
0.8
0.6
0.4
0.2
0
-
0.2
-
0.4
-
0.6
-
0.8
-
1.0
0
2048
4096
6144
8192 10240 12288 14336 16384
I
N
L
(
L
S
B
)
Digital Input Code
T
A
=
-
40
_
C
0
2048
4096
6144
8192 10240 12288 14336 16384
Digital Input Code
T
A
=
-
40
_
C
1.0
0.8
0.6
0.4
0.2
0
-
0.2
-
0.4
-
0.6
-
0.8
-
1.0
D
N
L
(
L
S
B
)
1.0
0.8
0.6
0.4
0.2
0
-
0.2
-
0.4
-
0.6
-
0.8
-
1.0
0
2048
4096
6144
8192 10240 12288 14336 16384
I
N
L
(
L
S
B
)
Digital Input Code
T
A
= +85
_
C
0
2048
4096
6144
8192 10240 12288 14336 16384
Digital Input Code
T
A
= +85
_
C
1.0
0.8
0.6
0.4
0.2
0
-
0.2
-
0.4
-
0.6
-
0.8
-
1.0
D
N
L
(
L
S
B
)
DAC8801
SLAS403A NOVEMBER 2004 REVISED DECEMBER 2004
At T
A
= +25
C, +V
DD
= +5 V, unless otherwise noted.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 1.
Figure 2.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 3.
Figure 4.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 5.
Figure 6.
5
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1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
S
u
p
p
l
y
C
u
r
r
e
n
t
,
I
D
D
(
m
A
)
Logic Input Voltage (V)
V
DD
= +5.0V
V
DD
= +2.7V
6
0
-
6
-
12
-
18
-
24
-
30
-
36
-
42
-
48
-
54
-
60
-
66
-
72
-
78
-
84
-
90
-
96
-
102
-
108
-
114
10
100
1k
10k
100k
1M
10M
100M
A
t
t
e
n
u
a
t
i
o
n
(
d
B
)
Bandwidth (Hz)
Time (0.1
s/div)
O
u
t
p
u
t
V
o
l
t
a
g
e
(
5
V
/
d
i
v
)
Trigger Pulse
Voltage Output Settling
Time (0.2
s/div)
O
u
t
p
u
t
V
o
l
t
a
g
e
(
5
0
m
V
/
d
i
v
)
Trigger Pulse
Code: 3FFFh to 2000h
DAC8801
SLAS403A NOVEMBER 2004 REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS: V
DD
= +5 V (continued)
At T
A
= +25
C, +V
DD
= +5 V, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
REFERENCE BANDWIDTH
Figure 7.
Figure 8.
DAC SETTLING TIME
DAC GLITCH
Figure 9.
Figure 10.
6
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TYPICAL CHARACTERISTICS: V
DD
= +2.7V
1.0
0.8
0.6
0.4
0.2
0
-
0.2
-
0.4
-
0.6
-
0.8
-
1.0
0
2048
4096
6144
8192 10240 12288 14336 16384
I
N
L
(
L
S
B
)
Digital Input Code
T
A
= +25
_
C
0
2048
4096
6144
8192 10240 12288 14336 16384
Digital Input Code
T
A
= +25
_
C
1.0
0.8
0.6
0.4
0.2
0
-
0.2
-
0.4
-
0.6
-
0.8
-
1.0
D
N
L
(
L
S
B
)
0
2048
4096
6144
8192 10240 12288 14336 16384
Digital Input Code
T
A
=
-
40
_
C
1.0
0.8
0.6
0.4
0.2
0
-
0.2
-
0.4
-
0.6
-
0.8
-
1.0
D
N
L
(
L
S
B
)
1.0
0.8
0.6
0.4
0.2
0
-
0.2
-
0.4
-
0.6
-
0.8
-
1.0
0
2048
4096
6144
8192 10240 12288 14336 16384
I
N
L
(
L
S
B
)
Digital Input Code
T
A
=
-
40
_
C
1.0
0.8
0.6
0.4
0.2
0
-
0.2
-
0.4
-
0.6
-
0.8
-
1.0
0
2048
4096
6144
8192 10240 12288 14336 16384
I
N
L
(
L
S
B
)
Digital Input Code
T
A
= +85
_
C
0
2048
4096
6144
8192 10240 12288 14336 16384
Digital Input Code
T
A
= +85
_
C
1.0
0.8
0.6
0.4
0.2
0
-
0.2
-
0.4
-
0.6
-
0.8
-
1.0
D
N
L
(
L
S
B
)
DAC8801
SLAS403A NOVEMBER 2004 REVISED DECEMBER 2004
At T
A
= +25
C, +V
DD
= +2.7V, unless otherwise noted.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 11.
Figure 12.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 13.
Figure 14.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 15.
Figure 16.
7
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THEORY OF OPERATION
V
OUT
+
-V
REF
CODE
16384
(1)
V
REF
GND
I
OUT
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
R
FB
R
R
R
_
+
OPA277
V+
V-
15 V
-15 V
V
O
V
DD
R
FB
I
OUT
GND
DAC8801
U2
U1
V
DD
V
REF
DAC8801
SLAS403A NOVEMBER 2004 REVISED DECEMBER 2004
The DAC8801 is a single channel current output, 16-bit digital-to-analog converter (DAC). The architecture,
illustrated in Figure 17, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the
ladder is either switched to GND or the I
OUT
terminal. The I
OUT
terminal of the DAC is held at a virtual GND
potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference
input V
REF
that determines the DAC full-scale current. The R-2R ladder presents a code independent load
impedance to the external reference of 5 k
25%. The external reference voltage can vary in a range of -10 V
to 10 V, thus providing bipolar I
OUT
current operation. By using an external I/V converter and the DAC8801 R
FB
resistor, output voltage ranges of -V
REF
to V
REF
can be generated.
When using an external I/V converter and the DAC8801 R
FB
resistor, the DAC output voltage is given by
Equation 1:
Figure 17. Equivalent R-2R DAC Circuit
Each DAC code determines the 2R leg switch position to either GND or I
OUT
. Because the DAC output
impedance as seen looking into the I
OUT
terminal changes versus code, the external I/V converter noise gain will
also change. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage such
that the amplifier offset is not modulated by the DAC I
OUT
terminal impedance change. External op amps with
large offset voltages can produce INL errors in the transfer function of the DAC8801 due to offset modulation
versus DAC code. For best linearity performance of the DAC8801, an op amp (OPA277) as shown in Figure 18
is recommended. This circuit allows V
REF
to swing from -10V to +10V.
Figure 18. Voltage Output Configuration
8
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t
(CSS)
t
(DS)
t
(DH)
t
(CH)
t
(CL)
t
(CSH)
SDI
CLK
CS
D13
D12
D11
D10
D9
D8
D7
D6
D1
D0
DAC8801
SLAS403A NOVEMBER 2004 REVISED DECEMBER 2004
Figure 19. DAC8801 Timing Diagram
Table 1. Control Logic Truth Table
(1)
CLK
CS
Serial Shift Register
DAC Register
X
H
No effect
Latched
+
L
Shift register data advanced one bit
Latched
X
H
No effect
Latched
X
+
Shift register data transferred to DAC register
New data loaded from serial register
(1)
+ Positive logic transition; X = Don't care
Table 2. Serial Input Register Data Format, Data Loaded MSB First
B13
B0
Bit
(MSB)
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
(LSB)
Data
(1)
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(1)
A full 16-bit data word can be loaded into the serial register, but only the last 14 bits are transferred to the DAC register when CS goes
high.
9
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APPLICATION INFORMATION
Stability Circuit
_
+
V
DD
R
FB
I
OUT
GND
U1
V
DD
V
REF
V
OUT
C1
U2
V
REF
Positive Voltage Output Circuit
GND
OPA277
-2.5 V
GND
0
3
V
OUT
3
+2.5 V
V
OUT
I
OUT
OPA277
C1
R
FB
DAC8801
V
DD
V
DD
+2.5V Reference
V
IN
V
OUT
V
REF
-
+
-
+
DAC8801
SLAS403A NOVEMBER 2004 REVISED DECEMBER 2004
For a current-to-voltage design as shown in Figure 20, the DAC8801 current output (I
OUT
) and the connection
with the inverting node of the op amp should be as short as possible and according to correct PCB layout design.
For each code change there is a step function. If the GBP of the op amp is limited and parasitic capacitance is
excessive at the inverting node then gain peaking is possible. Therefore, for circuit stability, a compensation
capacitor C1 (4 pF to 20 pF typ) can be added to the design as shown in Figure 20.
Figure 20. Gain Peaking Prevention Circuit With Compensation Capacitor
As shown in Figure 21, in order to generate a positive voltage output, a negative reference is input to the
DAC8801. This design is suggested instead of using an inverting amp to invert the output due to tolerance errors
of the resistor. For a negative reference, V
OUT
and GND of the reference are level-shifted to a virtual ground and
a -2.5 V input to the DAC8801 with an op amp.
Figure 21. Positive Voltage Output Circuit
10
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Bipolar Output Circuit
V
OUT
+
D
16, 384
*
1
V
REF
(2)
R
FB
OPA277
U4
-2.5 V
3
V
OUT
3
+2.5 V
V
OUT
10 k
W
10 k
W
+2.5 V
V
REF
V
DD
V
DD
GND
DAC8801
OPA277
U2
I
OUT
C1
C2
5 k
W
-
+
-
+
(+10 V)
(-10 V
3
V
OUT
3
+10 V)
Programmable Current Source Circuit
I
L
+
(
R2
)
R3
)
R1
R3
V
REF
D
(3)
V
DD
V
DD
V
REF
V
REF
DAC8801
U1
R
FB
OPA277
U2
I
OUT
GND
150 k
W
R1
4
15 k
W
R2
4
C1
10 pF
OPA277
U2
15 k
W
R2
50
W
R3
4
50
W
R3
V
OUT
150 k
W
R1
I
L
LOAD
-
+
+
-
DAC8801
SLAS403A NOVEMBER 2004 REVISED DECEMBER 2004
The DAC8801, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output I
OUT
is the inverse of the input reference voltage at V
REF
.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 22,
external op amp U4 is added as a summing amp and has a gain of 2X that widens the output span to 5 V. A
4-quadrant multiplying circuit is implemented by using a 2.5-V offset of the reference voltage to bias U4.
According to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full scale produces
output voltages of V
OUT
= -2.5 V to V
OUT
= +2.5 V.
Figure 22. Bipolar Output Circuit
A DAC8801 can be integrated into the circuit in Figure 23 to implement an improved Howland current pump for
precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two features of
the circuit. A application of this circuit includes a 4-mA to 20-mA current transmitter with up to a 500-
load. With
a matched resistor network, the load current of the circuit is shown in Equation 3:
Figure 23. Programmable Bidirectional Current Source Circuit
11
www.ti.com
Z
O
+
R1 R3(R1
)
R2)
R1(R2
)
R3 )
*
R1 (R2
)
R3)
(4)
Cross-Reference
DAC8801
SLAS403A NOVEMBER 2004 REVISED DECEMBER 2004
The value of R3 in the previous equation can be reduced to increase the output current drive of U3. U3 can drive
20 mA in both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination of the
circuit compensation capacitor C1 in the circuit is not suggested because of the change in the output impedance
Z
O
, according to Equation 4:
As shown in Equation 4, with matched resistors, Z
O
is infinite and the circuit is optimum for use as a current
source. However, if unmatched resistors are used, Z
O
is positive or negative with negative output impedance
being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems
are eliminated. The value of C1 can be determined for critical applications; however, for most applications a
value of several pF is suggested.
The DAC8801 has an industry-standard pinout. Table 3 provides the cross-reference information.
Table 3. Cross Reference
SPECIFIED
INL
DNL
TEMPERATURE
PACKAGE
PACKAGE
CROSS
PRODUCT
(LSB)
(LSB)
RANGE
DESCIPTION
OPTION
REFERENCE
DAC8801IDGK
1
1
-40
C to +85
C
8-Lead MicroSOIC
MSOP-8
ADS5553CRM
DAC8801IDRB
1
1
-40
C to +85
C
8-Lead Small Outline
SON-8
N/A
12
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
DAC8801IDGKR
ACTIVE
MSOP
DGK
8
2000
TBD
CU SNPB
Level-1-220C-UNLIM
DAC8801IDGKT
ACTIVE
MSOP
DGK
8
250
TBD
CU SNPB
Level-1-220C-UNLIM
DAC8801IDRBR
ACTIVE
SON
DRB
8
2500
TBD
CU
Level-1-240C-UNLIM
DAC8801IDRBT
ACTIVE
SON
DRB
8
250
TBD
CU
Level-1-240C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
Addendum-Page 1
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