FEATURES

SINGLE-CHIP SOLUTION TO DIRECTLY
MEASURE EIGHT LOW-LEVEL CURRENTS

HIGH PRECISION, TRUE INTEGRATING
FUNCTION

INTEGRAL LINEARITY:

0.01% of Reading

0.5ppm of FSR

VERY LOW NOISE: 5.2ppm of FSR

LOW POWER: 13.5mW/channel

ADJUSTABLE DATA RATE: Up to 3.125kSPS

PROGRAMMABLE FULL SCALE

DAISY-CHAINABLE SERIAL INTERFACE

Dual

Switched
Integrator

Dual

Switched

Integrator

Modulator

Digital

Filter

Digital

Input/Output

FORMAT

DCLK

DVALID

DOUT

DIN

Control

IN3

IN1

VREF

DVDD

AVDD

DGND

AGND

Dual

Switched

Integrator

Dual

Switched

Integrator

Modulator

Digital

Filter

IN4

IN2

Dual

Switched
Integrator

Dual

Switched

Integrator

Modulator

Digital

Filter

IN7

IN5

Dual

Switched

Integrator

Dual

Switched

Integrator

Modulator

Digital

Filter

IN8

IN6

CLK

CONV

RANGE0

RANGE1

RANGE2

TEST

CLK_4X

HISPD/LOPWR

RESET

APPLICATIONS

CT SCANNER DAS

PHOTODIODE SENSORS

INFRARED PYROMETER

LIQUID/GAS CHROMATOGRAPHY

Protected by US Patent #5841310

DESCRIPTION

The DDC118 is a 20-bit octal channel, current-input
analog-to-digital (A/D) converter. It combines both
current-to-voltage and A/D conversion so that eight
low-level current output devices, such as photodiodes, can
be directly connected to its inputs and digitized.

For each of the eight inputs, the DDC118 provides a
dual-switched integrator front-end. This design allows for
continuous current integration: while one integrator is
being digitized by the onboard A/D converter, the other is
integrating the input current. Adjustable full-scale ranges
from 12pC to 350pC and adjustable integration times from
50

s to 1s allow currents from fAs to

As to be measured

with outstanding precision. Low-level linearity is

0.5ppm

of the full-scale range and noise is 5.2ppm of the full-scale
range.

Two modes of operation are provided. In Low-Power
mode, total power dissipation is only 13.5mW per channel
with a maximum data rate of 2.5kSPS. High-Speed mode
supports data rates up to 3.125kSPS with a corresponding
dissipation of 18mW per channel.

The DDC118 has a serial interface designed for
daisy-chaining in multi-device systems. Simply connect
the output of one device to the input of the next to create
the chain. Common clocking feeds all the devices in the
chain so that the digital overhead in a multi-DDC118
system is minimal.

The DDC118 is a single-supply device using a +5V analog
supply and supporting a +2.7V to +5.25V digital supply.
Operating over the industrial temperature range of -40

to 85

C, the DDC118 is offered in a QFN-48 package.

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

Octal Current Input 20-Bit

Analog-To-Digital Converter

www.ti.com

2002-2005, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

ABSOLUTE MAXIMUM RATINGS

(1)

Analog Input Current

750

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AVDD to DVDD

-0.3V to +6V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AVDD to AGND

-0.3V to +6V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DVDD to DGND

-0.3V to +6V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to DGND

0.2V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VREF Input to AGND

2.0V to AVDD + 0.3V

. . . . . . . . . . . . . . . . . .

Analog Input to AGND

-0.3V to +0.7V

. . . . . . . . . . . . . . . . . . . . . . .

Digital Input Voltage to DGND

-0.3V to DVDD + 0.3V

. . . . . . . . . . .

Digital Output Voltage to DGND

-0.3V to AVDD + 0.3V

. . . . . . . . .

Operating Temperature

-40

C to +85

. . . . . . . . . . . . . . . . . . . . . .

Storage Temperature

-60

C to +150

. . . . . . . . . . . . . . . . . . . . . . .

Junction Temperature (TJ)

+150

. . . . . . . . . . . . . . . . . . . . . . . . . . .

(1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.

This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe

proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

ORDERING INFORMATION

For package and ordering information, see the Package
Option Addendum located at the end of this data sheet.

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

ELECTRICAL CHARACTERISTICS

At TA = +25

C, AVDD = +5V, DVDD = 3V, VREF = +4.096V, Range 5 (250pC), and continuous mode operation, unless otherwise noted.

Low-Power Mode: TINT = 400

s and CLK = 4MHz; High-Speed Mode: TINT = 320

s and CLK = 4.8MHz.

Low-Power Mode

High-Speed Mode

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

ANALOG INPUT RANGE

Range 0

10.2

13.8

(1)

Range 1

47.5

52.5

Range 2

100

105

Range 3

142.5

150

157.5

Range 4

190

200

210

Range 5

237.5

250

262.5

Range 6

285

300

315

Range 7

332.5

350

367.5

Negative Full-Scale Range

-0.4% of Positive Full-Scale Range

Input Current

(2)

750

DYNAMIC CHARACTERISTICS

Data Rate

2.5

3.125

kSPS

Integration Time, T

INT

Continuous Mode

400

1,000,000

320

Integration Time, T

INT

Non-continuous Mode, Range 1 to 7

System Clock Input (CLK)

CLK_4X = 0

4.8

MHz

CLK_4X = 1

19.2

MHz

Data Clock (DCLK)

MHz

ACCURACY

Noise, Low-Level Input

(3)

SENSOR

(4)

= 50pF, Range 5 (250pC)

5.2

6.5

5.5

ppm of

FSR

(5)

, rms

Integral Linearity Error

(6)

0.01% Reading

0.5ppm FSR, typ

Integral Linearity Error

(6)

0.025% Reading

1.0ppm FSR, max

Resolution

FORMAT = 1

Bits

Resolution

FORMAT = 0

Bits

Input Bias Current

0.1

Range Error Match

(7)

All Ranges

0.1

0.5

% of FSR

Range Sensitivity to VREF

REF

= 4.096

0.1V

1:1

Offset Error

Range 5 (250pC)

400

1000

ppm of FSR

Offset Error Match

(7)

100

ppm of FSR

DC Bias Voltage

(9)

Low-Level Input (< 1% FSR)

0.05

Power-Supply Rejection Ratio

at dc

200

ppm of FSR/V

Internal Test Signal

Internal Test Accuracy

PERFORMANCE OVER TEMPERATURE

Offset Drift

0.5

(8)

ppm of

FSR/

Offset Drift Stability

0.2

(8)

ppm of FSR/

minute

DC Bias Voltage Drift

(9)

Input Bias Current Drift

= +25

C to +45

0.01

(8)

pA/

Range Drift

(10)

ppm/

REFERENCE

Voltage

4.000

4.096

4.200

Input Current

(11)

Average Value

150

190

(1)

indicates that specification is the same as Low-Power Mode.

(2) Exceeding maximum input current specification may damage device.
(3) Input is less than 1% of full scale.
(4) CSENSOR is the capacitance seen at the DDC118 inputs from wiring, photodiode, etc.

(5) FSR is Full-Scale Range.
(6) A best-fit line is used in measuring nonlinearity.
(7) Matching between side A and side B of the same input.
(8) Ensured by design, not production tested.
(9) Voltage produced by the DDC118 at its input which is applied to the sensor.
(10)Range drift does not include external reference drift.
(11)Input reference current decreases with increasing TINT (see the Voltage Reference section, page 11).

(12)Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the FORMAT pin (see text).

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

At TA = +25

C, AVDD = +5V, DVDD = 3V, VREF = +4.096V, Range 5 (250pC), and continuous mode operation, unless otherwise noted.

Low-Power Mode: TINT = 400

s and CLK = 4MHz; High-Speed Mode: TINT = 320

s and CLK = 4.8MHz.

High-Speed Mode

Low-Power Mode

PARAMETER

UNITS

MAX

TYP

MIN

MAX

TYP

MIN

TEST CONDITIONS

DIGITAL INPUT/OUTPUT

Logic Levels

0.8DVDD

DVDD + 0.1

- 0.1

0.2DVDD

= -500

DVDD - 0.4

= 500

0.4

Input Current (I

)

0 < V

< DVDD

Data Format

(12)

Straight Binary

POWER-SUPPLY REQUIREMENTS

Analog Power-Supply Voltage (AVDD)

4.75

5.25

Digital Power-Supply Voltage (DVDD)

2.7

5.25

Supply Current

Total Analog Current

Total Digital Current

DVDD = +3V

1.34

Total Power Dissipation

DVDD = +3V

108

150

144

200

Total Power Dissipation per Channel

DVDD = +3V

13.5

18.75

(1)

indicates that specification is the same as Low-Power Mode.

(2) Exceeding maximum input current specification may damage device.
(3) Input is less than 1% of full scale.
(4) CSENSOR is the capacitance seen at the DDC118 inputs from wiring, photodiode, etc.

(12)Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the FORMAT pin (see text).

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

PIN CONFIGURATION

Top View

QFN

DIN

RESET

TEST

DGND

AGND

AVDD

AGND

I
D

DOUT

CLK_4X

FORMAT

HISPD/LOPWR

RANGE0

RANGE1

RANGE2

AGND

VREF

AGND

DDC118

PIN DESCRIPTIONS

PIN

NUMBER

FUNCTION

DESCRIPTION

DOUT

Digital Output

Serial Data Output

DOUT

Digital Output

Serial Data Output: Complementary Signal (optional, see text on page 13)

CLK_4X

Digital Input

Master Clock Divider Control: 0 = divide by 1, 1 = divide by 4

FORMAT

Digital Input

Digital Output Word Format: 0 = 16 Bits, 1 = 20 Bits

HISPD/LOPWR

Digital Input

Mode Control: 0 = Low-Power, 1 = High-Speed

RANGE0

Digital Input

Range Control 0 (least significant bit)

RANGE1

Digital Input

Range Control 1

RANGE2

Digital Input

Range Control 2 (most significant bit)

AGND

9, 11-13, 18, 19, 24-26, 28

Analog

Analog Ground

VREF

Analog Input

External Voltage Reference Input, 4.096V Nominal

AIN8

Analog Input

Analog Input 8

AIN7

Analog Input

Analog Input 7

AIN6

Analog Input

Analog Input 6

AIN5

Analog Input

Analog Input 5

AIN4

Analog Input

Analog Input 4

AIN3

Analog Input

Analog Input 3

AIN2

Analog Input

Analog Input 2

AIN1

Analog Input

Analog Input 1

AVDD

Analog

Analog Power Supply, 5V Nominal

DGND

29, 30, 38, 41, 43, 45, 47, 48

Digital

Digital Ground

TEST

Digital Input

Test Mode Control

RESET

Digital Input

Resets the Digital Circuitry, Active Low

33, 34

No connection. These pins must be left unconnected.

DIN

Digital Input

Serial Data Input: Complementary Signal (optional, see text on page 13)

DIN

Digital Input

Serial Data Input

DVDD

Digital

Digital Power Supply, 3V Nominal

DCLK

Digital Input

Serial Data Clock Input: Complementary Signal (optional, see text on page 13)

DCLK

Digital Input

Serial Data Clock Input

CLK

Digital Input

Master Clock Input

DVALID

Digital Output

Data Valid Output, Active Low

CONV

Digital Input

Conversion Control Input: 0 = Integrate on Side B, 1 = Integrate on Side A

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

TYPICAL CHARACTERISTICS

At TA = +25

C, characterization done with Range 5 (250pC), AVDD = +5V, DVDD = 3V, VREF = +4.096V, and Low-Power Mode: TINT = 400

s and CLK = 4MHz,

unless otherwise noted.

NOISE vs C

SENSOR

100

400

500

300

200

SENSOR

(pF)

i
s

(
p

)

Range 1

Range 2

Range 7

NOISE vs T

INT

1000

0.1

100

INT

(ms)

i
s

(
ppm

r
m

)

SENSOR

= 50pF

SENSOR

= 0pF

Range 5

NOISE vs TEMPERATURE

Temperature (

i
s

(
ppm

r
m

)

SENSOR

= 50pF

Range 1

Range 3

Range 2

Range 7

NOISE vs C

SENSOR

Noise (ppm of FSR, rms)

SENSOR

(pF)

100

150

200

300

500

Range

23.6

30.8

36.3

41.3

46.1

57.0

68.1

89.3

134.0

Range

7.3

10.4

12.3

14.4

16.0

18.8

21.7

27.7

38.9

Range

5.2

6.7

8.2

8.9

10.0

11.9

13.5

16.3

22.4

Range

4.4

5.5

6.5

7.2

8.0

9.2

10.2

12.5

16.6

Range

4.2

4.9

5.6

6.0

6.7

7.8

8.6

10.6

13.5

Range

4.0

4.5

5.1

5.4

5.9

6.8

7.6

9.0

11.7

Range

3.8

4.3

4.8

5.1

5.4

6.1

6.8

8.1

10.4

Range

3.7

4.1

4.4

4.7

5.0

5.7

6.4

7.4

9.5

NOISE vs INPUT LEVEL

100

Input Level (% of Full-Scale)

i
s

(
ppm

r
m

)

SENSOR

= 50pF

SENSOR

= 0pF

Range 5

RANGE DRIFT vs TEMPERATURE

Temperature (

nge

r
i
f
t

(
ppm)

2000

1500

1000

500

1000

1500

2000

All Ranges

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

TYPICAL CHARACTERISTICS (continued)

At TA = +25

C, characterization done with Range 5 (250pC), AVDD = +5V, DVDD = 3V, VREF = +4.096V, and Low-Power Mode: TINT = 400

s and CLK = 4MHz,

unless otherwise noted.

vs TEMPERATURE

Temperature (

)

0.1

0.01

All Ranges

ANALOG SUPPLY CURRENT vs TEMPERATURE

Temperature (

r
r
ent

(
m

)

Low-Power Mode

POWER CONSUMPTION HISTOGRAM

12.00

12.25

12.50

12.75

13.00

13.25

13.50

13.75

14.00

14.25

14.50

14.75

15.00

15.25

15.50

15.75

16.00

Power per Channel (mW)

r
e

(
%

)

Low-Power Mode

Data collected
from multiple lots.

OFFSET DRIFT vs TEMPERATURE

Temperature (

f
s

r
i
f
t

(
p

)

100

DIGITAL SUPPLY CURRENT vs TEMPERATURE

2.5

2.0

1.5

1.0

0.5

Temperature (

r
r
ent

(
m

)

DVDD = 3V

DVDD = 5V

Low-Power Mode

OFFSET DRIFT HISTOGRAM AT ROOM TEMPERATURE

1200

1000

800

600

400

200

1.0

0.6

0.2

0.6

1.0

Offset Drift (ppm of FSR/minute)

Occ

Range 5

Repeated measurement
of offset drift over a
one minute interval.

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

THEORY OF OPERATION

The block diagram of the DDC118 is shown in Figure 1.
The device contains eight identical input channels that
perform the function of current-to-voltage integration
followed by a multiplexed A/D conversion. Each input has
two integrators so that the current-to-voltage integration
can be continuous in time. The output of the sixteen
integrators are switched to four delta-sigma (

)

converters via four four-input multiplexers. With the

DDC118 in the continuous integration mode, the output of
the integrators from one side of the inputs will be digitized
while the other eight integrators are in the integration
mode, as illustrated in the timing diagram in Figure 2. This
integration and A/D conversion process is controlled by
the system clock, CLK. The results from side A and side
B of each signal input are stored in a serial output shift
register. The DVALID output goes low when the shift
register contains valid data.

Dual

Switched

Integrator

Dual

Switched

Integrator

M odulato r

Digital

Filter

D ig ital

In pu t/Output

FORMAT

DCLK

DVALID

DOUT

DIN

C ontro l

IN3

IN1

VREF

DGND

DVDD

AGND

AVDD

Dual

Switched

Integrator

Dual

Switched

Integrator

M odulato r

Digital

Filter

IN4

IN2

Dual

Switched

Integrator

Dual

Switched

Integrator

M odulato r

Digital

Filter

IN7

IN5

Dual

Switched

Integrator

Dual

Switched

Integrator

M odulato r

Digital

Filter

IN8

IN6

CLK

CONV

RANGE0

RANGE1

RANGE2

TEST

CLK_4X

HISPD/LOPWR

RESET

Figure 1. DDC118 Block Diagram

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

The digital interface of the DDC118 provides the digital
results via a synchronous serial interface consisting of
differential data clocks (DCLK and DCLK), a valid data pin
(DVALID), differential serial data output pins (DOUT and
DOUT), and differential serial data input pins (DIN and
DIN). The DDC118 contains only four A/D converters, so
the conversion process is interleaved (see Figure 2). The
integration and conversion process is fundamentally
independent of the data retrieval process. Consequently,
the CLK frequency and DCLK frequencies need not be the
same. DIN and DIN are only used when multiple
converters are cascaded and should be tied to DGND and
DVDD otherwise.

DEVICE OPERATION

Basic Integration Cycle

The topology of the front end of the DDC118 is an analog
integrator as shown in Figure 3. In this diagram, only Input
IN1 is shown. This representation of the input stage
consists of an operational amplifier, a selectable feedback
capacitor network (C

), and several switches that

implement the integration cycle. The timing relationships
of all of the switches shown in Figure 3 are illustrated in
Figure 4. Figure 4 is used to conceptualize the operation
of the integrator input stage of the DDC118 and should not
be used as an exact timing tool for design. See Figure 5 for
the block diagrams of the reset, integrate, wait and convert
states of the integrator section of the DDC118. This
internal switching network is controlled externally with the
convert pin (CONV), range selection pins
(RANGE0-RANGE2), and the system clock (CLK). For the
best noise performance, CONV must be synchronized
with the rising edge of CLK. It is recommended that CONV
toggle within

10ns of the rising edge of CLK.

The noninverting inputs of the integrators are connected to
ground. Consequently, the DDC118 analog ground should
be as clean as possible. The range switches, along with
the internal and external capacitors (C

), are shown in

parallel between the inverting input and output of the
operational amplifier. At the beginning of a conversion, the
switches S

A/D

, S

INTA

, S

INTB

, S

REF1

, S

REF2

, and S

RESET

are set (see Figure 4).

IN1, IN2, IN5, and IN6,

Integrator A

IN1, IN2, IN5, and IN6,

Integrator B

IN3, IN4, IN7, and IN8,

Integrator A

IN3, IN4, IN7, and IN8,

Integrator B

Conversion in Progress

DVALID

IN1B
IN2B
IN5B
IN6B

IN3B
IN4B
IN7B
IN8B

IN1A
IN2A
IN5A
IN6A

Integrate

IN3A
IN4A
IN7A
IN8A

IN1B
IN2B
IN5B
IN6B

IN3B
IN4B
IN7B
IN8B

IN1A
IN2A
IN5A
IN6A

IN3A
IN4A
IN7A
IN8A

Figure 2. Basic Integration and Conversion Timing for the DDC118 (continuous mode)

50pF

25pF

12.5pF

VREF

RANGE2

RANGE1

RANGE0

To Converter

RESET

REF2

A/D1A

INTA

REF1

INTB

IN1

ESD

Protection

Diodes

Input

Current

Integrator A

Integrator B (same as A)

Photodiode

3pF

Figure 3. Basic Integration Configuration for Input 1, shown with a 250pC (C

= 62.5pF) Input Range

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

At the completion of an A/D conversion, the charge on the
integration capacitor (C

) is reset with S

REF1

and

RESET

(see Figure 4 and Figure 5a). In this manner, the selected
capacitor is charged to the reference voltage, VREF. Once
the integration capacitor is charged, S

REF1

and S

RESET

are switched so that VREF is no longer connected to the
amplifier circuit while it waits to begin integrating (see
Figure 5b). With the rising edge of CONV, S

INTA

closes,

which begins the integration of side A. This process puts
the integrator stage into its integrate mode (see Figure 5c).

Charge from the input signal is collected on the integration
capacitor, causing the voltage output of the amplifier to
decrease. The falling edge of CONV stops the integration
by switching the input signal from side A to side B (S

INTA

and S

INTB

). Prior to the falling edge of CONV, the signal on

side B was converted by the A/D converter and reset
during the time that side A was integrating. With the falling
edge of CONV, side B starts integrating the input signal.
Now the output voltage of the side A operational amplifier
is presented to the input of the

A/D converter (see

Figure 5d).

Integration Capacitors

There are eight different capacitors available on-chip for
both sides of every channel in the DDC118. These internal
capacitors are trimmed in production to achieve the
specified performance for range error of the DDC118. The
range control pins (RANGE0-RANGE2) change the
capacitor value for all four integrators. Consequently, all
inputs and both sides of each input will always have the
same full-scale range. Table 1 shows the capacitor value
selected for each range selection.

Table 1. Range Selection of the DDC118

RANGE2

RANGE1

RANGE0

(pF, typ)

INPUT RANGE

(pC, typ)

-0.048 to 12

12.5

0.2 to 50

0.4 to 100

37.5

0.6 to 150

0.8 to 200

62.5

0.1 to 250

1.2 to 300

87.5

1.4 to 350

Voltage Reference

The external voltage reference is used to reset the
integration capacitors before an integration cycle begins.
It is also used by the

converter while the converter is

measuring the voltage stored on the integrators after an
integration cycle ends. During this sampling, the external
reference must supply the charge needed by the

converter. For an integration time of 400

s, this charge

translates to an average VREF current of approximately
150

A. The amount of charge needed by the

converter

is independent of the integration time; therefore,
increasing the integration time lowers the average current.
For example, an integration time of 800

s lowers the

average VREF current to 75

It is critical that VREF be stable during the different modes
of operation (see Figure 5). The

converter measures

the voltage on the integrator with respect to VREF. Since
the integrator capacitors are initially reset to VREF, any
drop in VREF from the time the capacitors are reset to the
time when the converter measures the integrator output
will introduce an offset. It is also important that VREF be
stable over longer periods of time because changes in
VREF correspond directly to changes in the full-scale
range. Finally, VREF should introduce as little additional
noise as possible.

For these reasons, it is strongly recommended that the
external reference source be buffered with an operational
amplifier, as shown in Figure 6. In this circuit, the voltage
reference is generated by a 4.096V reference.

A low-pass

filter to reduce noise connects the reference to an
operational amplifier configured as a buffer. This amplifier
should have low noise, and input/output common-mode
ranges that support VREF. Following the buffer are
capacitors placed close to the DDC118 VREF pin. Even
though the circuit in Figure 6 might appear to be unstable
because of the large output capacitors, it works well for
most operational amplifiers. It is NOT recommended that
series resistance be placed in the output lead to improve
stability since this can cause a drop in VREF, which
producing large offsets.

0.10

+5V

10k

0.10

0.1

OPA350

0.47

+5V

To VREF
Pin 10 of
the DDC118

REF3140

Figure 6. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the DDC118

DDC118

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DDC118 Frequency Response

The frequency response of the DDC118 is set by the front
end integrators and is that of a traditional continuous time
integrator, as shown in Figure 7. By adjusting T

INT

, the

user can change the 3dB bandwidth and the location of the
notches in the response. The frequency response of the

converter that follows the front end integrator is of no

consequence because the converter samples a held
signal from the integrators. That is, the input to the

converter is always a DC signal. Since the output of the
front end integrators are sampled, aliasing can occur.
Whenever the frequency of the input signal exceeds
one-half of the sampling rate, the signal will fold back down
to lower frequencies.

0.1

INT

100
T

INT

Frequency

i
n

(
d

)

Figure 7. Frequency Response of the DDC118

Test Mode

When Test Mode is used, the inputs (IN1, IN2, IN3, IN4,
IN5, IN6, IN7, and IN8) are disconnected from the DDC118
integrators to enable the user to measure a zero input
signal regardless of the current supplied to the inputs. In
addition, packets of charge can be transferred to the
integrators in 11pC intervals to measure non-zero values.
The test mode works with both the continuous and
non-continuous modes. The timing diagram for the test
mode is shown in Figure 8 with the timing specifications
given in Table 2.

To enter Test Mode, hold TEST high while CONV
transitions. If TEST is held high during the entire
integration period, the integrators measure a zero value.
This mode can be used to help debug a design or perform
diagnostic tests. To apply packets of charge during Test
Mode, simply strobe TEST low then high before the next
CONV transition. Each rising edge of TEST causes
approximately 11pC of charge to be transferred to the
integrators. This charge transfer is independent of the
integration time. Data retrieval during Test Mode is
identical to normal operation. To exit Test Mode, take
TEST low and allow several cycles after exiting before
using the data.

Action

CONV

TEST

Integrate B

Integrate A

Test Mode Disabled

0pC into B

11pC into A

22pC into B

33pC into A

Test Mode Disabled

Test Mode Enabled: Inputs Disconnected

Integrate B

Integrate A

Figure 8. Timing Diagram of the Test Mode of the DDC118

Table 2. Timing for the DDC118 in the Test Mode

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

Setup Time for Test Mode Enable

100

Setup Time for Test Mode Disable

100

Hold Time for Test Mode Enable

100

From Rising Edge of TEST to the Edge of CONV while Test Mode

Enabled

Falling Edge to Rising Edge of TEST

Rising Edge to Falling Edge of TEST

DDC118

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DIGITAL INTERFACE

The digital interface of the DDC118 provides the digital
results via a synchronous serial interface consisting of
differential data clocks (DCLK and DCLK), a valid data pin
(DVALID), differential serial data output pins (DOUT and
DOUT), and differential serial data input pins (DIN and
DIN). The DDC118 contains only four A/D converters, so
the conversion process is interleaved (see Figure 2,
page 9). The integration and conversion processes are
independent of the data retrieval process. Consequently,
the CLK frequency and DCLK frequencies need not be the
same. DIN and DIN are used when multiple converters are
cascaded. Cascading or daisy-chaining greatly simplifies
the interconnection and routing of the digital outputs in
cases where a large number of converters are needed.
Refer to the Cascading Multiple Converters section of this
data sheet for more detail.

Complementary Signals (DCLK, DIN, and DOUT)

The DDC118 provides optional complementary inputs
(DCLK, DIN) to help reduce digital coupling to the analog
inputs. If using these inputs, connect a complementary
signal to each. If these inputs are not connected on the
DDC118, they should be tied to DGND. DOUT is a
complementary output designed to drive DIN. If not using
DOUT, leave it floating.

System and Data Clocks (CLK and CONV)

The system clock is supplied to CLK and the data clock is
supplied to DCLK. Make sure the clock signals are
clean--avoid overshoot or ringing. For best performance,
generate both clocks from the same clock source. DCLK
should be disabled by taking it low after the data has been
shifted out or while CONV is transitioning.

When using multiple DDC118s, pay close attention to the
DCLK distribution on the printed circuit board (PCB). In
particular, make sure to minimize skew in the DCLK signal
as this can lead to timing violations in the serial interface
specifications. See the Cascading Multiple Converters
section for more details.

System Clock Divider (CLK_4X)

The CLK_4X input enables an internal divider on the
system clock as shown in Table 3. When CLK_4X = 1, the
system clock is divided by four. This allows a 4X faster
system clock, which in turn provides a finer quantization of
the integration time as the CONV signal needs to be
synchronized with the system clock for the best
performance.

Table 3. CLK_4X Pin Operation

CLK_4X

PIN

CLK DIVIDER

VALUE

TYPICAL CLK

FREQUENCY

INTERNAL CLOCK

FREQUENCY

4MHz

16MHz

4MHz

High-Speed and Low-Power Modes
(HISPD/LOPWR)

The HISPD/LOPWR input controls the power dissipation
and in turn, the maximum allowable CLK frequency and
data rate, as shown in Table 4. With HISPD/LOPWR = 0,
the Low-Power Mode is selected with a typical 13.5mW/
channel and a maximum data rate of 2.5kSPS. Setting
HISPD/LOPWR = 1 selects the High-Speed Mode, which
supports a maximum data rate of 3.125kSPS with a corre-
sponding typical power of 18.0mW/channel.

Table 4. HISPD/LOPWR Pin Operation

HISPD/

LOPWR

MODE

TYPICAL

POWER/

CHANNEL

MAXIMUM

CLK FREQUENCY

(CLK_4X = 0)

MAXIMUM

DATA
RATE

Low-Power

13.5mW/ch

4.0MHz

2.5kSPS

High-Speed

18.0mW/ch

4.8MHz

3.125kSPS

Data Valid (DVALID)

The DVALID signal indicates that data is ready. Data
retrieval may begin after DVALID goes low. This signal is
generated using an internal clock divided down from the
system clock CLK. The phase relationship between this
internal clock and CLK is set when power is first applied
and is random. Since the user must synchronize CONV
with CLK, the DVALID signal will have a random phase
relationship with CONV. This uncertainty is

1/f

CLK

Polling DVALID eliminates any concern about this
relationship. If data read back is timed from CONV, wait the
maximum value of t

or t

to insure data is valid.

Reset (RESET)

The DDC118 is reset asynchronously by taking the
RESET input low, as shown in Figure 9. Make sure the
reset pulse is at least 50

s wide. After resetting the

DDC118, wait at least four conversions before using the
data. It is very important to make sure the RESET is glitch
free to avoid unintended resets. The RESET pin is used
during power-up; see the Power-Up Sequence section for
more details.

RESET

> 50

Figure 9. Reset Timing

Convert (CONV)

CONV controls the integration time (T

INT

). For optimum

analog performance, make sure CONV is synchronized to
CLK.

This recommendation implies that while SPEED is low,
T

INT

needs to be adjusted in steps of 250ns if CLK_4X is

low and CLK = 4MHz. If CLK_4X is high and CLK =
16MHz, this allows T

INT

to be adjusted in steps of 62.5ns.

DDC118

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Conversion Rate

The conversion rate of the DDC118 is set by a combination
of the integration time (determined by the user) and the
speed of the A/D conversion process. The A/D conversion
time is primarily a function of the system clock (CLK)
speed. One A/D conversion cycle encompasses the
conversion of two signals (one side of each dual integrator
feeding the modulator) and the reset time for each of the
integrators involved in the two conversions. In most
situations, the A/D conversion time is shorter than the
integration time. If this condition exists, the DDC118 will
operate in the continuous mode. When the DDC118 is in
the continuous mode, the sensor output is continuously
integrated by one of the two sides of each input.

In the event that the A/D conversion takes longer than the
integration time, the DDC118 will switch into a
non-continuous mode. In non-continuous mode, the A/D
converter is not able to keep pace with the speed of the
integration process. Consequently, the integration
process is periodically halted until the digitizing process
catches up. These two basic modes of operation for the
DDC118--continuous and non-continuous modes--are
described below.

Continuous and Non-Continuous Operational
Modes

Figure 10 shows the state diagram of the DDC118. In all,
there are eight states. Table 5 provides a brief explanation
of each state.

Table 5. State Descriptions

STATE

MODE

DESCRIPTION

Ncont

Complete m/r/az of side A, then side B (if previous
state is state 4). Initial power-up state when CONV
is initially held HIGH.

Ncont

Prepare side A for integration.

Cont

Integrate on side A.

Cont

Integrate on side B; m/r/az on side A.

Cont

Integrate on side A; m/r/az on side B.

Cont

Integrate on side B.

Ncont

Prepare side B for integration.

Ncont

Complete m/r/az of side B, then side A (if previous
state is state 5). Initial power-up state when CONV
is initially held LOW.

Four signals are used to control progression around the
state diagram: CONV, mbsy, and their complements. The
state machine uses the level as opposed to the edges of
CONV to control the progression. mbsy is an internally-
generated signal not available to the user. It is active
whenever a measurement/reset/auto-zero (m/r/az) cycle
is in progress.

Int A/Meas B

Cont

CONV

mbsy

CONV

mbsy

CONV

mbsy

CONV

mbsy

CONV

mbsy

CONV

mbsy

CONV

Int B/Meas A

Cont

Ncont

Int A
Cont

Ncont

Int B
Cont

CONV

CONV|mbsy

Figure 10. Integrate/Measure State Diagram

During the cont mode, mbsy is not active when CONV
toggles. The non-integrating side is always ready to begin
integrating when the other side finishes its integration.
Consequently, monitoring the current status of CONV is all
that is needed to know the current state. Cont mode
operation corresponds to states 3-6. Two of the states, 3
and 6, only perform an integration (no m/r/az cycle).

mbsy becomes important when operating in the ncont
mode, states 1, 2, 7, and 8. Whenever CONV is toggled
while mbsy is active, the DDC118 will enter or remain in
either ncont state 1 (or 8). After mbsy goes inactive, state
2 (or 7) is entered. This state prepares the appropriate side
for integration. In the ncont states, the inputs to the
DDC118 are grounded.

One interesting observation from the state diagram is that
the integrations always alternate between sides A and B.
This relationship holds for any CONV pattern and is
independent of the mode. States 2 and 7 insure this
relationship during the ncont mode.

When power is first applied to the DDC118, the beginning
state is either 1 or 8, depending on the initial level of CONV.
For CONV held high at power-up, the beginning state is 1.
Conversely, for CONV held low at power-up, the beginning
state is 8. In general, there is a symmetry in the state
diagram between states 1-8, 2-7, 3-6, and 4-5. Inverting
CONV results in the states progressing through their
symmetrical match.

DDC118

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TIMING EXAMPLES

Cont Mode

A few timing diagrams help illustrate the operation of the
state machine. These diagrams are shown in Figure 11
through Figure 19. Table 6 gives generalized timing
specifications in units of CLK periods for CLK_4X = 0. If
CLK_4X = 1, these values increase by a factor of four
because of the internal clock divider. Values (in

s) for

Table 6 can be easily found for a given CLK. For example,
if CLK = 4MHz, then a CLK period = 0.25

s. t

in Table 6

would then be 367.50

0.125

Table 6. Timing Specifications Generalized in

CLK Periods

SYMBOL

DESCRIPTION

VALUE
(CLK periods with CLK_4X = 0)

Cont mode m/r/az cycle

1470

0.5

Cont mode data ready

1380

0.5

1st ncont mode data ready

1379

2nd ncont mode data ready

1450

t10

Ncont mode m/r/az cycle

2901

Figure 11 shows a few integration cycles beginning with
initial power-up for a cont mode example. The top signal
is CONV and is supplied by the user. The next line
indicates the current state in the state diagram. The
following two traces show when integrations and

measurement cycles are underway. The internal signal
mbsy is shown next. Finally, DVALID is given. DVALID
goes active low when data is ready to be retrieved from the
DDC118. It stays low until DCLK is taken high and then
back low by the user. The text below the DVALID pulse
indicates the side of the data available to be read, and
arrows help match the data to the corresponding
integration. The signals illustrated in Figure 11 through
Figure 19 are drawn at approximately the same scale.

In Figure 11, the first state is ncont state 8. The DDC118
always powers up in the ncont mode. In this case, the first
state is 8 because CONV is initially low. After the first two
states, cont mode operation is reached and the states
begin toggling between 4 and 5. From now on, the input is
being continuously integrated, either on side A or side B.
The time needed for the m/r/az cycle, or t

, is the same time

that determines the boundary between the cont and ncont
modes described earlier in the Overview section. DVALID
goes low after CONV toggles in time t

, indicating that data

is ready to be retrieved. As shown in Figure 11, there are
two values for t

and t

. The reason for this is discussed in

the Special Considerations section.

See Figure 12 for the timing diagram of the internal
operations occurring during continuous mode operation.
Table 7 gives the timing specifications in the continuous
mode.

SYMBOL

DESCRIPTION

VALUE (CLK = 4MHz, CLK_4X = 0)

VALUE (CLK = 4.8MHz, CLK_4X = 0)

Cont Mode m/r/az Cycle

367.50

0.125

306.25

0.104

Cont Mode Data Ready

345.00

0.125

287.5

0.104

Figure 11. Continuous Mode Timing

Integrate A

Integrate B

Integrate A

m/r/az

m/r/az A

m/r/az B

CONV

State

Integration

Status

m/r/az
Status

mbsy

DVALID

t = 0

Power-Up

Side B

Data

Side A

Data

Side B

Data

DDC118

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INT

End Integration Side A
Start Integration Side B

Side A

Data Ready

Side B

Data Ready

Side A

End Integration Side B
Start Integration Side A

End Integration Side A
Start Integration Side B

CONV

DVALID

A/D Conversion

Inputs 1, 2, 5, and 6 (Internal)

A/D Conversion

Inputs 3, 4, 7, and 8 (Internal)

Side B

Figure 12. Timing Diagram of the Internal Operation in Continuous Mode of the DDC118

Table 7. Timing for the Internal Operation in Continuous Mode

CLK = 4MHz, CLK_4X = 0

CLK = 4.8MHz, CLK_4X = 0

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

TINT

Integration Period (continuous mode)

400

1,000,000

320

1,000,000

t12

A/D Conversion Time (internally controlled)

169.5

141.25

t13

A/D Conversion Reset Time (internally controlled)

3.333

t14

Integrator and A/D Conversion Reset Time
(internally controlled)

19.167

DDC118

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Ncont Mode

Non-continuous mode of operation is intended for Ranges
1 to 7. It is not recommended to use Range 0 when
operating in non-continuous mode. Figure 13 illustrates
operation in the ncont mode. The integrations come in
pairs (that is, sides A/B or sides B/A) followed by a time
during which no integrations occur. During that time, the
previous integrations are being measured, reset and
auto-zeroed. Before the DDC118 can advance to states 3
or 6, both sides A and B must be finished with the m/r/az
cycle which takes time t

. When the m/r/az cycles are

completed, time t

is needed to prepare the next side for

integration. This time is required for the ncont mode
because the m/r/az cycle of the ncont mode is slightly
different from that of the cont mode. After the first

integration ends, DVALID goes low in time t

. This time is

the same as in the cont mode. The second data will be
ready in time t

after the first data is ready. One result of the

naming convention used in this data sheet is that when the
DDC118 is operating in the ncont mode, it passes through
both ncont mode states and cont mode states. For
example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4,
1, 2, 3, 4 ... where 3 and 4 are cont mode states. Ncont
mode, by definition, means that for some portion of the
time, neither side A nor B is integrating. States that perform
an integration are labeled cont mode states, while those
that do not are called ncont mode states. Since
integrations are performed in the ncont mode, just not
continuously, some cont mode states must be used in a
ncont mode state pattern.

SYMBOL

DESCRIPTION

VALUE (CLK = 4MHz, CLK_4X = 0)

VALUE (CLK = 4.8MHz, CLK_4X = 0)

1st ncont Mode Data Ready

344.75

0.25

287.292

0.208

2nd ncont Mode Data Ready

362.5

302.083

t10

ncont Mode m/r/az Cycle

725.25

0.25

604.375

0.208

t11

Prepare Side for Integration

Figure 13. Non-Continuous Mode Timing

Int B

Int A

Int B

Int A

m/r/az B

m/r/az A

m/r/az B

CONV

State

mbsy

m/r/az

Status

Integration

Status

DVALID

Side A

Data

Side B

Data

Side A

Data

Side B

Data

DDC118

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INT

Release

State

End Integration Side A

Start Integration Side B

End Integration Side B

Wait State

Side A

Data Ready

Side B

Data Ready

Start Integration Side A

CONV

A/D Conversion

Inputs 1, 2, 5, and 6

A/D Conversion

Inputs 3, 4, 7, and 8

DVALID

Figure 14. Conversion Detail for the Internal Operation of Non-Continuous Mode with Side A Integrated

First

Table 8. Internal Timing for the DDC118 in Non-Continuous Mode

SYMBOL

DESCRIPTION

CLK = 4MHz, CLK_4X = 0

CLK = 4.8MHz, CLK_4X = 0

UNITS

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

INT

Integration Time (non-continuous mode)

400

1,000,000

320

1,000,000

A/D Conversion Time (internally controlled)

169.5

141.25

A/D Conversion Reset Time (internally controlled)

3.333

Integrator and A/D Conversion Reset Time
(internally controlled)

19.5

16.25

Total A/D Conversion and Reset Time (internally controlled)

725.25

0.25

604.375

0.208

Release Time

INT

Release

State

End Integration Side A

Start Integration Side B

End Integration Side B

Wait State

Side A

Data Ready

Side B

Data Ready

Start Integration Side A

CONV

A/D Conversion

Inputs 1, 2, 5, and 6

A/D Conversion

Inputs 3, 4, 7, and 8

DVALID

Figure 15. Internal Operation Timing Diagram of Non-Continuous Mode with Side B Integrated First

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Looking at the state diagram, one can see that the CONV
pattern needed to generate a given state progression is not
unique. Upon entering states 1 or 8, the DDC118 remains
in those states until mbsy goes low, independent of CONV.
As long as the m/r/az cycle is underway, the state machine
ignores CONV (see Figure 10, page 14). The top two
signals in Figure 16 are different CONV patterns that
produce the same state. This feature allows flexibility in
generating ncont mode CONV patterns. For example, the
DDC118 Evaluation Fixture operates in the ncont mode by
generating a square wave with pulse width < t

. Figure 17

illustrates operation in the ncont mode using a 50% duty

cycle CONV signal with T

INT

= 512 CLK periods. Care

must be exercised when using a square wave to generate
CONV. There are certain integration times that must be
avoided since they produce very short intervals for state 2
(or state 7 if CONV is inverted). As seen in the state
diagram, the state progresses from 2 to 3 as soon as
CONV is high. The state machine does not insure that the
duration of state 2 is long enough to properly prepare the
next side for integration (t

). This must be done by the

user with proper timing of CONV. For example, if CONV is
a square wave with T

INT

= 970 CLK periods, state 2 will

only be 9 CLK periods long; therefore, t

will not be met.

CONV1

CONV2

State

mbsy

Figure 16. Equivalent CONV Signals in Non-Continuous Mode

CONV

DVALID

State

Integration

Status

mbsy

Int B

Int A

Int B

Side A

Data

Side B

Data

Side A

Data

Int A

Figure 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal

DDC118

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Changing Between Modes

Changing from the cont to ncont mode occurs whenever
T

INT

< t

. Figure 18 shows an example of this transition.

In this figure, the cont mode is entered when the integration
on side A is completed before the m/r/az cycle on side B
is complete. The DDC118 completes the measurement on
sides B and A during states 8 and 7 with the input signal
shorted to ground. Ncont integration begins with state 6.

Changing from the ncont to cont mode occurs when T

INT

is increased so that T

INT

is always

, as shown in

Figure 19 (see also Figure 14 and Table 8, page 18). With
a longer T

INT

, the m/r/az cycle has enough time to finish

before the next integration begins and continuous
integration of the input signal is possible. For the special
case of the very first integration when changing to the cont
mode, T

INT

can be < t

. This is allowed because there is

no simultaneous

m/r/az cycle on the side B during state

3--there is no need to wait for it to finish before ending the
integration on side A.

CONV

Continuous

Non-Continuous

State

Integration

Status

m/r/az

Status

mbsy

m/r/az B

m/r/az A

m/r/az B

m/r/az A

m/r/az B

Integrate A

Integrate B

Int A

Int B

Figure 18. Changing from Continuous Mode to Non-Continuous Mode

CONV

Non-Continuous

Continuous

State

mbsy

m/r/az
Status

Integration

Status

m/r/az A

m/r/az B

m/r/az A

Int B

Int A

Integrate A

Integrate B

Figure 19. Changing from Non-Continuous Mode to Continuous Mode

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DATA FORMAT (FORMAT)

The serial output data is provided in an offset binary code
as shown in Table 9. The digital input pin FORMAT selects
how many bits are used in the output word. When
FORMAT is high (1), 20 bits are used. When FORMAT is
low (0), the lower 4 bits are truncated so that only 16 bits
are used. Note that the LSB size is 16 times bigger when
FORMAT = 0. An offset is included in the output to allow
slightly negative inputs, from board leakages for example,
from clipping the reading. This offset is approximately
0.4% of the positive full-scale.

Table 9. Ideal Output Code

(1)

vs Input Signal

INPUT

SIGNAL

IDEAL OUTPUT CODE

FORMAT = HIGH

(1)

IDEAL OUTPUT CODE

FORMAT = LOW

(0)

100% FS

1111 1111 1111 1111 1111

1111 1111 1111 1111

0.001531% FS

0000 0001 0000 0001 0000

0000 0001 0000 0001

0.001436% FS

0000 0001 0000 0000 1111

0000 0001 0000 0000

0.000191% FS

0000 0001 0000 0000 0010

0000 0001 0000 0000

0.000096% FS

0000 0001 0000 0000 0001

0000 0001 0000 0000

0% FS

0000 0001 0000 0000 0000

0000 0001 0000 0000

-0.3955% FS

0000 0000 0000 0000 0000

0000 0000 0000 0000

(1) Excludes the effects of noise, INL, offset, and gain errors.

DATA RETRIEVAL

In both the continuous and non-continuous modes of
operation, the data from the last conversion is available for
retrieval on the falling edge of DVALID (see Figure 20 and
Table 10). Data is shifted out on the falling edge of the data
clock, DCLK. Make sure not to retrieve data while CONV
changes as this can introduce noise. Stop activity on
DCLK at least 10

s before or after a CONV transition.

Setting the FORMAT pin = 0 (16-bit output word) reduces
the time needed to retrieve data by 20%, since there are
fewer bits to shift out. This time reduction can be useful in
multichannel systems requiring only 16 bits of resolution.

CLK

DVALID

DCLK

DOUT

Input 8

MSB

Input 1

LSB

Input 8

LSB

Input 7

MSB

Input 5

LSB

Input 4

MSB

Input 2

LSB

Input 1

MSB

Input 8

MSB

Figure 20. Digital Interface Timing Diagram for Data Retrieval From a Single DDC118

Table 10. Timing for the DDC118 Data Retrieval

SYMBOL

DESCRIPTION

CLK = 4MHz, CLK_4X = 0

CLK = 4.8MHz, CLK_4X = 0

UNITS

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

t18

Propagation Delay from Falling Edge of CLK to DVALID LOW

t19

Propagation Delay from Falling Edge of DCLK to DVALID HIGH

t20

Hold Time that DOUT is Valid Before the Falling Edge of DVALID

1.75

1.458

t21

Hold Time that DOUT is Valid After Falling Edge of DCLK

t21A(1)

Propagation Delay from Falling Edge of DCLK to Valid DOUT

(1)

With a maximum load of one DDC118 (4pF typical) with an additional load of (5pF

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

SPECIAL CONSIDERATIONS

Cascading Multiple Converters

Multiple DDC118 units can be connected in serial
configuration, as illustrated in Figure 21.

DOUT can be used with DIN to daisy-chain several

DDC118 devices together to minimize wiring. In this mode
of operation, the serial data output is shifted through
multiple DDC118s, as illustrated in Figure 21.

See Figure 22 for the timing diagram when the DIN input
is used to daisy-chain several devices. Table 11 gives the
timing specification for data retrieval using DIN.

IN8

Sensor

DIN

DOUT

DDC118

DIN

DOUT

DIN

DOUT

VAL

I
D

Data Retrieval

Outputs

IN7

IN6

IN5

IN4

IN3

IN2

IN1

IN8

IN7

IN6

IN5

IN4

IN3

IN2

IN1

IN8

IN7

IN6

IN5

IN4

IN3

IN2

IN1

VAL

I
D

VAL

I
D

DDC118

Data Clock

Figure 21. Daisy-Chained DDC118s

CLK

DVALID

DCLK

DIN

DOUT

Input A

MSB

Input A

LSB

Input B

MSB

Input L

LSB

Input M

MSB

Input W

LSB

Input X

MSB

Input X

LSB

Input A

MSB

Figure 22. Timing Diagram When Using the DIN Function of the DDC118

Table 11. Timing for the DDC118 Data Retrieval Using DIN

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

t22

Set-Up Time From DIN to Falling Edge of DCLK

t23

Hold Time For DIN After Falling Edge of DCLK

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

RETRIEVAL BEFORE CONV TOGGLES
(CONTINUOUS MODE)

Date retrieval before CONV toggles is the most
straightforward method. Data retrieval begins soon after
DVALID goes low and finishes before CONV toggles, as
shown in Figure 23. For best performance, data retrieval
must stop t

before CONV toggles. This method is most

appropriate for longer integration times. The maximum
time available for readback is T

INT

. For DCLK =

10MHz and CLK = 4MHz, the maximum number of
DDC118s that can be daisy-chained together (FORMAT =
high) is calculated by Equation 1:

INT

355.125

160

DCLK

NOTE: 128

DCLK

is used for FORMAT = low.

where

DCLK

is the period of the data clock. For example,

if T

INT

= 1000

s and DCLK = 10MHz, the maximum

number of DDC118s (FORMAT = high) is shown in
Equation 2:

1000

355.125

(160)(100ns)

40.30

40DDC118s

(or 50 for FORMAT = low).

SYMBOL

DESCRIPTION

CLK = 4MHz, CLK_4X = 0

CLK = 4.8MHz, CLK_4X = 0

UNITS

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

t27

Cont Mode Data Ready

345.00

0.125

287.5

0.104

t28

Data Retrieval Shutdown Before Edge of CONV

Figure 23. Readback Before CONV Toggles

(1)

(2)

...

Side B

Data

Side A

Data

INT

CONV

DVALID

DCLK

DOUT

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

RETRIEVAL AFTER CONV TOGGLES
(CONTINUOUS MODE)

For shorter integration times, more time is available if data
retrieval begins after CONV toggles and ends before the
new data is ready. Data retrieval must wait t

after CONV

toggles before beginning. See Figure 24 for an example of
this. The maximum time available for retrieval is
t

- t

(344.875

s 10

s 1.75

s for

CLK = 4MHz), regardless of T

INT

. The maximum number

of DDC118s that can be daisy-chained together (FORMAT
= high) is calculated by Equation 3:

333.125

160

DCLK

NOTE: 128

DCLK

is used for FORMAT = low.

For DCLK = 10MHz, the maximum number of DDC118s is
20 (or 26 for FORMAT = low).

SYMBOL

DESCRIPTION

CLK = 4MHz, CLK_4X = 0

CLK = 4.8MHz, CLK_4X = 0

UNITS

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

t26

Hold Time that DOUT is Valid Before Falling Edge of DVALID

1.75

1.458

t27

Cont Mode Data Ready

345.00

0.125

287.5

0.104

t29

Data Retrieval Start-Up After Edge of CONV

Figure 24. Readback After CONV Toggles

(3)

INT

...

Side A

Data

Side B

Data

Side A

Data

CONV

DVALID

DCLK

DOUT

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

RETRIEVAL BEFORE AND AFTER CONV
TOGGLES (CONTINUOUS MODE)

For the absolute maximum time for data retrieval, data can
be retrieved before and after CONV toggles. Nearly all of
T

INT

is available for data retrieval. Figure 25 illustrates

how this is done by combining the two previous methods.
Retrieval during CONV toggling to prevent digital noise, as
discussed previously, and finished before the next data is
ready. The maximum number of DDC118s that can be
daisy-chained together (FORMAT = high) is:

INT

1.75

160

DCLK

NOTE: 128

DCLK

is used for FORMAT = low.

For T

INT

= 400

s and DCLK = 10MHz, the maximum

number of DDC118s is 23 (or 29 for FORMAT = low).

RETRIEVAL: NONCONTINUOUS MODE

Retrieving in noncontinuous mode is slightly different,
compared to the continuous mode. As illustrated in
Figure 26, DVALID goes low in time t

after the first

integration completes. If T

INT

is shorter than this time, all

of t

is available to retrieve data before the other side data

is ready. For T

INT

> t

, the first integration data is ready

before the second integration completes. Data retrieval
must be delayed until the second integration completes,
leaving less time available for retrieval. The time available
is t

INT

). The second integration's data must be

retrieved before the next round of integration begins. This
time is highly dependent on the pattern used to generate
CONV. As with the continuous mode, data retrieval must
halt before and after CONV toggles (t

, t

) and be

completed before new data is ready (t

SYMBOL

DESCRIPTION

CLK = 4MHZ, CLK_4X = 0

CLK = 4.8MHZ, CLK_4X = 0

UNITS

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

t26

Hold Time that DOUT is Valid Before Falling Edge of DVALID

1.75

1.458

t28

Data Retrieval Shutdown Before Edge of CONV

t29

Data Retrieval Start-Up After Edge of CONV

Figure 25. Readback Before and After CONV Toggles

SYMBOL

DESCRIPTION

CLK = 4MHz, CLK_4X = 0

CLK = 4.8MHz, CLK_4X = 0

UNITS

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

t30

1st ncont Mode Data Ready

344.75

0.25

287.292

0.208

t31

2nd ncont Mode Data Ready

362.500

302.083

Figure 26. Readback in Non-Continuous Mode

...

DCLK

DVALID

CONV

DOUT

Side B

Data

Side A

Data

INT

...

IN T

3 0

IN T

3 1

S ide A

Data

S ide B

Data

CONV

DVALID

DCLK

D OUT

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

POWER-UP SEQUENCING

Prior to power-up, all digital and analog inputs must be low.
After the power supplies have settled, release RESET
after time t

. (See Figure 28 and Table 12.) Wait for time

to begin applying the digital signals CONV and CLK.

The first CONV pulse will complete the release state and
begin integration.

LAYOUT

POWER SUPPLIES AND GROUNDING

Both AVDD and DVDD should be as quiet as possible. It
is particularly important to eliminate noise from AVDD that
is non-synchronous with the DDC118 operation. Figure 27
illustrates two acceptable ways to supply power to the
DDC118. The first case shows two separate +5V supplies
for AVDD and DVDD. In this case, each +5V supply of the
DDC118 should be bypassed with 10

F solid tantalum

capacitors and 0.1

F ceramic capacitors. The second

case shows the DVDD power supply derived from the
AVDD supply with a < 10

isolation resistor. In both cases,

the 0.1

F capacitors should be placed as close to the

DDC118 package as possible. It is recommended that
both the analog and digital grounds (AGND and DGND) be
connected to a single ground plane on the printed circuit
board (PCB).

THERMAL PAD

It is strongly recommended that the thermal pad on the
DDC118 be connected to ground on the PCB. No PCB
traces should be routed underneath the thermal pad.

DDC118

0.1

< 10

+5V

One +5V Supply

AVDD

DVDD

AVDD

DVDD

AGND

DGND

AGND

DGND

DDC118

0.1

Separate Supplies

Figure 27. Power-Supply Connection Options

Release State

Start Integration

AVDD
DVDD

CONV

RESET

CLK

Integrate Side B

...

Figure 28. Timing Diagram at Power-Up of the DDC118

Table 12. Timing for the DDC118 Power-Up Sequence

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

t32

Power Supplies Settled to RESET Release

t33

RESET Release to CONV, CLK Begin

t34

First CONV Pulse Width

DDC118

SBAS325A - JUNE 2004 - REVISED JUNE 2005

www.ti.com

Shielding Analog Signal Paths

As with any precision circuit, careful PCB layout ensures
the best performance. It is essential to make short, direct
interconnections and avoid stray wiring
capacitance--particularly at the analog input pins. Digital
signals should be kept as far from the analog input signals
as possible on the PCB.

Input shielding practices should be taken into
consideration when designing the circuit layout for the
DDC118. The inputs to the DDC118 are high impedance
and extremely sensitive to extraneous noise. Leakage

currents between the PCB traces can exceed the input
bias current of the DDC118 if shielding is not implemented.
Figure 29 illustrates an acceptable approach to this
problem. A PC ground plane is placed around the inputs
of the DDC118. This shield helps minimize coupled noise
into the input pins.

This approach reduces leakage effects by surrounding
these sensitive pins with a low impedance analog ground.
Leakage currents from other portions of the circuit will flow
harmlessly to the low impedance analog ground rather
than into the analog input stage of the DDC118.

IN4

IN3

Digital I/O and Digital Power

Analog

Ground

Analog

Ground

Analog

Ground

IN2

IN1

DDC118

IN7

IN8

IN5

IN6

Analog Power

Figure 29. Recommended Shield for DDC118 Layout Design

PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

DDC118IRTCR

ACTIVE

QFN

RTC

2500 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

DDC118IRTCT

ACTIVE

QFN

RTC

250

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco

Plan

The

planned

eco-friendly

classification:

Pb-Free

(RoHS)

Green

(RoHS

Sb/Br)

please

check

http://www.ti.com/productcontent

for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

1-Jul-2005

Addendum-Page 1

IMPORTANT NOTICE

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