Burr Brown Products
from Texas Instruments

FEATURES

APPLICATIONS

DESCRIPTION

Modulator

Digital

Filter

Serial

Interface

DVALID

DCLK

DOUT

DIN

Configuration

and

Control

IN2

IN1

VREF

DGND

DVDD

AGND

AVDD

Modulator

Digital

Filter

IN4

IN3

Modulator

Digital

Filter

IN30

IN29

Modulator

Digital

Filter

IN32

IN31

CLK

CONV

DIN_CFG

CLK_CFG

RESET

Dual
Switched
Integrator

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

32-Channel, Current-Input

Analog-to-Digital Converter

The DDC232 has a serial interface designed for
daisy-chaining

multi-device

systems.

Simply

SINGLE-CHIP SOLUTION TO DIRECTLY

connect the output of one device to the input of the

MEASURE 32 LOW-LEVEL CURRENTS

next to create the chain. Common clocking feeds all

HIGH-PRECISION, TRUE INTEGRATING

the devices in the chain so that the digital overhead

FUNCTION

in a multi-DDC232 system is minimal.

INTEGRAL LINEARITY:

The DDC232 uses a +5V analog supply and a +2.7V

±0.025% of Reading ±1.0ppm of FSR

+3.6V

digital

supply.

Operating

over

the

temperature range of 0°C to +70°C, the DDC232 is

VERY LOW NOISE: 5.3ppm of FSR

offered in a BGA-64 package.

LOW POWER: 7mW/channel

ADJUSTABLE FULL-SCALE RANGE

ADJUSTABLE DATA RATE: Up to 6kSPS

 Integration Times Down to 166.5

DAISY-CHAINABLE SERIAL INTERFACE

CT SCANNER DAS

PHOTODIODE SENSORS

X-RAY DETECTION SYSTEMS
Protected by US Patent #5841310

The DDC232 is a 20-bit, 32-channel, current-input
analog-to-digital (A/D) converter. It combines both
current-to-voltage and A/D conversion so that 32
separate low-level current output devices, such as
photodiodes, can be directly connected to its inputs
and digitized.

For each of the 32 inputs, the DDC232 provides a
dual-switched integrator front-end. This configuration
allows for continuous current integration: while one
integrator is being digitized by the onboard A/D
converter, the other is integrating the input current.
Adjustable integration times range from 166

s to 1s,

allowing currents from fAs to

As to be continuously

measured with outstanding precision.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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PACKAGE/ORDERING INFORMATION

ABSOLUTE MAXIMUM RATINGS

(1)

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

For the most current package and ordering information, see the Package Option Addendum at the end of this
document.

AVDD to AGND

0.3V to +6V

DVDD to DGND

0.3V to +3.6V

AGND to DGND

±0.2V

VREF Input to AGND

2.0V to AVDD + 0.3V

Analog Input to AGND

0.3V to +0.7V

Digital Input Voltage to DGND

0.3V to DVDD + 0.3V

Digital Output Voltage to DGND

0.3V to AVDD + 0.3V

Operating Temperature

0°C to +70°C

Storage Temperature

60°C to +150°C

Junction Temperature (T

)

+150°C

(1)

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.

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ELECTRICAL CHARACTERISTICS

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

At T

= +25°C, AVDD = +5V, DVDD = +3.0V, VREF = +4.096V, t

INT

= 333µs in Low-Power mode (CLK = 5MHz),

Range = 7, and continuous mode operation, unless otherwise noted.

DDC232C

DDC232CK

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

ANALOG INPUT RANGE

Range 1

Range 2

100

110

100

110

Range 3

135

150

165

135

150

165

Range 4

180

200

220

180

200

220

Range 5

225

250

275

225

250

275

Range 6

270

300

330

270

300

330

Range 7

315

350

385

315

350

385

Negative Full-Scale Range

0.4% of Positive Full-Scale Range

DYNAMIC CHARACTERISTICS

Data Rate

Low-Power Mode

3.125

kSPS

High-Speed Mode

Not Supported

6.2

kSPS

Integration Time, t

INT

Continuous Mode, Low-Power Mode

320

1,000,000

320

1,000,000

Continuous Mode, High-Speed Mode

Not Supported

162

1,000,000

Non-Continuous Mode

System Clock (CLK)

Low-Power Mode, Clk_4x = 0

MHz

High-Speed Mode, Clk_4x = 0

MHz

Low-Power Mode, Clk_4x = 1

MHz

High-Speed Mode, Clk_4x = 1

MHz

Data Clock (DCLK)

MHz

Configuration Clock (CLK_CFG)

MHz

ACCURACY

Noise, Low-Level Input

(1)

SENSOR

(2)

= 50pF

5.3

ppm of FSR

(3)

, rms

Integral Linearity Error

(4)

±0.025% Reading ± 1.0ppm FSR, typ

±0.05% Reading ± 1.5ppm FSR, max

Resolution

Format = 1

Bits

Format = 0

Bits

Input Bias Current

±0.1

±10

±0.1

±10

Range Error Match

(5)

0.1

0.5

0.1

0.5

% of FSR

Range Sensitivity to VREF

VREF = 4.096 ±0.1V

1:1

Offset Error

±200

±1000

±200

±1000

ppm of FSR

Offset Error Match

(5)

±100

ppm of FSR

DC Bias Voltage

(6)

Low-Level Input (< 1% FSR)

±0.1

±2

±0.1

±2

Power-Supply Rejection Ratio

at DC

100

±800

100

±800

ppm of FSR/V

(1)

Input is less than 1% of full-scale.

(2)

SENSOR

is the capacitance seen at the DDC232 inputs from wiring, photodiode, etc.

(3)

FSR is Full-Scale Range.

(4)

A best-fit line is used in measuring nonlinearity.

(5)

Matching between side A and side B of the same input.

(6)

Voltage produced by the DDC232 at its input that is applied to the sensor.

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DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

ELECTRICAL CHARACTERISTICS (continued)

At T

= +25°C, AVDD = +5V, DVDD = +3.0V, VREF = +4.096V, t

INT

= 333µs in Low-Power mode (CLK = 5MHz),

Range = 7, and continuous mode operation, unless otherwise noted.

DDC232C

DDC232CK

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

PERFORMANCE OVER TEMPERATURE

Offset Drift

±0.5

(7)

±0.5

(7)

ppm of FSR/°C

Offset Drift Stability

±0.2

(7)

±0.2

(7)

ppm of FSR/minute

DC Bias Voltage Drift

(8)

±3

V/°C

Input Bias Current Drift

= +25°C to +45°C

0.01

(7)

0.01

(7)

pA/°C

Range Drift

(9)

ppm/°C

Range Drift Match

(10)

±5

ppm/°C

REFERENCE

Voltage

4.000

4.096

4.200

4.000

4.096

4.200

Input Current

(11)

Average Value with t

INT

= 333

325

Average Value with t

INT

= 166.5

650

DIGITAL INPUT/OUTPUT

Logic Levels

(0.8)DVDD

DVDD + 0.1

(0.8)DVDD

DVDD + 0.1

0.1

(0.2)DVDD

0.1

(0.2)DVDD

= 500

DVDD 0.4

= 500

0.4

Input Current (I

)

0 < V

< DVDD

±10

Data Format

(12)

Straight Binary

POWER-SUPPLY REQUIREMENTS

Analog Power-Supply Voltage (AVDD)

4.75

5.0

5.25

4.75

5.0

5.25

Digital Power-Supply Voltage (DVDD)

2.7

3.0

3.6

2.7

3.0

3.6

Supply Current

Analog Current

Low-Power Mode

High-Speed Mode

Not Supported

Digital Current

Low-Power Mode

3.7

High-Speed Mode

Not Supported

7.0

Total Power Dissipation

Low-Power Mode

224

288

224

288

High-Speed Mode

Not Supported

320

Per Channel Power Dissipation

Low-Power Mode

mW/Channel

High-Speed Mode

Not Supported

mW/Channel

(7)

Ensured by design, not production tested.

(8)

Voltage produced by the DDC232 at its input that is applied to the sensor.

(9)

Range drift does not include external reference drift.

(10) Matching between side A and side B of the same input.
(11) Input reference current decreases with increasing t

INT

(see the

Voltage Reference

section, page 10).

(12) Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the Format bit.

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PIN CONFIGURATION

Top View

Columns

IN7

IN9

IN11

IN6

IN5

IN8

IN10

IN12

IN19

IN29

IN31

IN18

IN17

IN20

IN30

IN32

IN3

IN13

IN15

IN2

IN1

IN4

IN14

IN16

AGND

QGND

AGND

AVDD

AGND

VREF

AVDD

AGND

AVDD

DGND

VREF

CLK

DOUT

DIN

DGND

DCLK

DGND

CONV

IN23

IN25

IN27

IN22

IN21

IN24

IN26

IN28

CLK_CFG

DGND

DVDD

DIN_CFG

DVALID

DGND

RESET

DGND

BGA

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

PIN DESCRIPTIONS

PIN

LOCATION

FUNCTION

DESCRIPTION

IN132

Rows 14

Analog Input

Analog Inputs for Channels 1 to 32

QGND

Analog

Quiet Analog Ground

AGND

G5, F5, E5, D5, C5, B5, A5, D6, H6

Analog

Analog Ground

DGND

A7, C6, D7, E7, C8, G8

Digital

Digital Ground

AVDD

E6, F6, G6

Analog

Analog Power Supply, +5V Nominal

VREF

A6, B6

Analog Input

External Voltage Reference Input, +4.096V Nominal

DVALID

Digital Output

Data Valid Output, Active Low

DIN_CFG

Digital Input

Configuration Register Data Input

CLK_CFG

Digital Input

Configuration Register Clock Input

RESET

Digital Input

Digital Reset, Active Low

DVDD

Digital

Digital Power Supply, 3.3V Nominal

CONV

Digital Input

Conversion Control Input; 0 = Integrate on Side B, 1 = Integrate on Side A

DIN

Digital Input

Serial Data Input

DOUT

Digital Output

Serial Data Output

No Connect

Do not connect; must be left floating.

CLK

Digital Input

Master Clock Input

DCLK

Digital Input

Serial Data Clock Input

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THEORY OF OPERATION

Modulator

Digital

Filter

Serial

Interface

DVALID

DCLK

DOUT

DIN

Configuration

and

Control

IN2

IN1

VREF

DGND

DVDD

AGND

AVDD

Modulator

Digital

Filter

IN4

IN3

Modulator

Digital

Filter

IN30

IN29

Modulator

Digital

Filter

IN32

IN31

CLK

CONV

DIN_CFG

CLK_CFG

RESET

Dual
Switched
Integrator

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

digitized while the other 32 integrators are in the

The block diagram of the DDC232 is shown in

integration

mode.

This

integration

and

A/D

Figure 2

. The device contains 32 identical input

conversion process is controlled by the system clock,

channels

that

perform

the

function

CLK. The results from side A and side B of each

current-to-voltage

integration

followed

signal input are stored in a serial output shift register.

multiplexed A/D conversion. Each input has two

The DVALID output goes low when the shift register

integrators so that the current-to-voltage integration

contains valid data.

can be continuous in time. The output of the 64
integrators are switched to 16 delta-sigma (

)

converters via multiplexers. With the DDC232 in the
continuous integration mode, the output of the
integrators from one side of the inputs will be

Figure 2. DDC232 Block Diagram

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DEVICE OPERATION

Basic Integration Cycle

50pF

25pF

12.5pF

VREF

Range[2] Bit

Range[1] Bit

Range[0] Bit

To Converter

RESET

REF2

ADC1A

INTA

REF1

INTB

IN1

ESD

Protection

Diodes

Input

Current

Integrator A

Integrator B (same as A)

Photodiode

3pF

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

At the completion of an A/D conversion, the charge
on the integration capacitor (C

) is reset with S

REF1

The topology of the front end of the DDC232 is an

and S

RESET

(see

Figure 4

and

Figure 5

a). This is

analog integrator as shown in

Figure 3

. In this

done during reset. In this manner, the selected

diagram, only input IN1 is shown. The input stage

capacitor is charged to the reference voltage, VREF.

consists of an operational amplifier, a selectable

Once the integration capacitor is charged, S

REF1

and

feedback

capacitor

network

and

several

RESET

are switched so that VREF is no longer

switches that implement the integration cycle. The

connected to the amplifier circuit while it waits to

timing relationships of all of the switches shown in

begin integrating (see

Figure 5

b). With the rising

Figure 3

are illustrated in

Figure 4

edge of CONV, S

INTA

closes, which begins the

conceptualizes the operation of the integrator input

integration of side A. This process puts the integrator

stage of the DDC232 and should not be used as an

stage into its integrate mode (see

Figure 5

c).

exact timing tool for design.

Charge from the input signal is collected on the

See

Figure 5

for the block diagrams of the reset,

integration capacitor, causing the voltage output of

integrate, wait, and convert states of the integrator

the amplifier to decrease. The falling edge of CONV

section of the DDC232. This internal switching

stops the integration by switching the input signal

network is controlled externally with the convert pin

from side A to side B (S

INTA

and S

INTB

). Prior to the

(CONV), and the system clock (CLK). For the best

falling edge of CONV, the signal on side B was

noise performance, CONV must be synchronized

converted by the A/D converter and reset during the

with the rising edge of CLK. It is recommended that

time that side A was integrating. With the falling edge

CONV toggle within ±10ns of the rising edge of CLK.

of CONV, side B starts integrating the input signal. At
this

point,

the

output

voltage

the

side

The noninverting inputs of the integrators are

operational amplifier is presented to the input of the

connected to ground. Consequently, the DDC232

A/D converter (see

Figure 5

d).

analog ground should be as clean as possible. The
internal and external capacitors (C

), are shown in

parallel between the inverting input and output of the
operational

amplifier.

the

beginning

conversion, the switches S

A/D

, S

INTA

, S

INTB

, S

REF1

REF2

, and S

RESET

are set (see

Figure 4

Figure 3. Basic Integration Configuration for Input 1

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A/D1A

VREF

Integrator A

Voltage Output

Configuration of

Integrator A

Wait

Convert

Wait

Convert

Integrate

REF1

REF2

INTA

INTB

RESET

CONV

CLK

i
t

To Converter

RESET

REF2

A/D

VREF

REF1

INT

a) Reset Configuration

To Converter

RESET

REF2

A/D

VREF

REF1

INT

c) Integrate Configuration

To Converter

RESET

REF2

A/D

VREF

REF1

INT

d) Convert Configuration

To Converter

RESET

REF2

A/D

VREF

REF1

INT

b) Wait Configuration

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

Figure 4. Integration Timing Diagram (see

Figure 3

)

Figure 5. Diagrams for the Four Configurations of the Front-End Integrators

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Integration Capacitors

Voltage Reference

0.10

+5V

10k

0.10

OPA350

0.47

+5V

To VREF Pin on
the DDC232

REF3140

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

average VREF current of approximately 325µA. The
amount of charge needed by the

converter is

independent

the

integration

time;

therefore,

There

are

seven

different

capacitors

available

increasing the integration time lowers the average

on-chip for both sides of every channel in the

current. For example, an integration time of 800µs

DDC232. These internal capacitors are trimmed in

lowers the average VREF current to TBDµA.

production to achieve the specified performance for
range error of the DDC232. The range control bits

It is critical that VREF be stable during the different

(Range[2:0]) change the capacitor value for all

modes of operation (see

Figure 5

). The

converter

integrators. Consequently, all inputs and both sides

measures the voltage on the integrator with respect

of each input will always have the same full-scale

to VREF. Since the integrator capacitors are initially

range.

Table 1

shows the capacitor value selected

reset to VREF, any drop in VREF from the time the

for each range selection.

capacitors are reset to the time when the converter
measures the integrator output will introduce an

Table 1. Range Selection

offset. It is also important that VREF be stable over
longer periods of time because changes in VREF

INPUT

RANGE

correspond directly to changes in the full-scale

Range[2]

Range[1]

Range[0]

(pF, typ)

(pC, typ)

range. Finally, VREF should introduce as little

0.04 to 12.5

additional noise as possible.

12.5

0.2 to 50

For these reasons, it is strongly recommended that

0.4 to 100

the external reference source be buffered with an
operational amplifier, as shown in

Figure 6

. In this

37.5

0.6 to 150

circuit, the voltage reference is generated by a

0.8 to 200

+4.096V reference. A low-pass filter to reduce noise

62.5

0.1 to 250

connects the reference to an operational amplifier

1.2 to 300

configured as a buffer. This amplifier should have

87.5

1.4 to 350

low noise and input/output common-mode ranges
that support VREF. Even though the circuit in

Figure 6

might appear to be unstable due to the

large output capacitors, it works well for most

The external voltage reference is used to reset the

operational amplifiers. It is not recommended that

integration capacitors before an integration cycle

series resistance be placed in the output lead to

begins. It is also used by the

converter while the

improve stability since this can cause a drop in

converter is measuring the voltage stored on the

VREF, which produces large offsets.

integrators after an integration cycle ends. During
this sampling, the external reference must supply the
charge

needed

the

converter.

For

integration time of 333µs, this charge translates to an

Figure 6. Recommended External Voltage Reference Circuit for Best Low-Noise Operation

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Frequency Response

CONFIGURATION REGISTER

0.1

INT

100

INT

Frequency

i
n

(
d

)

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

The frequency response of the DDC232 is set by the

Some aspects of device operation are controlled by

front end integrators and is that of a traditional

the onboard configuration register. The DIN_CFG,

continuous time integrator, as shown in

Figure 7

. By

CLK_CFG, and RESET pins are used to write to this

adjusting

INT

the

user

can

change

the

3dB

bandwidth and the location of the notches in the

CONV low and strobe RESET; see

Figure 8

. Then

response.

The

frequency

response

the

begin shifting in the configuration data on DIN_CFG.

converter that follows the front end integrator is of no

Data is written to the configuration register most

consequence because the converter samples a held

significant bit first. The data is internally latched on

signal from the integrators. That is, the input to the

the falling edge of CLK_CFG. Partial writes to the

converter is always a DC signal. Since the output

configuration register are not allowed--make sure to

of the front end integrators are sampled, aliasing can

send all 12 bits when updating the register.

occur. Whenever the frequency of the input signal

Optional readback of the configuration register is

exceeds one-half of the sampling rate, the signal will

available immediately after the write sequence.

fold back down to lower frequencies.

During

readback,

the

12-bit

configuration

data

followed by a 4-bit revision id and the test pattern are
shifted out on the DOUT pin on the rising edge of
DCLK.

NOTE: with Format = 1, the test pattern is 304 bits
with only the last 72 bits non-zero. This sequence of
outputs is repeated twice for each DDC232 and
daisy-chaining

supported

configuration

readback.

Table

shows

the

test

pattern

configuration during readback.

Table 3

shows the

timing for the configuration register read and write
operations. Strobe CONV to begin normal operation.

Table 2. Test Pattern During Readback

TEST PATTERN

TOTAL

Format BIT

(Hex)

READBACK BITS

30F066012480F6h

512

30F066012480F69055h

640

Figure 7. TFrequency Response

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Configuration

Data

Write Configuration Register Data

Configuration Register Operations

Test Pattern

Read Configuration Register

and Test Pattern

RESET

CLK_CFG

DIN_CFG

DCLK

DOUT

CONV

Normal Operation

WTWR

WTRST

MSB

LSB

MSB

LSB

STCF

RST

HDCF

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

Figure 8. Configuration Register Write and Read Operations

Table 3. Timing for the Configuration Register Read/Write

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

WTRST

Wait Required from Reset High to First Rising Edge of CLK_CFG

µs

WTWR

Wait Required from Last CLK-CFG of Write Operation to

µs

First CLK_CFG of Read Operation

STCF

Set-Up Time from DIN_CFG to Falling Edge of CLK_CFG

HDCF

Hold Time for DIN_CFG After Falling Edge of CLK_CFG

RST

Pulse Width for RESET Active

µs

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DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

Configuration Register

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Range[2]

Range[1]

Range[0]

Format

Pwr/Spd

Clk_4x

Test

Bits 119

Range[2:0] Analog Input Range

000: 12.5pC

100: 200pC

001: 50pC

101: 250pC

010: 100pC

110: 300pC

011: 150pC

111: 350pC (default)

Bit 8

Format
0 = 16-Bit Output
1 = 20-Bit Output (default)

Format selects how many bits are used in the data output word.

Bit 7

Pwr/Spd
0 = Low-Power Mode (default)
1 = High-Speed Mode (DDC232CK Only)

TYPICAL

MAXIMUM CLK

MAXIMUM

Pwr/Spd BIT

MODE

POWER/CHANNEL (mW)

FREQUENCY (MHz)

(1)

DATA RATE (kHz)

Low-Power

3.125

(2)

High-Speed

(2)

(1)

Assumes Clk_4x = 0.

(2)

Only the DDC232CK supports High-Speed mode.

Bit 6

Clk_4x (System Clock Divider)
0 = Internal Clock Divider = 1 (default)
1 = Internal Clock Divider = 4

The Clk_4x input enables an internal divider on the system clock. When Clk_4x = 1, the system
clock is divided by 4. This allows a 4X faster system clock, which in turn provides a finer
quantization of the integration time because the CONV signal needs to be synchronized with the
system clock for the best performance.

Clk_4x BIT

CLK DIVIDER VALUE

CLK FREQUENCY

INTERNAL CLOCK FREQUENCY

5MHz

20MHz

5MHz

Bits 51

00000

Bit 0

Test Mode
0 = Test Mode Off (default)
1 = Test Mode On

When Test Mode is used, the inputs (IN1 through IN32) are disconnected from the DDC232
integrators to enable the user to measure a zero input signal regardless of the current supplied
to the inputs. The test mode works with both the continuous and non-continuous modes.

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DIGITAL INTERFACE

Reset (RESET)

RESET

> 1

System and Data Clocks (CLK and CONV)

Conversion Rate

Data Valid (DVALID)

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

with CONV. This uncertainty is ± 1/f

CLK

. Polling

DVALID

eliminates

any

concern

about

this

The digital interface of the DDC232 outputs the

relationship. If data read back is timed from CONV,

digital results via a synchronous serial interface

wait the maximum value of t

or t

to insure data is

consisting of a data clock (DCLK), a valid data pin

valid.

(DVALID), a serial data output pin (DOUT), and a
serial data input pin (DIN). The integration and
conversion process is fundamentally independent of
the data retrieval process. Consequently, the CLK

The DDC232 is reset asynchronously by taking the

and DCLK frequencies need not be the same,

RESET input low, as shown in

Figure 9

. Make sure

though

for

best

performance,

highly

the release pulse is at least 1µs wide. After resetting

recommended that they be derived from the same

the DDC232, wait at least four conversions before

clocking source to keep their phase relationship

using the data. It is very important that RESET is

constant. DIN is only used when multiple converters

glitch-free to avoid unintentional resets.

are

cascaded

and

should

tied

DGND

otherwise. Depending on t

INT

, CLK, and DCLK, it is

possible to daisy-chain multiple converters. This
greatly simplifies the interconnection and routing of
the digital outputs in those applications where a large
number of converters are needed. Configuration of
the DDC232 is set by a dedicated register addressed
using the DIN_CFG and CLK_CFG pins.

Figure 9. Reset Timing

The system clock is supplied to CLK and the data

The conversion rate of the DDC232 is set by a

clock is supplied to DCLK. Make sure the clock

combination of the integration time (determined by

signals are clean--avoid overshoot or ringing. For

the user) and the speed of the A/D conversion

best performance, generate both clocks from the

process. The A/D conversion time is primarily a

same clock source. DCLK should be disabled by

function of the system clock (CLK) speed. One A/D

taking it low after the data has been shifted out or

conversion cycle encompasses the conversion of two

while CONV is transitioning.

signals (one side of each dual integrator feeding the

When using multiple DDC232s, pay close attention

modulator) and the reset time for each of the

to the DCLK distribution on the printed circuit board

integrators involved in the two conversions. In most

(PCB). In particular, make sure to minimize skew in

situations, the A/D conversion time is shorter than

the DCLK signal because this can lead to timing

the integration time. If this condition exists, the

violations in the serial interface specifications. See

DDC232 will operate in the continuous mode. When

the Cascading Multiple Converters section for more

the DDC232 is in the continuous mode, the sensor

details.

output is continuously integrated by one of the two
sides of each input.

In the event that the A/D conversion takes longer

The DVALID signal indicates that data is ready. Data

than the integration time, the DDC232 will switch into

retrieval may begin after DVALID goes low. This

a non-continuous mode. In non-continuous mode,

signal is generated using an internal clock divided

the A/D converter is not able to keep pace with the

down from the system clock, CLK. The phase

speed of the integration process. Consequently, the

relationship between this internal clock and CLK is

integration process is periodically halted until the

set when power is first applied and is random. Since

digitizing process catches up. These two basic

the user must synchronize CONV with CLK, the

modes of operation for the DDC232--continuous and

DVALID signal will have a random phase relationship

non-continuous modes--are described below.

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Continuous

and

Non-Continuous

Operational

Int A/Meas B

Cont

CONV

mbsy

CONV

mbsy

State Diagram Notation:

CONV

mbsy = CONV high AND mbsy active.

CONV|mbsy = CONV high OR mbsy active.

CONV

mbsy

CONV

mbsy

CONV

mbsy

CONV

mbsy

CONV

Int B/Meas A

Cont

Ncont

Int A
Cont

Ncont

Int B

Cont

CONV

CONV|mbsy

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

Four signals are used to control progression around

Modes

the

state

diagram:

CONV,

mbsy,

and

their

complements. The state machine uses the level as

Figure 10

shows the state diagram of the DDC232.

opposed to the edges of CONV to control the

In all, there are eight states.

Table 4

provides a brief

progression. mbsy is an internally-generated signal

explanation of each state.

not available to the user. It is active whenever a
measurement/reset/auto-zero (m/r/az) cycle is in
progress.

During the continuous (cont) mode, mbsy is not
active when CONV toggles. The non-integrating side
is always ready to begin integrating when the other
side finishes its integration. Consequently, monitoring
the current status of CONV is all that is needed to
know

the

current

state.

Cont

mode

operation

corresponds to states 36. Two of the states, 3 and
6, only perform an integration (no m/r/az cycle).

mbsy becomes important when operating in the
non-continuous (ncont) mode (states 1, 2, 7, and 8).
Whenever CONV is toggled while mbsy is active, the
DDC232 will enter or remain in either ncont state 1
(or 8). After mbsy goes inactive, state 2 (or 7) is
entered. This state prepares the appropriate side for
integration. In the ncont states, the inputs to the
DDC232 are grounded.

One interesting observation from the state diagram is
that the integrations always alternate between sides
A and B. This relationship holds for any CONV
pattern and is independent of the mode. States 2
and 7 insure this relationship during the ncont mode.

When power is first applied to the DDC232, the
beginning state is either 1 or 8, depending on the
initial level of CONV. For CONV held high at
power-up, the beginning state is 1. Conversely, for
CONV held low at power-up, the beginning state is 8.
In general, there is a symmetry in the state diagram
between states 18, 27, 36, and 45. Inverting
CONV results in the states progressing through their

Figure 10. Integrate/Measure State Diagram

symmetrical match.

Table 4. State Descriptions

STATE

MODE

DESCRIPTION

Ncont

Complete m/r/az of side A, then side B (if previous state is state 4). Initial power-up state
when CONV is initially held High.

Ncont

Prepare side A for integration.

Cont

Integrate on side A.

Cont

Integrate on side B; m/r/az on side A.

Cont

Integrate on side A; m/r/az on side B.

Cont

Integrate on side B.

Ncont

Prepare side B for integration.

Ncont

Complete m/r/az of side B, then side A (if previous state is state 5). Initial power-up state
when CONV is initially held Low.

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TIMING EXAMPLES

Continuous Mode

Integrate A

Integrate B

Integrate A

m/r/az B

m/r/az A

m/r/az B

CONV

State

Integration

Status

m/r/az
Status

mbsy

DVALID

MRA Z

CMDR

t = 0

Power-Up

Side B

Data

Side A

Data

Side B

Data

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

diagram. The following two traces show when
integrations and measurement cycles are underway.
The internal signal mbsy is shown next. Finally,

A few timing diagrams help illustrate the operation of

DVALID is given. As described in the data sheet,

the

integrate/measure

state

machine.

These

DVALID goes active low when data is ready to be

diagrams are shown in

Figure 11

through

Figure 16

retrieved from the DDC232. It stays low until DCLK is

Table 5

gives generalized timing specifications in

taken high and then back low by the user. The text

units of CLK periods for Clk_4x = 0. If Clk_4x = 1,

below the DVALID pulse indicates the side of the

these values increase by a factor of 4 because of the

data available to be read and arrows help match the

internal clock divider. Values (in µs) for

Table 5

can

data to the corresponding integration.

be easily found for a given CLK.

Figure 11

shows a few integration cycles beginning

with initial power-up for a cont mode example. The
top signal is CONV and is supplied by the user. The
next line indicates the current state in the state

Figure 11. Continuous Mode Timing

Table 5. Timing Specifications Generalized in CLK Periods

VALUE

(CLK periods with Clk_4x = 0)

SYMBOL

DESCRIPTION

Low-Power Mode

High-Speed Mode

MRAZ

Cont mode m/r/az cycle

1552 ± 2

1612 ± 2

CMDR

Cont mode data ready

1382 ± 2

NCDR1

1st ncont mode data ready

TBD

NCDR2

2nd ncont mode data ready

TBD

NCMRAZ

Ncont mode m/r/az cycle

TBD

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ADCONV

IRST

ADRST

INT

End Integration Side A

Start Integration Side B

Side A

Data Ready

Side B

Data Ready

Side B

Side A

Side B

Side A

End Integration Side B

Start Integration Side A

End Integration Side A

Start Integration Side B

CONV

DVALID

A/D Conversion

Odd Channels (Internal)

A/D Conversion

Even Channels (Internal)

IRST

ADRST

ADCONV

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

Figure 11

, the first state is ncont state 8. The

that determines the boundary between the cont and

DDC232 always powers up in the ncont mode. In this

ncont modes described earlier in the Overview

case, the first state is 8 because CONV is initially

section. DVALID goes low after CONV toggles in

low. After the first two states, cont mode operation is

time t

CMDR

, indicating that data is ready to be

reached and the states begin toggling between 4 and

retrieved.

5. From now on, the input is being continuously

See

Figure 12

for the timing diagram of the internal

integrated, either on side A or side B. The time

operations

occurring

during

continuous

mode

needed for the m/r/az cycle, t

MRAZ

, is the same time

operation.

Table 6

gives the timing specifications of

the internal operations occurring during continuous
mode operation.

Figure 12. Timing Diagram for DDC232 Internal Operation in Continuous Mode

Table 6. Timing for the Internal Operation in Continuous Mode

Low-Power Mode

High-Speed Mode

(CLK = 5MHz)

(CLK = 9.6MHz)

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

INT

Integration Period (continuous mode)

320

1,000,000

162

1,000,000

µs

ADCONV

A/D Conversion Time (internally controlled)

135.6

TBD

µs

ADRST

A/D Conversion Reset Time (internally controlled)

3.2

TBD

µs

IRST

Integrator Reset Time (internally controlled)

TBD

µs

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Non-Continuous Mode

ADCONV

NCDR1

NCDR2

INT

ADRST

NCIRST

NCRL

Release

State

End Integration Side A
Start Integration Side B

End Integration Side B

Wait State

Side B Data Ready

Side A Data Ready

Start Integration Side A

CONV

A/D Conversion

Odd Channels

A/D Conversion

Even Channels

DVALID

ADCONV

INT

ADRST

NCIRST

NCRL

CONV

A/D Conversion

Odd Channels

A/D Conversion

Even Channels

DVALID

Release

State

End Integration Side B
Start Integration Side A

End Integration Side A

Wait State

Side B

Data Ready

Side A

Data Ready

Start Integration Side B

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

Figure 13

and

Figure 14

illustrate operation in non-continuous mode.

Figure 13. Conversion Detail for the Internal Operation of Non-Continuous Mode

with Side A Integrated First

Table 7. DDC232 Internal Timing in Non-Continuous Mode

CLK = 5MHz, Clk_4x = 0

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

INT

Integration Time (non-continuous mode)

TBD

1,000,000

µs

ADCONV

A/D Conversion Time (internally controlled)

135.6

µs

ADRST

A/D Conversion Reset Time (internally controlled)

3.2

µs

NCIRST

Non-Continuous Mode Integrator Reset Time (internally controlled)

TBD

µs

NCRL

Release Time

TBD

µs

NCDR1

1st Non-Continuous Mode Data Ready

TBD

NCDR2

2nd Non-Continuous Mode Data Ready

TBD

Figure 14. Internal Operation Timing Diagram Non-Continuous Mode with Side B Integrated First

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Changing Between Modes

CONV

Continuous

Non-Continuous

State

Integration

Status

m/r/az

Status

mbsy

m/r/az B

m/r/az A

m/r/az B

m/r/az A

m/r/az B

Integrate A

Integrate B

Int A

Int B

CONV

Non-Continuous

Continuous

State

mbsy

m/r/az
Status

Integration

Status

m/r/az A

m/r/az B

m/r/az A

Int B

Int A

Integrate A

Integrate B

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

is increased so that t

INT

is always

MRAZ

as shown

Figure 16

(see

Figure 13

and

Table 7

, page 18).

Changing from cont to ncont mode occurs whenever

With a longer t

INT

, the m/r/az cycle has enough time

INT

< t

MRAZ

Figure 15

shows an example of this

to finish before the next integration begins and

transition. In this figure, cont mode is entered when

continuous integration of the input signal is possible.

the integration on side A is completed before the

For the special case of the very first integration when

m/r/az cycle on side B is complete. The DDC232

changing to the cont mode, t

INT

can be < t

MRAZ

. This

completes the measurement on sides B and A during

is allowed because there is no simultaneous m/r/az

states 8 and 7 with the input signal shorted to

cycle on the side B during state 3--therefore, there

ground. Ncont integration begins with state 6.

is no need to wait for it to finish before ending the

Changing from ncont to cont mode occurs when t

INT

integration on side A.

Figure 15. Changing from Continuous Mode to Non-Continuous Mode

Figure 16. Changing from Non-Continuous Mode to Continuous Mode

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DATA FORMAT

DATA RETRIEVAL

CLK

DVALID

PDCDV

PDDCDV

HDDODC

HDDODV

PDDCDO

Input 32

MSB

Input

LSB

Input

MSB

Input 5

LSB

Input 4

MSB

Input 2

LSB

Input 1

MSB

Input 1

LSB

Input 32

MSB

DCLK

DOUT

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

Table 8. Ideal Output Code

(1)

vs Input Signal

INPUT

IDEAL OUTPUT CODE

The serial output data is provided in an offset binary

SIGNAL

FORMAT = 1

FORMAT = 0

code as shown in

Table 8

. The Format bit in the

100% FS

1111 1111 1111 1111 1111

1111 1111 1111 1111

configuration register selects how many bits are used

0.001531% FS

0000 0001 0000 0001 0000

0000 0001 0000 0001

in the output word. When Format = 1, 20 bits are

0.001436% FS

0000 0001 0000 0000 1111

0000 0001 0000 0000

used. When Format = 0, the lower 4 bits are

0.000191% FS

0000 0001 0000 0000 0010

0000 0001 0000 0000

truncated so that only 16 bits are used. Note that the

0.000096% FS

0000 0001 0000 0000 0001

0000 0001 0000 0000

LSB size is 16 times bigger when Format = 0. An
offset is included in the output to allow slightly

0% FS

0000 0001 0000 0000 0000

0000 0001 0000 0000

negative inputs (for example, from board leakages)

0.3955% FS

0000 0000 0000 0000 0000

0000 0000 0000 0000

from

clipping

the

reading.

This

offset

approximately 0.4% of the positive full-scale.

(1)

Excludes the effects of noise, INL, offset, and gain errors.

Setting the Format bit = 0 (16-bit output word) will

In both the continuous and non-continuous modes of

reduce the time needed to retrieve data by 20%

operation, the data from the last conversion is

since there are fewer bits to shift out. This can be

available for retrieval on the falling edge of DVALID

useful in multichannel systems requiring only 16 bits

(see

Figure 17

and

Table 9

). Data is shifted out on

of resolution.

the falling edge of the data clock, DCLK.

Make sure not to retrieve data around changes in
CONV because this can introduce noise. Stop
activity on DCLK at least 10µs before or after a
CONV transition.

Figure 17. Digital Interface Timing Diagram for Data Retrieval From a Single DDC232

Table 9. Timing for DDC232 Data Retrieval

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

PDCDV

Propagation Delay from Falling Edge of CLK to DVALID Low

PDDCDV

Propagation Delay from Falling Edge of DCLK to DVALID High

HDDODV

Hold Time that DOUT is Valid Before the Falling Edge of DVALID

400

HDDODC

Hold Time that DOUT is Valid After Falling Edge of DCLK

PDDCDO

(1)

Propagation Delay from Falling Edge of DCLK to Valid DOUT

(1)

With a maximum load of one DDC232 (4pF typical) with an additional load of 5pF.

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Cascading Multiple Converters

I
N

Sensor

DIN

DOUT

DDC232

I
D

Data

Retrieval

Output

Data Clock

DIN

DOUT

DDC232

I
D

DIN

DOUT

DDC232

I
D

DIN

DOUT

DDC232

I
D

CLK

DVALID

DCLK

DIN

STDIDC

HDDIDC

DOUT

Input

128

MSB

Input

128

MSB

Input

128

LSB

Input

127

MSB

Input 3

LSB

Input 2

MSB

Input 2

LSB

Input 1

MSB

Input 1

LSB

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

Figure 19

shows the timing diagram when the DIN

input

used

daisy-chain

several

devices.

Multiple DDC232 units can be connected in serial

Table 10

gives the timing specification for data

configuration; see

Figure 18

retrieval using DIN.

DOUT can be used with DIN to daisy-chain multiple
DDC232 devices together to minimize wiring. In this
mode of operation, the serial data output is shifted
through multiple DDC232s; see

Figure 18

Figure 18. Daisy-Chained DDC232s

Figure 19. Timing Diagram When Using DDC232 DIN Function; See

Figure 18

Table 10. Timing for DDC232 Data Retrieval Using DIN

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

STDIDC

Set-Up Time from DIN to Falling Edge of DCLK

HDDIDC

Hold Time for DIN After Falling Edge of DCLK

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RETRIEVAL BEFORE CONV TOGGLES

INT

CMDR

)

SDCV

(20

32)

DCLK

(1)

1000

286.8

(640)(100ns)

11.14

11 DDC232

(2)

...

Side B

Data

Side A

Data

INT

CMDR

SDCV

CONV

DVALID

DCLK

DOUT

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

(CONTINUOUS MODE)

NOTE: (16 × 32)

DCLK

is used for FORMAT = 0,

Data retrieval before CONV toggles is the most

where t

DCLK

is the period of the data clock. For

straightforward method. Data retrieval begins soon

example, if t

INT

= 1000µs and DCLK = 10MHz, the

after DVALID goes low and finishes before CONV

maximum number of DDC232s with FORMAT = 1 is

toggles,

shown

Figure

For

best

shown in

Equation 2

performance, data retrieval must stop t

SDCV

before

CONV toggles. This method is most appropriate for
longer

integration

times.

The

maximum

time

available for readback is t

INT

CMDR

SDCV

. For

(or 13 for FORMAT = 0)

DCLK = 10MHz and CLK = 5MHz, the maximum
number of DDC232s that can be daisy-chained
together (FORMAT = 1) is calculated by

Equation 1

Figure 20. Readback Before CONV Toggles

Table 11. Timing for Readback

CLK = 5MHz, Clk_4x = 0

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

SDCV

Data Retrieval Shutdown Before or After Edge of CONV

µs

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RETRIEVAL AFTER CONV TOGGLES

266

(20

32)

DCLK

(3)

INT

CMDR

SDCV

HDDODV

INT

...

Side A

Data

Side B

Data

Side A

Data

CONV

DVALID

DCLK

DOUT

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

(CONTINUOUS MODE)

For shorter integration times, more time is available if

NOTE: (16 × 32)

DCLK

is for FORMAT = 0.

data retrieval begins after CONV toggles and ends

For DCLK = 10MHz, the maximum number of

before the new data is ready. Data retrieval must

DDC232s is 4 (or 5 for FORMAT = 0).

wait t

SDCV

after CONV toggles before beginning. See

Figure 21

for an example of this. The maximum time

available for retrieval is t

CMDR

SDCV

+ t

HDDODV

regardless

INT

The

maximum

number

DDC232s that can be daisy-chained together with
FORMAT = 1 is calculated by

Equation 3

Figure 21. Readback After CONV Toggles

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RETRIEVAL BEFORE AND AFTER CONV

INT

SDCV

)

SDCV

)

HDDODV

(20

32)

DCLK

(4)

...

DCLK

DVALID

CONV

DOUT

Side B

Data

Side A

Data

INT

SDCV

HDDODV

INT

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

TOGGLES (CONTINUOUS MODE)

For the absolute maximum time for data retrieval,

NOTE: (16 × 32)

DCLK

is used for FORMAT = 0.

data can be retrieved before and after CONV
toggles. Nearly all of t

INT

is available for data

For t

INT

= 400

s and DCLK = 10MHz, the maximum

retrieval.

Figure 22

illustrates how this is done by

number

DDC232s

(or

for

combining the two previous methods. Pause the

FORMAT = 0).

retrieval during CONV toggling to prevent digital
noise, as discussed previously, and finish before the
next data is ready. The maximum number of
DDC232s that can be daisy-chained together with
FORMAT = 1 is:

Figure 22. Readback Before and After CONV Toggles

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RETRIEVAL: NON-CONTINUOUS MODE

...

IN T

N C D R 1

IN T

N C D R 2

Side A

Data

S ide B

Data

CO NV

D VA LID

DC LK

DO UT

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

The time available is t

NCDR2

INT

NCDR1

). Data

from the second integration must be retrieved before

Retrieving

non-continuous

mode

slightly

the next round of integration begins. This time is

different as compared with the continuous mode. As

highly dependent on the pattern used to generate

illustrated in

Figure 23

, DVALID goes low in time

CONV. As with the continuous mode, data retrieval

NCDR1

after the first integration completes. If t

INT

must halt before and after CONV toggles (t

SDCV

) and

shorter than this time, all of t

NCDR2

is available to

be completed before new data is ready (t

HDDODV

retrieve data before the other side data is ready. For
t

INT

> t

NCDR1

, the first integration data is ready before

the second integration completes. Data retrieval
must

delayed

until

the

second

integration

completes, leaving less time available for retrieval.

Figure 23. Readback in Non-Continuous Mode

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POWER-UP SEQUENCING

LAYOUT

POWER SUPPLIES AND GROUNDING

Power Supplies

RESET

POR

RST

AVDD

DVDD

AGND

DGND

DDC232

SBAS331C AUGUST 2004 REVISED SEPTEMBER 2006

Prior to power-up, all digital and analog inputs must
be low. At the time of power-up, all of these signals
should remain low until the power supplies have

Both AVDD and DVDD should be as quiet as

stabilized, as shown in

Figure 24

. At this time, begin

possible. It is particularly important to eliminate noise

supplying the master clock signal to the CLK pin.

from

AVDD

that

non-synchronous

with

the

Wait for time t

POR

, then give a RESET pulse. After

DDC232 operation.

Figure 25

illustrates how to

releasing RESET, the configuration register must be

supply power to the DDC232. Each supply of the

programmed.

Table 12

shows the timing for the

DDC232 should be bypassed with 10

F solid

power-up sequence.

tantalum capacitors. It is recommended that both the
analog and digital grounds (AGND and DGND) be
connected to a single ground plane on the printed
circuit board (PCB).

Figure 24. DDC232 Timing Diagram at Power-Up

Table 12. Timing for DDC232 Power-Up Sequence

Figure 25. Power-Supply Connections

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

Wait After Power-Up

POR

250

Until Reset

Shielding Analog Signal Paths

RST

Reset Low Width

µs

As with any precision circuit, careful PCB layout will
ensure the best performance. It is essential to make
short, direct interconnections and avoid stray wiring
capacitance--particularly at the analog input pins
and

QGND.

These

analog

input

pins

are

high-impedance

and

extremely

sensitive

extraneous noise. The QGND pin should be treated
as a sensitive analog signal and connected directly
to the supply ground with proper shielding. Leakage
currents between the PCB traces can exceed the
input bias current of the DDC232 if shielding is not
implemented. Digital signals should be kept as far as
possible from the analog input signals on the PCB.

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PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

DDC232CGXGR

ACTIVE

BGA

GXG

1000

TBD

SN/PB

Level-3-240C-168 HR

DDC232CGXGT

ACTIVE

BGA

GXG

250

TBD

SN/PB

Level-3-240C-168 HR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent

for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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PACKAGE OPTION ADDENDUM

www.ti.com

3-Oct-2006

Addendum-Page 1

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