Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS(
- PACKAGE/ORDERING INFORMATION
- PIN CONFIGURATION
- PIN DESCRIPTIONS
- ELECTRICAL CHARACTERISTICS: VS = + 2.7V to + 5.5V
- TYPICAL CHARACTERISTICS
- APPLICATIONS INFORMATION
- BASIC CONFIGURATION
- POWER SUPPLIES
- ADJUSTABLE CURRENT LIMIT AND CURRENT LIMIT FLAG PIN
- Setting the current limit
- Current Limit Accuracy
- Current Limit Flag Pin
- Quiescent Current Dependence on the Current Limit Setting
- CURRENT MONITOR
- ENABLE PIN-OUTPUT DISABLE
- ENSURING MICROCONTROLLER COMPATIBILITY
- RAIL TO RAIL OUTPUT RANGE
- RAIL TO RAIL INPUT RANGE
- OUTPUT PROTECTION
- THERMAL FLAG PIN
- POWER DISSIPATION AND SAFE OPERATING AREA
- FEEDBACK CAPACITOR IMPROVES RESPONSE
- PARALLEL OPERATION
- PowerPAD THERMALLY ENHANCED PACKAGE
- LAYOUT GUIDELINES
- APPLICATION CIRCUITS
OPA569
Rail-to-Rail I/O, 2A
POWER AMPLIFIER
DESCRIPTION
The OPA569 is a low-cost, high-current, operational amplifier
designed for driving a wide variety of loads while operating on
low-voltage supplies. It operates from either single or dual
supplies for design flexibility and has rail-to-rail swing on the
input and output. Typical output swing is within 150mV of the
supply rails, with output current of 2A. Output swing closer to
the rails is achievable with lighter loads.
The OPA569 is unity-gain stable, has low dc errors, is easy
to use, and free from the phase inversion problems found in
some power amplifiers. High performance is maintained at
voltage swings near the output rails.
The OPA569 provides an accurate user-selected current
limit that is set with an external resistor, or digitally adjusted
via a Digital-to-Analog Converter.
The OPA569 output can be independently disabled using the
Enable pin, saving power and protecting the load.
The I
MONITOR
pin provides a 1:475 bidirectional copy of the
output current. This eliminates the need for a series current
shunt resistor, allowing more voltage to be applied to the
load. This pin can be used for simple monitoring, or feedback
control to establish constant output current.
Two flags are provided: one for warning of thermal over-
stress, and one for current limit condition. The Thermal Flag
pin can be connected to the Enable pin to provide a thermal
shutdown solution.
Packaged in the Texas Instruments PowerPADTM package,
it is small and easy to heat-sink. The OPA569 is specified for
operation over the industrial temperature range, 40
C to
+85
C.
FEATURES
q
HIGH OUTPUT CURRENT: 2A
q
OUTPUT SWINGS TO: 150mV of Rails with I
O
= 2A
q
THERMAL PROTECTION
q
ADJUSTABLE CURRENT LIMIT
q
TWO FLAGS: Current Limit and Temperature
Warning
q
LOW SUPPLY VOLTAGE OPERATION: 2.7V to 5.5V
q
SHUTDOWN FUNCTION WITH OUTPUT DISABLE
q
SMALL POWER PACKAGE: SO-20 PowerPADTM
APPLICATIONS
q
THERMOELECTRIC COOLER DRIVER
q
LASER DIODE PUMP DRIVER
q
VALVE, ACTUATOR DRIVER
q
SYNCHRO, SERVO DRIVER
q
TRANSDUCER EXCITATION
q
GENERAL LINEAR POWER BOOSTER FOR
OP AMPS
q
PARALLELING OPTION FOR HIGHER
CURRENT APPLICATIONS
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002-2003, Texas Instruments Incorporated
SBOS264A DECEMBER 2002 REVISED DECEMBER 2003
OPA5
69
OPA569
Thermal
Flag
V
V
O
Parallel Out 1
Parallel Out 2
NOTE: (1) Connect
for thermal protection.
In
+In
V+
5
12,13
17, 18
7
4
8
2
14, 15
9
3
19
6
Current
Limit
Set
R
SET
(1)
Current
Limit
Flag
I
MONITOR
Enable
I
=
I
O
/475
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
OPA569
SBOS264A
2
www.ti.com
PIN #
NAME
DESCRIPTION
1, 10, 11, 20
PowerPAD
PowerPAD Connection Pins
2
Parallel Out 1
Connection for Paralleling Multiple
Amplifiers
3
Current Limit Set
Current Limit Set Pin
4
Current Limit Flag
Indicates When Part is in Current
Limit (Active LOW).
5
In
Inverting Input
6
+In
Noninverting Input
7
Thermal Flag
Indicates Thermal Stress (Active
LOW)
8
Enable
Enabled HIGH. Shut down LOW.
9
Parallel Out 2
Connection for Paralleling Multiple
Amplifiers
12, 13
V+
Positive Power-Supply Voltage
14, 15
V
O
Output
16
NC
No Internal Connection
17, 18
V
Negative Power-Supply Voltage
19
I
MONITOR
Provides 1:475 Bidirectional Copy
of Output Current.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
Supply Voltage ................................................................................. +7.5V
Output Current ............................................................... See SOA Curves
Signal Input Terminals (pins 2, 5, 6, and 9):
Voltage
(2)
............................................... (V) 0.5V to (V+) + 0.5V
Current
(2)
................................................................................
10mA
Output Short-Circuit
(3)
........ Continuous when thermal protection enabled
Current Monitor (pin 19) Short-Circuit ..................................... Continuous
Enable Pin (pin 8) .......................................... (V) 0.5V to (V) + 7.5V
PowerPAD (pins 1, 10, 11, 20, and pad) ...... (V) 0.5V to (V) + 0.5V
Current Limit Set (pin 3) ................................. (V) 0.5V to (V+) + 0.5V
Operating Temperature .................................................. 55
C to +125
C
Storage Temperature ..................................................... 65
C to +150
C
Junction Temperature .................................................................... +150
C
Lead Temperature (soldering, 10s) ............................................... +300
C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may de-
grade device reliability. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those specified is
not implied. (2) Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5V beyond the supply rails should
be current limited to 10mA or less. (3) Short-circuit to ground.
PIN CONFIGURATION
PACKAGE/ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
(1)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PowerPAD
(1)
Parallel Out 1
Current Limit Set
Current Limit Flag
In
+In
Thermal Flag
Enable
Parallel Out 2
PowerPAD
(1)
PowerPAD
(1)
I
MONITOR
V
(3)
V
(3)
NC
(2)
V
O
(3)
V
O
(3)
V+
(3)
V+
(3)
PowerPAD
(1)
OPA569
Metal
PowerPAD
Heat Sink
(Located
on
bottom
side)
NOTES: (1) PowerPAD pins 1, 10, 11, and 20 and the
PowerPAD should be connected to the most negative
supply (V) in either single or split supply configurations.
(2) NC means no internal connection.
(3) The following pin pairs must be connected together:
12 and 13; 14 and 15; 17 and 18.
Top View
SO
PIN DESCRIPTIONS
For the most current package and ordering information, see
the Package Option Addendum located at the end of this
data sheet.
OPA569
SBOS264A
3
www.ti.com
ELECTRICAL CHARACTERISTICS: V
S
= +2.7V to +5.5V
Boldface limits apply over the specified temperature range, T
A
= 40
C to +85
C.
At T
CASE
= +25
C, R
L
= 1k
, and connected to V
S
/ 2, unless otherwise noted.
NOTES: (1) See typical characteristic "Maximum Output Voltage vs Frequency." (2) See the typical characteristic "Total Harmonic Distortion + Noise vs Frequency."
(3) Swing to the rail is measured in final test. Under those conditions, the A
OL
is derived from characterization. (4) See Safe Operating Area (SOA) plots. (5) See typical
characteristic, "Overshoot vs Load Capacitance." (6) External current limit setting resistor is required. See Figure 1. (7) I
LIMIT
is the value of the desired current limit
and is equal to 9800 (I
SET
), where I
SET
is the current through the Current Limit Set pin (pin 3). Errors from this parameter can be calibrated out--see Applications
Information section. (8) V
SET
is a voltage reference that equals the difference between the voltage of the Current Limit Set pin and V, and is referenced to the negative
rail. Errors from this parameter can be calibrated out--see Applications Information section. (9) % Tolerance = [(I
OUT
/475) I
MONITOR
] 100/I
MONITOR
.
OPA569
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
OFFSET VOLTAGE
Input Offset Voltage
V
OS
I
O
= 0V, V
S
= +5V
0.5
2
mV
vs Temperature
dV
OS
/dT
T
A
= 40
C to +85
C
1.3
V/
C
vs Power Supply
PSRR
V
S
= +2.7V to +5.5V, V
CM
= (V) +0.55V
12
60
V/V
INPUT BIAS CURRENT
Input Bias Current
I
B
1
10
pA
vs Temperature
(doubles every 10
C)
Input Offset Current
I
OS
2
10
pA
NOISE
Input Voltage Noise Density, f = 1kHz
e
n
12
nV/
Hz
f = 0.1Hz to 10Hz
8
Vp-p
Current Noise Density, f = 1kHz
i
n
0.6
fA/
Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
V
CM
Linear Operation
(V) 0.1
(V+) + 0.1
V
Common-Mode Rejection Ratio
CMRR
V
S
= +5V, 0.1V < V
CM
< 3.2V
80
100
dB
V
S
= +5V, 0.1V < V
CM
< 5.1V
60
80
dB
INPUT IMPEDANCE
Differential
10
13
|| 4.5
|| pF
Common-Mode
10
13
|| 9
|| pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain
A
OL
0.2V
< V
O
< 4.8V, R
L
= 1k
, V
S
= +5V
100
126
dB
0.3V
< V
O
< 4.7V, R
L
= 1.15
, V
S
= +5V
90
dB
FREQUENCY RESPONSE
Gain Bandwidth Product
GBW
1.2
MHz
Slew Rate
SR
G = +1, V
O
= 4.0V Step
1.2
V/
s
Full-Power Bandwidth
(1)
See Typical Characteristics
Settling Time:
0.1%
G = 1, V
O
= 4.0V Step
5
s
Total Harmonic Distortion + Noise
(2)
THD+N
See Typical Characteristics
OUTPUT
Voltage Output Swing from Rail
V
O
R
L
= 1k
, A
OL
> 100dB
(V) + 0.2
(V
S
)
0.02
(V+) 0.2
V
I
O
=
2A, V
S
= +5V, A
OL
> 80dB
(3)
(V) + 0.3
(V
S
)
0.15
(V+) 0.3
V
Maximum Continuous Current Output: dc
(4)
2.4
A
Capacitive Load Drive
(5)
C
LOAD
See Typical Characteristics
Output Disabled
Output Impedance
12M || 570
|| pF
CURRENT LIMIT
Output Current Limit
(6)
Externally Adjustable
0.2 to
2.2
A
Current Limit Equation
I
LIMIT
= I
SET
9800
A
R
SET
Equation
R
SET
= 9800 (1.18V/I
LIMIT
)
Current Limit Tolerance
(7)
, Positive
I
LIMIT
= 1A
3
10
%
Negative
I
LIMIT
= 1A
3
15
%
Voltage on Current Limit Set Pin Tolerance
(8)
(V) + 1.05
(V) + 1.18
(V) + 1.3
V
OUTPUT CURRENT MONITOR (Pin 19)
Output Current Monitor
I
M
I
M
=
I
O
/475
A
Output Current Monitor Tolerance
(9)
, Positive
I
O
= +1A, R
MONITOR
= 400
3
10
%
Negative
I
O
= 1A, R
MONITOR
= 400
3
15
%
Compliance Voltage Range
Linear Operation
See Discussion on Current Monitor Section
OPA569
SBOS264A
4
www.ti.com
ENABLE/SHUTDOWN INPUT (Pin 8)
Enable Pin Bias Current
V
SD
= 0V
0.2
A
HIGH (Output enabled)
V
SD
Pin Open or Forced HIGH
(V) + 2.5
V
LOW (Output disabled)
V
SD
Pin Forced LOW
(V) + 0.8
V
Output Disable Time
R
L
= 1
0.5
s
Output Enable Time
R
L
= 1
15
s
THERMAL FLAG PIN (Pin 7)
Junction Temperature:
T
J
Alarm (Thermal Flag pin LOW)
Thermal Overstress
+147
C
Return to Normal Operation (Thermal Flag pin HIGH)
Normal Operation
+130
C
Thermal Flag Pin Voltage
Normal Operation I
pin 7
= +25
A
(V+) 0.8V
V+
V
During Thermal Overstress, I
pin 7
= 25
A
V
(V) + 0.8
V
CURRENT LIMIT FLAG PIN (Pin 4)
Current Limit Flag Pin Voltage
Normal Operation, I
pin 4
= +25
A
(V+) 0.8V
V+
V
During Current Limit, I
pin 4
= 25
A
V
(V) + 0.8
V
POWER SUPPLY
Specified Voltage Range
V
S
+2.7
+5.5
V
Operating Voltage Range
+2.7
+5.5
V
Quiescent Current
(10)
I
Q
I
O
= 0, I
LIMIT
= 200mA, V
S
= 5V
+3.4
+6
mA
I
O
= 0, I
LIMIT
= 2A, V
S
= 5V
+9
+11
mA
Quiescent Current in Shutdown Mode
I
O
= 0, V
SD
= 0.8V, V
S
= 5V
+0.01
mA
TEMPERATURE RANGE
Specified Range
Junction Temperature
40
+85
C
Operating Range
Junction Temperature
55
+125
C
Storage Range
65
+150
C
Thermal Resistance, Junction-to-Case
JC
0.37
C/W
Thermal Resistance, Junction-to-Ambient
JA
2oz Trace and 9in
2
Copper Pad
21.5
C/W
with Solder
ELECTRICAL CHARACTERISTICS: V
S
= +2.7V to +5.5V
(Cont.)
Boldface limits apply over the specified temperature range, T
A
= 40
C to +85
C.
At T
CASE
= +25
C, R
L
= 1k
, and connected to V
S
/ 2, unless otherwise noted.
OPA569
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
NOTE: (10) Quiescent current is a function of the current limit setting. See application section, "Adjustable Current Limit and Current Limit Flag Pin."
OPA569
SBOS264A
5
www.ti.com
TYPICAL CHARACTERISTICS
At T
A
= +25
C, V
S
= +5V, unless otherwise noted.
180
160
140
120
100
80
60
40
20
0
20
OPEN-LOOP GAIN AND PHASE vs FREQUENCY
Frequency (Hz)
1
10
100
1k
10k
100k
10M
1M
0.1
0
20
40
60
80
100
120
140
160
180
200
Phase (
)
A
OL
(dB)
120
100
80
60
40
20
0
POWER-SUPPLY AND COMMON-MODE
REJECTION RATIO vs FREQUENCY
Frequency (Hz)
PSRR and CMRR (dB)
1
10
100
1k
10k
100k
CMRR
PSRR
300
250
200
150
100
50
0
OUTPUT SWING TO POSITIVE RAIL
vs SUPPLY VOLTAGE
Supply Voltage (V)
Swing to Rail (mV)
2.7
3.0
3.5
4.0
4.5
5.0
5.5
I
OUT
= 200mA
I
OUT
= 2A
I
OUT
= 1A
300
250
200
150
100
50
0
OUTPUT SWING TO NEGATIVE RAIL
vs SUPPLY VOLTAGE
Supply Voltage (V)
Swing to Rail (mV)
2.7
3.0
3.5
4.0
4.5
5.0
5.5
I
OUT
= 200mA
I
OUT
= 2A
I
OUT
= 1A
300
250
200
150
100
50
0
OUTPUT SWING TO POSITIVE RAIL
vs TEMPERATURE
Temperature (
C)
Swing to Rail (mV)
55
35
15
5
25
45
65
85
V
S
= 2.7V, I
O
= 2A
V
S
= 5V, I
O
= 1A
V
S
= 2.7V, I
O
= 200mA
V
S
= 5V, I
O
= 2A
V
S
= 2.7V, I
O
= 1A
V
S
= 5V, I
O
= 200mA
300
250
200
150
100
50
0
OUTPUT SWING TO NEGATIVE RAIL
vs TEMPERATURE
Temperature (
C)
Swing to Rail (mV)
55
35
15
5
25
45
65
85
V
S
= 2.7V, I
O
= 2A
V
S
= 5V, I
O
= 1A
V
S
= 5V, I
O
= 200mA
V
S
= 5V, I
O
= 2A
V
S
= 2.7V, I
O
= 1A
V
S
= 2.7V, I
O
= 200mA
OPA569
SBOS264A
6
www.ti.com
TYPICAL CHARACTERISTICS
(Cont.)
At T
A
= +25
C, V
S
= +5V, unless otherwise noted.
1000
100
10
1
INPUT VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY
Frequency (Hz)
Input Voltage Noise (nV
Hz)
10
100
1k
10k
100k
0.1Hz TO 10Hz INPUT VOLTAGE NOISE
1
V/div
1s/div
6
5
4
3
2
1
0
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
Frequency (Hz)
Output Voltage (Vp-p)
100
1k
100k
10k
1M
V
S
= 5V
R
L
= 1k
R
L
= 1
R
L
= 1k
V
S
= 2.7V
R
L
= 1
10
1
0.1
0.01
0.001
TOTAL HARMONIC DISTORTION+NOISE
vs FREQUENCY
Frequency (Hz)
THD+N (%)
20
100
1k
10k 20k
R
L
= 2
R
L
= 8
R
L
= 1k
10
8
6
4
2
0
QUIESCENT CURRENT vs SUPPLY VOLTAGE
Supply Voltage (V)
Quiescent Current (mA)
2.7
3
3.5
4
4.5
5
5.5
Current Limit = 1A
Current Limit = 2A
Current Limit = 200mA
10
8
6
4
2
0
QUIESCENT CURRENT vs TEMPERATURE
Temperature (
C)
Quiescent Current (mA)
55
35
5
15
25
45
65
105
85
125
I
Q
(I
LIMIT
= 2A)
I
Q
(I
LIMIT
= 200mA)
OPA569
SBOS264A
7
www.ti.com
TYPICAL CHARACTERISTICS
(Cont.)
At T
A
= +25
C, V
S
= +5V, unless otherwise noted.
12
10
8
6
4
2
0
SHUTDOWN CURRENT vs SUPPLY VOLTAGE
Supply Voltage (V)
Shutdown Current (
A)
2.7
3
3.5
4
4.5
5
5.5
I
LIMIT
= 200mA, 1A, and 2A
SHUTDOWN CURRENT vs TEMPERATURE
Temperature (
C)
Shutdown Current (
A)
12
10
8
6
4
2
0
55
35
5
15
25
45
65
105
85
125
10
8
6
4
2
0
QUIESCENT CURRENT vs CURRENT LIMIT SETTING
Current Limit Setting (A)
Quiescent Current (mA)
0
0.5
1
1.5
2
2.5
10000
1000
100
10
1
0.1
0.01
INPUT BIAS CURRENT vs TEMPERATURE
Temperature (
C)
Input Bias Current
(pA)
55
35
15
5
25
45
65
85
105
125
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
SLEW RATE vs LOAD RESISTANCE
Load Resistance (
)
Slew Rate (V/
s)
1
10
SR
SR+
100
1000
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
SLEW RATE vs TEMPERATURE
Temperature (
C)
Slew Rate (V/
s)
55
5
25
45
35
15
65
85
105
125
SR
SR+
OPA569
SBOS264A
8
www.ti.com
TYPICAL CHARACTERISTICS
(Cont.)
At T
A
= +25
C, V
S
= +5V, unless otherwise noted.
1.2
1.19
1.18
1.17
1.16
VOLTAGE ON CURRENT LIMIT SET PIN
vs TEMPERATURE
Temperature (
C)
[V
SET
(V
)] (V)
55
35
15
5
65
85
105
25
45
125
1.25
1.2
1.15
1.1
1.05
VOLTAGE ON CURRENT LIMIT SET PIN
vs SUPPLY VOLTAGE
Supply Voltage (V)
[V
SET
(V
)]
2.7
3
3.5
4
4.5
5
5.5
Current Limit = 1A
Current Limit = 2A
Current Limit = 200mA
OFFSET VOLTAGE
PRODUCTION DISTRIBUTION
Offset Voltage (mV)
2
1.8
1.6
1.4
1.2
1.0
Population
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2
Typical Production
Distribution of
Packaged Units.
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
Population
Drift (
V/
C)
10
9
8
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
9
10
Typical Production
Distribution of
Packaged Units.
SMALL-SIGNAL STEP RESPONSE
(G = +1, R
L
= 1k
)
50mV/div
10
s/div
LARGE-SIGNAL STEP RESPONSE
(G = +1, R
L
= 1k
)
1V/div
20
s/div
OPA569
SBOS264A
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TYPICAL CHARACTERISTICS
(Cont.)
At T
A
= +25
C, V
S
= +5V, unless otherwise noted.
SMALL-SIGNAL STEP RESPONSE
(G = +1, R
L
= 10
)
50mV/div
10
s/div
LARGE-SIGNAL STEP RESPONSE
(G = +1, R
L
= 10
)
1V/div
20
s/div
SMALL-SIGNAL STEP RESPONSE
(G = +1, R
L
= 1
)
50mV/div
20
s/div
LARGE-SIGNAL STEP RESPONSE
(G = +1, R
L
= 1
)
1V/div
20
s/div
ENABLE
(10
Load)
2V/div
1V/div
4
s/div
Enable/Disable 0.8 to 2.5V
Above Negative Supply
Output Driven to +2V
ENABLE
(1
Load)
10
s/div
Enable/Disable 0.8 to 2.5V
Above Negative Supply
Output Driven to +2V
1V/div
2V/div
OPA569
SBOS264A
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www.ti.com
TYPICAL CHARACTERISTICS
(Cont.)
At T
A
= +25
C, V
S
= +5V, unless otherwise noted.
DISABLE
(10
Load)
200ns/div
Enable/Disable 0.8 to 2.5V
Above Negative Supply
Output Driven to +2V
2V/div
1V/div
DISABLE
(1
Load)
200ns/div
Enable/Disable 0.8 to 2.5V
Above Negative Supply
Output Driven
to +2V
2V/div
1V/div
POWER ON
(1
Load)
1ms/div
Output Driven to +2V
Supply 0V to 5V
5V/div
1V/div
POWER OFF
(1
Load)
1ms/div
1V/div
5V/div
Output Driven to +2V
Supply 5V to 0V
IN AND OUT OF CURRENT LIMIT TRANSIENT
(R
L
= 0.75
, Current Limit = 2A)
V
OUT
(2V/div)
Current Limit Flag
(5V/div)
200
s/div
IN AND OUT OF CURRENT LIMIT TRANSIENT
(R
L
= 7.5
, Current Limit = 200mA)
V
OUT
(2V/div)
Current Limit Flag
(5V/div)
200
s/div
OPA569
SBOS264A
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TYPICAL CHARACTERISTICS
(Cont.)
At T
A
= +25
C, V
S
= +5V, unless otherwise noted.
OVERLOAD RECOVERY
(G = +1)
1V/div
40
s/div
V
IN
V
OUT
NO PHASE INVERSION WITH INPUTS
LARGER THAN SUPPLY VOLTAGE
(G = +1, R
L
= 10
)
1V/div
1ms/div
V
IN
V
OUT
15
10
5
0
5
10
15
CURRENT MONITOR AND CURRENT LIMIT ERROR
vs SUPPLY VOLTAGE
Supply Voltage (V)
Current Monitor and
Current Limit Error (%)
I
LIMIT
+
I
LIMIT
I
MONITOR
I
MONITOR
+
2.7
3
3.5
4
4.5
5
5.5
15
10
5
0
5
10
15
CURRENT MONITOR AND CURRENT
LIMIT ERROR vs TEMPERATURE
Temperature (
C)
Current Monitor and
Current Limit Error (%)
55
35
I
LIMIT
+
I
LIMIT
15
5
25
45
65
85
I
MONITOR
+
I
MONITOR
15
10
5
0
5
10
15
CURRENT MONITOR AND CURRENT LIMIT ERROR
vs OUTPUT CURRENT
Output Current (A)
Current Monitor and
Current Limit Error (%)
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
I
LIMIT
I
MONITOR
+
I
LIMIT
+
I
MONITOR
50
40
30
20
10
0
OVERSHOOT vs LOAD CAPACITANCE
(G = +1, R
L
= 1k
)
Load Capacitance (pF)
Overshoot (%)
10
100
1k
10k
OPA569
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APPLICATIONS INFORMATION
BASIC CONFIGURATION
Figure 1 shows the OPA569 connected as a basic non-
inverting amplifier; however, the OPA569 can be used in
virtually any op amp configuration. A current limit setting
resistor (R
SET
, in Figure 1) is essential to the OPA569's
operation, and cannot be omitted.
Power-supply terminals should be bypassed with low series
impedance capacitors. Using a larger tantalum and smaller
ceramic type in parallel is recommended. Power-supply
wiring should have low series impedance.
POWER SUPPLIES
The OPA569 operates with excellent performance from a
single (+2.7V to +5.5V) supply or from dual supplies. Power
supply voltages do not need to be equal as long as the total
voltage remains below 5.5V. Parameters that vary signifi-
cantly with operating voltage are shown in the typical charac-
teristics section.
ADJUSTABLE CURRENT LIMIT AND CURRENT
LIMIT FLAG PIN
The OPA569 provides over-current protection to the load
through its accurate, user-adjustable current limit (pin 3). The
current limit value, I
LIMIT
, can be set from 0.2A to 2.2A by
controlling the current through the Current Limit Set pin. The
current limit, I
LIMIT
, will be 9800 I
SET
; where I
SET
is the current
through the Current Limit Set pin. Setting the current limit
requires no special power resistors. The output current does
not flow through this pin.
Setting the current limit
As illustrated in Figure 2, the simplest method of setting the
current limit is to connect a resistor or potentiometer between
FIGURE 1. Basic Connections.
FIGURE 2. Setting the Current Limit--Resistor Method.
V
IN
R
1
R
2
47
F
Enable
(2)
47
F
0.1
F
Current
Limit Set
47
F
12,
13
14,
15
19
5
6
8
3
17,
18
0.1
F
R
SET
(
)
I
LIMIT
(A)
23.2k
11.5k
7.68k
5.76k
0.5
1.0
1.5
2.0
R
SET
(1)
V+
NOTES: (1) R
SET
sets the current
limit value from 0.2A to 2.2A.
R
SET
can be a potentiometer to
easily adjust current limit and
calibrate out errors at the current
limit node. (2) Enable--pull LOW
to disable output.
V
O
I
MONITOR
V
OPA569
R
SET
V
ADJUST
(1)
(b) Resistor/Voltage Source Method
NOTE: (1) This voltage source must be able to
sink the current from the Current Limit Set pin,
which is I
LIMIT
/9800.
1.18V
V
I
LIMIT
= 9800 (1.18V V
ADJUST
)
R
SET
5
6
3
14,
15
17,
18
5
6
3
14,
15
17,
18
R
POT
(a) Resistor or Potentiometer Method
Putting a set resistor in series with the potentiometer
will prevent potential short-circuit on pin.
1.18V
V
I
LIMIT
= 9800 (1.18V/R
SET
)
the current limit set pin and V, the negative supply, accord-
ing to the formula:
I
LIMIT
= 9800 (1.18V/R
SET
)
Alternatively, the output current limit can be set by applying
a voltage source in series with a resistance using the equa-
tion:
I
LIMIT
= 9800 [(1.18V V
ADJUST
)/R
SET
]
The voltage source will be referenced to V.
OPA569
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Current Limit Accuracy
Internally separate circuits monitor the positive and negative
current limits. Each circuit output is compared to a single
internal reference that is set by the user with an external
resistor or a resistor/voltage source combination. The OPA569
employs a patented circuit technique to achieve an accurate
and stable current limit throughout the full output range. The
initial accuracy of the current limit is typically within 3%;
however, due to internal matching limitations, the error can
be as much as 15%. The variation of the current limit with
factors such as output current level, output voltage and
temperature is shown in the Typical Characteristics section.
When the accuracy of one current limit (sourcing or sinking)
is more important than the other, it is possible to set its
accuracy to better than 1% by adjusting the external resistor
or the applied voltage. The accuracy of the other current limit
will still be affected by internal matching.
Current Limit Flag Pin
The OPA569 features a Current Limit Flag pin (pin 4) that
can be monitored to determine when the part is in current
limit. The output signal of the current limit flag pin is compat-
ible to standard logic in single supply applications. The
output signal is a CMOS logic gate that switches from V+ to
V to indicate that the amplifier is in current limit. This flag
output pin can source and sink up to 25
A. Additional
parasitic capacitance between pins 3 and 4 can cause
instability at the edge of the current limit. Avoid routing these
traces in parallel close to each other.
Quiescent Current Dependence on the
Current Limit Setting
The OPA569 is a low power amplifier, with a typical 3.4mA
quiescent current (with the current limit configured for 200mA).
The quiescent current varies with the current limit setting--
it increases 0.5mA for each additional 200mA increase in
the current limit, as shown in Figure 3.
FIGURE 3. Quiescent Current vs Current Limit Setting.
10
8
6
4
2
0
QUIESCENT CURRENT vs CURRENT LIMIT SETTING
Current Limit Setting (A)
Quiescent Current (mA)
0
0.5
1
1.5
2
2.5
FIGURE 4. Transimpedance Amplifier to Monitor Load
Current.
OPA569
R
L
I
O
I
O
/475
I
MONITOR
V
O
V
O
= 1V
at I
O
= 1A
2.5V
5
6
19
14,
15
12,
13
R = 475
C
In
+In
+2.5V
OPA348
17,
18
CURRENT MONITOR
The OPA569 features an accurate output current monitor
(I
MONITOR
) without requiring the use of series resistance with
the load. This increases efficiency significantly and provides
better overall swing-to-supply performance.
An internal circuit creates a 1:475 copy of the output current.
This copy of the output current can be monitored indepen-
dently or it can be used in applications such as current
control drive, setting non-symmetric positive and negative
current limits or paralleling two or more devices for increased
output current drive. When not being used, the Current
Monitor pin may be left floating.
Some restrictions apply when using the current monitor
function. When the main amplifier is sourcing current, the
current monitor circuit must be sourcing current. Likewise,
when the main amplifier is sinking current, the current moni-
tor circuit must also be sinking current. Additionally, the
swing on the I
MONITOR
pin is smaller than the output swing.
When the amplifier is sourcing current, the voltage of the
Current Monitor pin must be at least two hundred millivolts
less than the output voltage of the amplifier. Conversely,
when the amplifier is sinking current, the voltage of the
Current Monitor pin must be at least two hundred millivolts
greater than the output voltage of the amplifier. Resistive
loads are able to meet these restrictions. Other types of
loads may cause invalid current monitor values.
A simple way to monitor the load current and meet these
requirements is to connect a resistor (with resistance less
than 400 R
L
) from the I
MONITOR
pin to the same potential to
which the other side of the load is connected. Another
method is to use a transimpedance amplifier, as shown in
Figure 4. This circuit must assure that the potential of the
I
MONITOR
pin remains in the valid voltage range by connecting
it to the same potential to which the load is connected--most
likely ground for dual supply or mid-supply for single-supply
applications.
OPA569
SBOS264A
14
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The accuracy of the current copy is reduced with small output
currents. An internal circuit monitors the direction of the
output current and enables the positive or the negative
current monitoring circuitry accordingly. There is an approxi-
mate 20
s delay in the change of current direction. The
switching point is near quiescent conditions and may cause
current monitor inaccuracy with small output currents.
ENABLE PIN--OUTPUT DISABLE
The Enable pin can disable the OPA569 within microsec-
onds. When disabled, the amplifier draws less than 10
A and
its output enters a high-impedance state that allows multi-
plexing. It is important to note that when the amplifier is
disabled, the Thermal Flag pin circuitry continues to operate.
This feature allows use of the Thermal Flag pin output to
implement thermal protection strategies. For more details,
please see the section on thermal protection.
The OPA569 Enable pin has an internal pull-up circuit, so it
does not have to be connected to the positive supply for
normal operation. To disable the amplifier, the Enable pin
must be connected to no more than (V) + 0.8V. To enable
the amplifier, either allow the Enable pin to float or connect
it to at least (V) + 2.5V.
The Enable pin is referenced to the negative supply (V).
Therefore, shutdown operation is slightly different in single-
supply and dual-supply applications.
In single-supply operation, V typically equals common
ground, thus the enable/disable logic signal and the OPA569
Enable pin are referenced to the same potential. In this
configuration, the logic level and the OPA569 Enable pin can
simply be tied together. Disable occurs for voltage levels of
less than 0.8V. The OPA569 is enabled at logic levels
greater than 2.5V.
In dual-supply operation, the logic level is referenced to a
logic ground. However, the OPA569 Enable pin is still refer-
enced to V. To disable the OPA569, the voltage level of the
logic signal needs to be level-shifted. This can be done using
an optocoupler, as shown in Figure 5.
Examples of output behavior during disabled and enabled
conditions with various load impedances are shown in the
typical characteristics section. Please note that this behavior
is a function of board layout, load impedances and bypass
strategies. For sensitive loads, the use of a low-pass filter or
other protection strategy is recommended.
ENSURING MICROCONTROLLER COMPATIBILITY
Not all microcontrollers output the same logic state after
power-up or reset. 8051-type microcontrollers, for example,
output logic HIGH levels on their ports while other models
power up with logic LOW levels after reset.
In configuration (a) shown in Figure 5, the enable/disable
signal is applied on the cathode side of the photodiode within
the optocoupler. A logic HIGH level causes the OPA569 to
be enabled, and a logic LOW level disables the OPA569. In
configuration (b) of Figure 5, with the logic signal applied on
the anode side, a high level disables the OPA569 and a low
level enables the op amp.
RAIL TO RAIL OUTPUT RANGE
The OPA569 has a class AB output stage with common
source transistors that are used to achieve rail-to-rail output
swing. It was designed to be able to swing closer to the rail
than other existing linear amplifiers, even with high output
current levels. A quick way to estimate the output swing with
various output current requirements is by using the equation:
V
SWING
[typical] = 0.1 I
O
Plots of the Output Swing vs Output Current, Supply Voltage,
and Temperature are provided in the typical characteristics
section.
Optocoupler
4N38
NOTE: (1) Optional--may be required
to limit leakage current of optocoupler
at high temperatures.
Enable
V+
V
O
5
6
8
14,
15
17,
18
12,
13
(a) +5V
(b) HCT or TTL In
HCT or
TTL In
(a)
(b)
OPA569
(1)
V
FIGURE 5. OPA569 Shutdown Configuration for Dual
Supplies.
OPA569
SBOS264A
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RAIL TO RAIL INPUT RANGE
The input common-mode voltage range of the OPA569
extends 100mV beyond the supply rails. This is achieved by
a complementary input stage with an N-channel input differ-
ential pair in parallel with a P-channel differential pair. The
N-channel input pair is active for input voltages close to the
positive rail while the P-channel input pair is active for input
voltages close to the negative rail. The transition point is
typically at (V+) 1.3V, and there is a small transition region
around the switching point where both transistors are on. It
is important to note that the two input pairs can have offsets
of different signs and magnitudes. Therefore, as the transi-
tion point is crossed, the offset of the amplifier changes. This
offset shift accounts for the reduced common-mode rejection
ratio over the full input common-mode range.
OUTPUT PROTECTION
Reactive and EMF-generating loads can return load current
to the amplifier, causing the output voltage to exceed the
power-supply voltage. This damaging condition can be
avoided with clamp diodes from the output terminal to the
power supplies, as shown in Figure 6. Schottky rectifier
diodes with a 3A or greater continuous rating are recom-
mended.
THERMAL FLAG PIN
The OPA569 has thermal sensing circuitry that provides a
warning signal when the die temperature exceeds safe limits.
Unless the Thermal Flag is connected to the Enable pin,
when this flag is triggered, the part continues to operate even
FIGURE 6. Output Protection Diode.
OPA569
Output Protection Diode
Output Protection Diode
Current
Limit
Set
R
SET
V
O
+V
12,
13
3
17,
18
In
+In
14,
15
V
Enable Pin
14,
15
8
5
6
Thermal
Flag Pin
Disable
On
7
AND
OPA569
FIGURE 7. Enable/Shutdown Control Using Thermal Flag Pin
and External Control Signal.
though the junction temperature exceeds 150
C. This allows
maximum usable operation in very harsh conditions but
degrades reliability. The Thermal Flag pin can be used to
provide for orderly system shutdown before failure occurs. It
can be also used to evaluate the thermal environment to
determine need for and appropriate design of a shutdown
mechanism.
The thermal flag output signal is from a CMOS logic gate that
switches from V+ to V to indicate that the amplifier is in
thermal limit. This flag output pin can source and sink up to
25
A. The Thermal Flag pin is HIGH during normal opera-
tion. Power dissipated in the amplifier will cause the junction
temperature to rise. When the junction temperature exceeds
150
C, the Thermal Flag pin will go LOW, and remain LOW
until the amplifier has cooled to 130
C. Despite this hyster-
esis, with a method of orderly shutdown, the Thermal Flag
pin can cycle on and off, depending on load and signal
conditions. This limits the dissipation of the amplifier but may
have an undesirable effect on the load. This temperature
range exceeds the absolute maximum temperature rating
and is intended to protect the device from excessive tem-
peratures that can cause damage. Brief and infrequent
excursions in this temperature range are likely to be toler-
ated, but are not recommended.
It is possible to connect the Thermal Flag pin directly to the
Enable pin for automatic shutdown protection. When both
thermal shutdown and the amplifier enable/disable functions
are desired, the externally generated control signal and the
Thermal Flag pin outputs should be combined with an AND
gate, as shown on Figure 7. The temperature protection was
designed to protect against overload conditions. It was not
intended to replace proper heatsinking. Continuously running
the OPA569 in and out of thermal shutdown will degrade
reliability.
OPA569
SBOS264A
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Any tendency to activate the thermal protection circuit indi-
cates excessive power dissipation or an inadequate heat
sink. For reliable, long term, continuous operation, the junc-
tion temperature should be limited to 125
C maximum. To
estimate the margin of safety in a complete design (including
heat sink), increase the ambient temperature until the ther-
mal protection is triggered. Use worst-case loading and
signal conditions. For good, long-term reliability, thermal
protection should trigger more than 25
C above the maxi-
mum expected ambient conditions of your application. This
produces a junction temperature of 125
C at the maximum
expected ambient condition.
Fast transients of large output current swings (for example
switching quickly from sourcing 2A to sinking 2A) may cause
a glitch on the Thermal Flag pin. When switching large
currents is expected, the use of extra bypass between the
supplies or a low-pass filter on the Thermal Flag pin is
recommended.
POWER DISSIPATION AND
SAFE OPERATING AREA
Power dissipation depends on power supply, signal and load
conditions. It is dominated by the power dissipation of the
output transistors. For DC signals, power dissipation is equal
to the product of output current, I
OUT
and the output voltage
across the conducting output transistor (V
S
-V
OUT
). Dissipa-
tion with AC signals is lower. Application Bulletin AB-039
(SBOA022) explains how to calculate or measure power
dissipation with unusual signals and loads and can be found
at the TI web site (www.ti.com).
Output short-circuits are particularly demanding for the am-
plifier because the full supply voltage is seen across the
conducting transistor. It is very important to note that the
temperature protection will not shut the part down in over-
temperature conditions, unless the Thermal Flag pin is con-
nected to the Enable pin; see the section on Thermal Flag.
Figure 8 shows the safe operating area at room temperature
with various heatsinking efforts. Note that the safe output
current decreases as (V
S
V
OUT
) increases. Figure 9 shows
the safe operating area at various temperatures with the
PowerPAD being soldered to a 2 oz copper pad.
The power that can be safely dissipated in the package is
related to the ambient temperature and the heatsink design.
The PowerPAD package was specifically designed to pro-
vide excellent power dissipation, but board layout greatly
influences the heat dissipation of the package. Refer to
the "PowerPAD Thermally Enhanced Package" section for
further details.
The OPA569 has a junction-to-ambient thermal resistance
(
JA
) value of 21.6
C/W when soldered to 2oz copper plane.
This value can be further decreased to 12
C/W by the
addition of forced air. Figure 10 shows the junction-to-
ambient thermal resistance of the DWP-20 package.
FIGURE 10. Junction-to-Ambient Thermal Resistance with
Various Heatsinking Efforts.
FIGURE 8. Safe Operating Area at Room Temperature.
FIGURE 9. Safe Operating Area at Various Ambient Tempera-
tures. PowerPAD soldered to a 2oz copper pad.
10
1
0.1
V
S
V
OUT
(V)
SAFE OPERATING AREA AT ROOM TEMPERATURE
Output Current (A)
0
1
2
3
4
5
6
Copper--soldered,
without forced air.
Copper--soldered,
with 150lfm airflow.
Copper--soldered,
with 500lfm airflow.
Current is limited by the
maximum output current.
Copper--soldered,
with 250lfm airflow.
10
1
0.1
V
S
V
OUT
(V)
SAFE OPERATING AREA AT VARIOUS
AMBIENT TEMPERATURES
Output Current (A)
0
1
2
3
4
5
6
T
A
= +125
C
T
A
= +85
C
T
A
= +25
C
T
A
= 40
C
T
A
= 0
C
Current is limited by
the maximum output
current.
HEATSINKING METHOD
JA
The part is soldered to a 2 oz copper pad under the
21.6
exposed pad.
Soldered to copper pad with forced airflow (150lfm).
15.1
Soldered to copper pad with forced airflow (250lfm).
13.2
Soldered to copper pad with forced airflow (500lfm).
12.0
OPA569
SBOS264A
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Junction temperature should be kept below 125
C for reliable
operation. The junction temperature can be calculated by:
T
J
= T
A
+ P
D
JA
where
JA
=
JC
+
CA
T
J
= Junction Temperature (
C)
T
A
= Ambient Temperature (
C)
P
D
= Power Dissipated (W)
JA
= Junction-to-Ambient Thermal Resistance
JC
= Junction-to-Case Thermal Resistance
CA
= Case-to-Air Thermal Resistance
The Maximum Power Dissipation vs Temperature for the
heatsinking methods listed in Figure 10 is shown in Figure 11.
To appropriately determine required heatsink area, required
power dissipation should be calculated and the relationship
between power dissipation and thermal resistance should be
considered to minimize shutdown conditions and allow for
proper long-term operation (junction temperature of 125
C).
Once the heatsink area has been selected, worst-case load
conditions should be tested to ensure proper thermal protec-
tion.
For applications with limited board size, refer to Figure 12 for
the approximate thermal resistance relative to heatsink area.
Increasing the heatsink area beyond 2in
2
provides little
improvement in thermal resistance. To achieve the 21.5
C/W
stated in the Electrical Characteristics, a copper plane size of
9in
2
was used. The SO-20 PowerPAD package is well suited
for continuous power levels, as shown in Figure 11. Higher
power levels may be achieved in applications with a low
on/off duty cycle.
FIGURE 11. Maximum Power Dissipation vs Temperature.
FEEDBACK CAPACITOR IMPROVES RESPONSE
For optimum settling time and stability with higher impedance
feedback networks (R
F
> 50k
), it may be necessary to add
a feedback capacitor across the feedback resistor, R
F
, as
shown in Figure 13. This capacitor compensates for the zero
created by the feedback network impedance and the OPA569
input capacitance (and any parasitic layout capacitance).
The effect becomes more significant with higher impedance
networks.
The size of the capacitor needed is estimated using the
equation:
R
IN
C
IN
= R
F
C
F
where C
IN
is the sum of the input capacitance of the OPA569
plus the parasitic layout capacitance.
14
12
10
8
6
4
2
0
Temperature (
C)
MAXIMUM POWER DISSIPATION
vs TEMPERATURE
Power Dissipated in Package (W)
55
30
20
5
45
70
95
120
With 250lfm Airlow
With 150lfm Airlow
Without Forced Air
With 500lfm Airlow
T
J
= 150
C
FIGURE 12. Thermal Resistance vs Circuit Board Copper
Area.
35
30
25
20
15
10
Thermal Resistance,
JA
(
C/W)
0
1
2
3
4
5
Copper Area (inches
2
)
THERMAL RESISTANCE vs COPPER AREA
OPA569
Surface-Mount Package
OPA569
V+
V
V
OUT
V
IN
R
IN
5
12,
13
14,
15
17,
18
6
R
IN
C
IN
= R
F
C
F
R
F
C
L
C
IN
C
IN
C
F
Where C
IN
is equal to the OPA569's input
capacitance (approximately 9pF) plus any
parasitic layout capacitance.
FIGURE 13. Feedback Capacitor for use with Higher Imped-
ance Networks.
OPA569
SBOS264A
18
www.ti.com
PARALLEL OPERATION
The OPA569 allows parallel operation of multiple op amps to
extend output current capability or improve the output volt-
age swing to the rail. Special internal circuitry causes the
load current to be shared equally between two (or more) op
amps.
Figure 14 shows two ways to connect the input terminals.
When the amplifier inputs are connected in parallel, the
effective offset voltage is averaged and the bandwidth and
slew rate performance are the same as that of a single
amplifier. It is also possible to use one amplifier to be the
"master" and connect the other inputs to a voltage within the
common-mode input range of the amplifier; however, slew
rate and bandwidth performance will be degraded.
For best performance, keep additional capacitance at the
Parallel Out pins to a minimum and avoid routing these lines
close to other lines that might see large voltage swings.
FIGURE 14. Parallel Operation.
Mold Compound (Epoxy)
Leadframe Die Pad
Exposed at Base of the Package
Leadframe (Copper Alloy)
IC (Silicon)
Die Attach (Epoxy)
FIGURE 15. Section View of a PowerPAD Package.
PowerPAD THERMALLY ENHANCED PACKAGE
The OPA569 uses the SO-20 PowerPAD package, a ther-
mally enhanced, standard size IC package designed to
eliminate the use of bulky heatsinks and slugs traditionally
used in thermal packages. This package can be easily
mounted using standard PCB assembly techniques.
The PowerPAD package is designed so that the leadframe
die pad (or thermal pad) is exposed on the bottom of the IC,
as shown in Figure 15. This provides an extremely low
thermal resistance (
JC
) path between the die and the
exterior of the package. The thermal pad on the bottom of
the IC can then be soldered directly to the PCB, using the
PCB as a heatsink. In addition, plated-through holes (vias)
provide a low thermal resistance heat flow path to the back
side of the PCB.
Soldering the PowerPAD to the PCB ia always recom-
mended, even with applications that have low power dissipa-
tion. This provides the necessary thermal and mechanical
connection between the leadframe die pad and the PCB.
OPA569
(A2)
V+
V
IN
V
(a) Inputs connected in parallel.
17,
18
12,
13
5
6
2
9
14,
15
R
L
Parallel Out 2
Parallel Out 1
OPA569
(A1)
V+
V
17,
18
12,
13
5
6
2
9
14,
15
Parallel Out 2
Parallel Out 1
OPA569
(A2)
V+
V
IN
V
(b) Amplifier A1 as "master", A2 as "slave".
17,
18
12,
13
5
6
2
9
14,
15
R
L
Parallel Out 2
Parallel Out 1
OPA569
(A1)
V+
V
17,
18
12,
13
5
6
2
9
14,
15
Parallel Out 2
Parallel Out 1
PowerPAD Assembly Process
1. The PowerPAD must be connected to the most negative
supply voltage of the device, which will be ground in single-
supply applications and V in split-supply applications.
2. Prepare the PCB with a top-side etch pattern, as shown in
Figure 16. There should be etch for the leads as well as
etch for the thermal land.
3. Place the recommended number of plated-through holes
(or thermal vias) in the area of the thermal pad. These
holes should be 13 mils in diameter. They are kept small
so that solder wicking through the holes is not a problem
during reflow. The minimum recommended number of
holes for the SO-20 PowerPAD package is 24, as shown
in Figure 16.
4. It is recommended, but not required, to place a small
number of additional holes under the package and outside
the thermal pad area. These holes provide an additional
heat path between the copper land and the ground plane.
They may be larger because they are not in the area to be
soldered, so wicking is not a problem. This is illustrated in
Figure 16.
OPA569
SBOS264A
19
www.ti.com
5. Connect all holes, including those within the thermal pad
area and outside the pad area, to the internal ground
plane or other internal copper plane for single supply
applications, and V for split-supply applications.
6. When laying out these holes to the ground plane, do not
use the typical web or spoke via connection methodology,
as shown in Figure 17. Web connections have a high
thermal resistance connection that is useful for slowing
the heat transfer during soldering operations. This makes
soldering the vias that have ground plane connections
easier. However, in this application, low thermal resis-
tance is desired for the most efficient heat transfer.
Therefore, the holes under the PowerPAD package should
make their connection to the internal ground plane with a
complete connection around the entire circumference of
the plated-through hole.
FIGURE 16. 20-Pin DWP PowerPAD PCB Etch and Via Pattern.
Web or Spoke Via
Solid Via
NOT RECOMMENDED
RECOMMENDED
FIGURE 17. Via Connection.
Thermal Land
299 mils x 510 mils
Minimum Area (7.59mm x 12.95mm)
(Copper)
OPTIONAL:
Additional 4 vias outside of
thermal pad area but under
the package
(Via diameter = 25 mils)
REQUIRED:
Thermal pad area: 140 mils x 176 mils
(3.56mm x 4.47mm) with 24 vias
(Via diameter = 13 mils)
9. With these preparatory steps in place, the PowerPAD IC
is simply placed in position and run through the solder
reflow operation as any standard surface-mount compo-
nent. This results in a part that is properly installed.
For detailed information on the PowerPAD package including
thermal modeling considerations and repair procedures,
please see Technical Brief SLMA002, "PowerPAD Thermally
Enhanced Package," located at www.ti.com.
LAYOUT GUIDELINES
The OPA569 is a power amplifier that requires proper layout
for best performance. Figure 18 shows an example layout.
Refinements to this example layout may be required based
on assembly process requirements.
Keep power-supply leads as short as possible. This will keep
inductance low and resistive losses at a minimum. A mini-
mum of 18 gauge wire thickness is recommended for power-
supply leads. The wire length should be less than 8 inches.
Proper power-supply bypassing with low ESR capacitors is
essential to achieve good performance. A parallel combina-
tion of 100nF ceramic and 47
F tantalum bypass capacitors
will provide low impedance over a wide frequency range.
Bypass capacitors should be placed as close as practical to
the power-supply pins of the OPA569.
PCB traces conducting high currents, such as from output to
load or from the power-supply connector to the power-supply
pins of the OPA569 should be kept as wide and short as
possible.
The twenty-four holes in the landing pattern for the OPA569
are for the thermal vias that connect the PowerPAD of the
OPA569 to the heatsink area on the PCB. The additional four
larger vias further enhance the heat conduction into the
heatsink area. All traces conducting high currents are very
wide for lowest inductance and minimal resistive losses. Note
that the negative supply (V) pin on the OPA569 can be
connected through the PowerPAD to allow for maximum
trace width for high current paths.
7. The top-side solder mask should leave the terminals of the
pad connections and the thermal pad area exposed. The
thermal pad area should leave the 13 mil holes exposed.
The larger holes outside the thermal pad area should be
covered with solder mask.
8. Apply solder paste to the exposed thermal pad area and
all of the package terminals.
FIGURE 18. 20-Pin DWP PowerPAD PCB Etch and Via
Pattern.
V
Parellel
Out 1
Current
Limit Set
Current Limit Flag
In
+In
Thermal Flag
Enable
I
MONITOR
V
V
OUT
V+
Parallel Out 2
Pin 1
NOTE: Avoid routing Current
Limit Set and Current Limit
Flag traces closely in parallel.
OPA569
SBOS264A
20
www.ti.com
FIGURE 21. Single Power Amplifier Driving Bidirectional Current through a TEC using Asymmetrical Bipolar Power Supplies.
FIGURE 19. Grounded Anode LED Driver.
APPLICATION CIRCUITS
FIGURE 20. Bridge Tied Load Driver.
Luxeon Star-0
High-Power LED
12,
13
5
3
R
SET
6
17,
18
(1)
14,
15
V
O
f
O
= 10kHz
V
IN
OPA569
R
1
49.9k
R
SHUNT
1
I
O
R
2
4.99k
4.99k
0.0033
F
R
3
49.9k
5V
+1V
0V
0mA
100mA
0V
2.5V
Feedback for Constant Current,
1V Input per 100mA Output as Shown.
NOTE: (1) Bypass as recommended.
R
SET
R
M
I
M
=
+
I
TEC
475
V
SET
Optional to
monitor the
load current.
TEC
OPA569
1k
Heat/Cool
V
TEC
V
TEC
= 2 (V
IN
V
SET
)
+
5
12,
13
17,
18
14,
15
Current
Limit
Set
Current
Limit
Set
17,
18
5
6
3
3
12,
13
14,
15
19
I
MONITOR
R
SET
NOTE: (1) Bypass as recommended.
5V
(1)
5V
6
1k
V
IN
OPA569
V
M
(1)
OPA569
5
12,
13
17,
18
19
1.2V
14,
15
NOTE: Total Supply Must
be < 5.5V Cooling/Heating.
NOTE: (1) Bypass as recommended.
R
MONITOR
I
MONITOR
+3.3V
(1)
6
V
IN
TEC
I
L
OPA569
SBOS264A
21
www.ti.com
1M
OPT101
(4)
5
4
3pF
R
1
10k
R
2
10k
OPA569
C
1
3.3nF
+5V
REF3025
LED
Luxeon
Star 0
High
Power
LED
+5V
3
2
1
12,
13
3
17,
18
19
+2.5V
+0.5V
NOTE: (1) Bypass as recommended.
(2) R
SET
establishes current limit.
(3) R
MONITOR
used to measure LED current.
(4) OPT101 Pin Numbers for DIP Package.
R
3
2.5k
C
2
0.01
F
LED
OPT101
Glass Microscope Slide
Approximately
92% light
available for application.
Optical Calibration
8%
V
B
8pF
PD
2
1
5
(1)
6
14,
15
3
8
R
SET
(2)
R
MONITOR
(3)
FIGURE 22. Power Booster for Precision Op Amp.
FIGURE 23. LED Output Regulation Circuit for Constant Optical Power.
R
L
2A max
6
7
4
2
3
1k
V
IN
OPA335
+5V
(1)
14,
15
12,
13
17,
18
5
6
OPA569
+5V
(1)
1k
NOTE: (1) Bypass as recommended.
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
OPA569AIDWP
ACTIVE
SO
Power
PAD
DWP
20
38
None
CU NIPDAU
Level-3-220C-168 HR
OPA569AIDWPR
ACTIVE
SO
Power
PAD
DWP
20
1000
None
CU NIPDAU
Level-1-220C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check
http://www.ti.com/productcontent
for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
Addendum-Page 1
IMPORTANT NOTICE
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