2000 California Micro Devices Corp. All rights reserved. All rights reserved. PAC DN006TM is a tradmark of California Micro Devices Corp.
6/19/2000
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
1
CALIFORNIA MICRO DEVICES
PACDN006
6 Channel ESD Protection Array
Features
Six channels of ESD protection
15KV ESD protection (HBM)
8KV contact, 15KV air ESD protection
per IEC 1000-4-2
Low loading capacitance, 3pF typ.
Miniature 8-pin MSOP or SOIC package
Product Description
The PACDN006 is a diode array designed to provide 6
channels of ESD protection for electronic components
or sub-systems. Each channel consists of a pair of
diodes which steers the ESD current pulse either to
the positive (V
P
) or negative (V
N
) supply. The
PACDN006 will protect against ESD pulses up to 15
KV Human Body Model (100 pF capacitor discharging
through a 1.5K
resistor) and 8KV contact discharge
per International Standard IEC1000-4-2.
Applications
I/O port protection for cellular
phones, notebook computers, PDAs, etc.
ESD protection for VGA (Video) port in
PC's or Notebook computers
ESD protection for sensitive
electronic equipment.
C0970500
SCHEMATIC CONFIGURATION
This device is particularly well-suited for portable
electronics (e.g. cellular phones, PDAs, notebook
computers) because of its small package footprint,
high ESD protection level, and low loading capaci-
tance. It is also suitable for protecting video output
lines and I/O ports in computers and peripheral
equipment.
N
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When placing an order please specify desired shipping: Tubes or Tape & Reel.
2000 California Micro Devices Corp. All rights reserved. All rights reserved. PAC DN006TM is a tradmark of California Micro Devices Corp.
6/19/2000
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
2
CALIFORNIA MICRO DEVICES
PACDN006
Note 2: From I/O pins to V
P
or V
N
only. V
P
bypassed to V
N
with 0.2 mF ceramic capacitor.
Note 3: Human Body Model per MIL-STD-883, Method 3015, C
Discharge
=100pF, R
Discharge
=1.5K
, V
P
=5.0V, V
N
=GND.
Note 4: This parameter is guaranteed by design and characterization.
Note 5: Standard IEC1000-4-2 with C
Discharge
=150pF, and R
Discharge
=330
, V
P
=5V, V
N
=GND.
Input Capacitance vs. Input Voltage
0
1
2
3
4
5
0
1
2
3
4
5
Input Voltage
Input Capacitance (pF
)
Typical variation of C
IN
with V
IN
(V
P
= 5V, V
N
= 0V, 0.1
F chip capacitor between V
P
& V
N
)
S
G
N
I
T
A
R
M
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)
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t
o
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(
A
m
0
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r
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t
a
r
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p
m
e
T
e
g
a
r
o
t
S
C
0
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1
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C
5
6
e
g
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u
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C
5
8
o
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0
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C
y
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V
o
t
V
5
.
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5
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+
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N
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5
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5
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5
9
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P
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r
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s
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V
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5
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8
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)
4
,
3
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5
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5
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V
P
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0
.
3
1
+
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N
V
0
.
3
1
C
5
2
=
T
,
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e
r
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=
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=
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p
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2
2000 California Micro Devices Corp. All rights reserved. All rights reserved. PAC DN006TM is a tradmark of California Micro Devices Corp.
6/19/2000
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
3
CALIFORNIA MICRO DEVICES
PACDN006
Application Information
See also California Micro Devices Application note
AP209, "Design Considerations for ESD protection."
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances to the Supply
and Ground rails. Refer to Figure 1, which illustrates
the case of a positive ESD pulse applied between an
input channel and Chassis Ground. The parasitic
series inductance back to the power supply is repre-
sented by L
1
. The voltage V
Z
on the line being pro-
tected is:
V
Z
= Forward voltage drop of D
1
+ L
1
x d(I
ESD
)/
dt + V
SUPPLY
where I
ESD
is the ESD current pulse, and
V
SUPPLY
is the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC 61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1nS. Here d(I
ESD
)/dt can be approximated by
DI
ESD
/Dt, or 30/(1x10
-9
). So just 10nH of series induc-
tance (L
1
) will lead to a 300V increment in V
Z
!
Similarly for negative ESD pulses, parasitic series
inductance from the V
N
pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
Another consideration is the output impedance of the
power supply for fast transient currents. Most power
supplies exhibit a much higher output impedance to
fast transient current spikes. In the V
Z
equation above,
the V
SUPPLY
term, in reality, is given by (V
DC
+ I
ESD
x
R
OUT
), where V
DC
and R
OUT
are the nominal supply DC
output voltage and effective output impedance of the
power supply respectively. As an example, a R
OUT
of 1
ohm would result in a 10V increment in V
Z
for a peak
I
ESD
of 10A.
To mitigate these effects, a high frequency bypass
capacitor should be connected between the V
P
pin of
the ESD Protection Array and the ground plane. The
value of this bypass capacitor should be chosen such
that it will absorb the charge transferred by the ESD
pulse with minimal change in V
P
. Typically a value in
the 0.1F to 0.2F range is adequate for
IEC-61000-4-2 level 4 contact discharge protection
(8KV). For higher ESD voltages, the bypass capacitor
should be increased accordingly. Ceramic chip capaci-
tors mounted with short printed circuit board traces are
good choices for this application. Electrolytic capaci-
tors should be avoided as they have poor high fre-
quency characteristics. For extra protection, connect a
zener diode in parallel with the bypass capacitor to
mitigate the effects of the parasitic series inductance
inherent in the capacitor. The breakdown voltage of the
zener diode should be slightly higher than the maxi-
mum supply voltage.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the V
P
pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply and
ground planes to minimize stray series inductance.
Figure 1.
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