2004 California Micro Devices Corp. All rights reserved.
09/21/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
1
PACDN009
5 Channel ESD Protection Array
Features
Five channels of ESD protection
8 kV contact, 15 kV air ESD protection per
channel (IEC 61000-4-2 standard)
15 kV of ESD protection per channel (HBM)
Low loading capacitance (3pF typical)
Low leakage current is ideal for battery-powered
devices
Available in miniature 8-lead MSOP package
Lead-free version available
Applications
Consumer electronic products
Cellular phones
PDAs
Notebook computers
Desktop PCs
Digital cameras and camcorders
VGA (video) port protection for desktop
and portable PCs
Product Description
The PACDN009 is a diode array designed to provide 5
channels of ESD protection for electronic components
or sub-systems. Each channel consists of a pair of
diodes which steers an ESD current pulse to either the
positive (V
P
) or negative (V
N
) supply. The PACDN009
protects against ESD pulses up to
15kV Human Body
Model (100 pF capacitor discharging through a 1.5K
resistor), and
8kV contact discharge, per International
Standard IEC 61000-4-2.
This device is particularly well-suited for portable elec-
tronics (e.g., cellular phones, PDAs, notebook comput-
ers) because of its small package footprint, high ESD
protection level, and low loading capacitance. It is also
suitable for protecting video output lines and I/O ports
in computers and peripherals and is ideal for a wide
range of consumer electronics products.
The PACDN009 is supplied in an 8-lead MSOP pack-
age and is available with optional lead-free finishing.
Electrical Schematic
Typical Application Circuit
PACDN009
I/O Port
Buffers
Connector
Expansion
Handheld/PDA ESD Protection
1 4 5 6 8
7
3
0.22
F*
* Capacitor should be placed
as close as possible to Pin7
1
2
3
4
8
7
6
5
VP
VN
N.C.
2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
09/21/04
PACDN009
Ordering Information
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
PIN DESCRIPTIONS
PIN
NAME
TYPE
DESCRIPTION
1
CH 1
I/O
ESD Channel
2
N.C. -
No
connect
3
V
N
GND
Negative voltage supply rail or ground reference rail
4
CH 2
I/O
ESD Channel
5
CH 3
I/O
ESD Channel
6
CH 4
I/O
ESD Channel
7
V
P
Supply
Positive voltage supply rail
8
CH 5
I/O
ESD Channel
PACKAGE / PINOUT DIAGRAMS
PACDN009
1
2
3
4
8
7
6
5
CH 1
N.C.
V
N
CH 2
CH 5
V
P
CH 4
CH 3
TOP VIEW
Note: This drawing is not to scale.
8-lead MSOP Package
PART NUMBERING INFORMATION
Leads
Package
Standard Finish
Lead-free Finish
Ordering Part
Number
1
Part Marking
Ordering Part
Number
1
Part Marking
8
MSOP
PACDN009M
D009
PACDN009MR
009R
2004 California Micro Devices Corp. All rights reserved.
09/21/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
3
PACDN009
Specifications
Note 1: Only one diode conducting at a time.
Note 1: All parameters specified at T
A
=25C unless otherwise noted. V
P
= 5V, V
N
= 0V unless noted.
Note 2: These parameters guaranteed by design and characterization.
Note 3: From I/O pins to V
P
or V
N
only. V
P
bypassed to V
N
with a 0.22
F ceramic capacitor (see Application Information for more
details).
Note 4: Human Body Model per MIL-STD-883, Method 3015, C
Discharge
= 100pF, R
Discharge
= 1.5K
, V
P
= 5.0V, V
N
grounded.
Note 5: Standard IEC 61000-4-2 with C
Discharge
= 150pF, R
Discharge
= 330
, V
P
= 5.0V, V
N
grounded.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNITS
Supply Voltage (V
P
- V
N
)
6.0
V
Diode Forward DC Current (Note 1)
20
mA
Operating Temperature Range
-40 to +85
C
Storage Temperature Range
-65 to +150
C
DC Voltage at any channel input
(V
N
- 0.5) to (V
P
+ 0.5)
V
Package Power Rating
MSOP Package
200
mW
STANDARD OPERATING CONDITIONS
PARAMETER
RATING
UNITS
Operating Temperature Range
-40 to +85
C
Operating Supply Voltage (V
P
- V
N
)
0 to 5.5
V
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
P
Supply Current
(V
P
-V
N
)=5.5V
10
A
V
F
Diode Forward Voltage
I
F
= 20mA
0.65
0.95
V
V
ESD
ESD Protection
Peak Discharge Voltage at any channel
input, in system
a) Human Body Model, MIL-STD-883,
Method 3015
b) Contact Discharge per IEC 61000-4-2
c) Air Discharge per IEC 61000-4-2
Note 3
Notes 2,4
Note 5
Note 5
15
8
15
kV
kV
kV
V
CL
Channel Clamp Voltage
Positive Transients
Negative Transients
@15kV ESD HBM
V
P
+ 13.0
V
N
- 13.0
V
V
I
LEAK
Channel Leakage Current
0
.1
1.0
A
C
IN
Channel Input Capacitance
@ 1 MHz, V
P
=5V, V
N
=0V,
V
IN
=2.5V; Note 2 applies
3
5
pF
2004 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
09/21/04
PACDN009
Performance Information
Input Capacitance vs. Input Voltage
0
1
2
3
4
5
0
1
2
3
4
5
VIN
C
IN
(pF)
Typical Variation of C
IN
vs. V
IN
(V
P
= 5V, V
N
= 0V, 0.1
F chip capacitor between V
P
and V
N
)
2004 California Micro Devices Corp. All rights reserved.
09/21/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
5
PACDN009
Application Information
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to
Figure 1
, which illus-
trates an example of a positive ESD pulse striking an
input channel. The parasitic series inductances back to
the power supply are represented by L
1
and
L
2
. The
voltage V
CL
on the line being protected is:
V
CL
= Fwd voltage drop of D
1
+ V
SUPPLY
+ L
1
x d(I
ESD
)
/
dt
+ L
2
x d(I
ESD
)
/
dt
where I
ESD
is the ESD current pulse, and V
SUPPLY
is
the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(I
ESD
)/dt can be approximated by
I
ESD
/
t, or 30/(1x10
-9
). So just 10nH of series induc-
tance (L
1
and
L
2
combined) will lead to a 300V incre-
ment in V
CL
!
Similarly for negative ESD pulses, parasitic series
inductance from the V
N
pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
Another consideration is the output impedance of the
power supply for fast transient currents. Most power
supplies exhibit a much higher output impedance to
fast transient current spikes. In the V
CL
equation
above, the V
SUPPLY
term, in reality, is given by (V
DC
+
I
ESD
x R
OUT
), where V
DC
and R
OUT
are the nominal
supply DC output voltage and effective output imped-
ance of the power supply respectively. For example,
with R
OUT
equal to 1 ohm, we would see a 10V incre-
ment in V
CL
for a peak I
ESD
of 10A.
If the inductances and resistance described above are
close to zero, the rail-clamp ESD protection diodes will
do a good job of protection. However, since this is not
possible in practical situations, a bypass capacitor
must be used to absorb the very high frequency ESD
energy. So for any brand of rail-clamp ESD protection
diodes, a bypass capacitor should be connected
between the V
P
pin of the diodes and the ground plane
(V
N
pin of the diodes) as shown in the Application Cir-
cuit diagram below. A value of 0.22F is adequate for
IEC-61000-4-2 level 4 contact discharge protection
(
8kV). Ceramic chip capacitors mounted with short
printed circuit board traces are good choices for this
application. Electrolytic capacitors should be avoided
as they have poor high frequency characteristics. For
extra protection, connect a zener diode in parallel with
the bypass capacitor to mitigate the effects of the para-
sitic series inductance inherent in the capacitor. The
breakdown voltage of the zener diode should be
slightly higher than the maximum supply voltage.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the V
P
pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also California Micro Devices Application Notes
AP209, "Design Considerations for ESD Protection"
and AP219, "ESD Protection for USB 2.0 Systems""
Figure 1. Application of Positive ESD Pulse between Input Channel and Ground
N
L
2
L
1
V
P
V
PATH OF ESD CURRENT PULSE I
ONE
CHANNEL
OF
PAC DN009
CHANNEL
INPUT
GROUND RAIL
CHASSIS GROUND
POSITIVE SUPPLY RAIL
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
LINE BEING
PROTECTED
ESD
D
1
2
D
0A
20A
V
CL
2004 California Micro Devices Corp. All rights reserved.
6
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
09/21/04
PACDN009
Application Information (cont'd)
Implementation Examples
ESD events are very high-speed pulses with rise times
in the range of 1ns or less. To effectively use the
PACDN009, the following design guidelines must be
observed (as discussed in the application section):
1) The inductance from the V
N
and V
P
connections of
the PACDN009 to ground must be very low. This
includes the path through the V
P
decoupling capacitor
to ground and the path to the power supply (as dis-
cussed above).
2) The inductance between the connector pin to be
protected and the PACDN009 channel input pin must
be kept to a minimum. If there is a large inductance
here, the ESD event will find a lower impedance path
which will more likely be through the device to be pro-
tected.
Figure 2
shows the implementation schematic
and
Figure 3
shows a possible layout for the
PACDN009. In figure 3, notice the large VCC and
ground areas with multiple via connections to the
underlying reference planes and the positioning of the
bypass capacitor. Note how the signal lines to be pro-
tected flow from the connector to the PACDN009 and
then out to the device to be protected (
Figure 3
). This
daisy chaining provides a low impedance path from the
connector to the PACDN009 and a higher impedance
path from the PACDN009 to the protected device.
Figure 2. Typical ESD protection implementation
ONE
CHANNEL
OF
PAC DN009
GROUND RAIL
POSITIVE SUPPLY RAIL
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
D
1
2
D
POWER SUPPLY
OPTIONAL
ZENER DIODE
FOR EXTRA
PROTECTION
CHANNEL
INPUT
DECOUPLING
CAPCITOR
0.22
F
LINE BEING
PROTECTED
2004 California Micro Devices Corp. All rights reserved.
09/21/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
7
PACDN009
Application Information (cont'd)
Figure 3. PCB Layout Recomendation
2004 California Micro Devices Corp. All rights reserved.
8
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
09/21/04
PACDN009
Mechanical Details
MSOP Mechanical Specifications
The PACDN009 is supplied in an 8-lead MSOP pack-
age. Dimensions are presented below.
For complete information on the MSOP-8 package,
see the specific California Micro Devices Package
Information document.
* This is an approximate number which may vary.
Package Dimensions for MSOP-8
PACKAGE DIMENSIONS
Package
MSOP
Leads
8
Dimensions
Millimeters
Inches
Min
Max
Min
Max
A
0.87
1.17
0.034
0.046
A1
0.05
0.25
0.002
0.010
B
0.30 (typ)
0.012 (typ)
C
0.18
0.007
D
2.90
3.10
0.114
0.122
E
2.90
3.10
0.114
0.122
e
0.65 BSC
0.025 BSC
H
4.78
4.98
0.188
0.196
L
0.52
0.54
0.017
0.025
# per tube
80 pieces*
# per tape
and reel
4000 pieces
Controlling dimension: inches
Mechanical Package Diagrams
E
D
H
1
2
3
4
8
7
6
5
L
END VIEW
C
e
B
A
A1
SEATING
PLANE
SIDE VIEW
TOP VIEW
Pin 1
Marking
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