cmi

Capella Microsystems Inc.

3777 Stevens Creek Blvd., Suite 320 Santa Clara, CA 95051-7364 U.S.A Tel: (408) 260-3400 FAX: (408) 248-3416

CMI9647 DVD/CD-ROM
RF PREAMPLIFIER &
FILTER/EQUALIZER

PRELIMINARY DATA SHEET

Revision 2.0

12/1/99

This preliminary data sheet indicates that this product is still in the design cycle. All specifications are based on
design goals only. Capella Microsystems Inc. assumes no responsibility for the use of this product.

Capella Microsystems Inc. reserves the right to make changes in specifications or discontinue this product at any
time without notice. Please contact Capella Microsystems Inc. for possible updates before starting a design.

Capella Microsystems Inc. products are not designed for use in life support applications. Any parties who use these
products in such applications do so at their own risk and agree to fully indemnify Capella Microsystems Inc. for
any damages resulting from such improper usage or sale.

cmi

3777 Stevens Creek Blvd., Suite 320 Santa Clara, CA 95051-7364 U.S.A Tel: (408) 260-3408 FAX: (408) 248-3416

KEY FEATURES

Single chip RF preamplifier & filter/equalizer
IC for DVD and CD applications

Able to interface to multiple optical pickups,
including Sankyo (SPU-3130), Sanyo (SF-
HD2R) and Hitachi (HOP-2100A)

High bandwidth (30MHz), low noise RF
summing amplifier that supports up to 4X DVD
and up to 36X CD-ROM

High bandwidth variable gain amplifier (VGA)
with 14dB gain control range

Built-in six pole, two zero (6P2Z) continuous
time equiripple filter/equalizer with user
programmable cutoff frequency (1MHz to
30MHz) and high frequency boost (0dB to
15dB)

Focus error detection using astigmatism method

One beam differential/push-pull amplitude
tracking error detection for CD and DVD
applications

One beam differential phase tracking error
detection for DVD applications

Three beam tracking error detection for CD
applications

Built-in alignment error detection circuitry

Built-in "normalization" circuitry for all the
servo error detection related blocks

RF envelope/ripple detection circuitry with RF
ripple output (RFRP)

Digital Wobble signal for DVD-RAM
applications

Drop out detection circuit for scratch detection

Dual automatic laser power control (ALPC)
circuitry for twin lens pick-up applications

Support of two polarity structures for laser
diodes

Sub-beam added signal output for three beam
CD applications

Two types of voltage reference outputs
(VR2=2.1V and VR3=4.2V)

Three wire serial interface port (SIP) circuit
with bi-directional SDATA port for controlling

gain imbalance, filter cutoff frequency, filter
boost and output offset compensation controls

Single 5V

5% power supply

48 pin LQFP

Total power dissipation is 600mW

Advanced 0.6

m DPDM mixed mode CMOS

process

FUNCTIONAL BLOCKS

High bandwidth RF summing amplifier
(A+B+C+D) Channels

Variable gain amplifier (VGA) amplifier

Continuous time equiripple filter/equalizer

Focus error detector (A+C)-(B+D)

One beam differential amplitude/ push-pull
tracking error detector (A+B)-(C+D)

One beam differential phase tracking error
detector

(

)

(

)

Three beam amplitude tracking error detector
(E-F)

Alignment error detector (A+D)-(B+C)

RF envelope/ripple detector

RF center detector

Data drop out detector

Digital Wobble circuitry

Dual automatic laser power control circuit
(ALPC)

Three wire serial interface port circuitry with bi-
directional SDATA port

Two bandgap referenced bias voltage outputs
(VR2 and VR3)

Sub-beam added signal detection circuit (E+F)

APPLICATIONS

DVD Player

DVD-ROM (up to 4X)

DVD Write Once or DVD-R

DVD re-writable or DVD-RAM

CD-ROM (up to 36X)

CD-R

CD-RW

cmi

3777 Stevens Creek Blvd., Suite 320 Santa Clara, CA 95051-7364 U.S.A Tel: (408) 260-3408 FAX: (408) 248-3416

VDD3

WBL

RFRP

FILACP

RFSUMN

FILACN

VDD2

RFO

GND2

RFSUMP

TEOHOLD

DOUT

36 GND3

OBTEOLPF

TEXO

TEO

FEO

AEO/SBAD

RFGAIN

EFGAIN

VDD4

GND4

VR3

LDC

CDLDO

CDMDI

DVDLDO

DVDMDI

VDD1

SDATA

GND1

CSB

SCLK

PDB

CVR

VR2

VF1

VE1

VD1

VC1

VB1

VA1

VD2

VC2

VB2

VA2

Prog.

Filter/

Equalizer

ALPC

Voltage

Reference

Amp.

3-Beam

Amp.

1-Beam

3-Beam

Tracking

(F-E)

Gain

Control

1-Beam

Tracking

(A+B)-(C+D)

Focus

Error

(A+C)-(B+D)

Alignment

Error

(A+D)-(B+C)

Sub-Beam

Added

(E+F)

MUX

Wobble

Dropout

Serial Interface

Port

VGA

SUM

Diff.

Phase Det.

(A+C)-(B+D)

MUX

TEO

LPF

TEXO

LPF

AMP

MUX

Peak -

Bottom

OBTEO

LPF

RFI

Figure 1: CMI9647 Block Diagram

DVD/CD

TRACK

Tangential

Direction

Radial

Direction

Figure 2:

Photodiode Configuration Assumed for Equations in Figure 1

cmi

3777 Stevens Creek Blvd., Suite 320 Santa Clara, CA 95051-7364 U.S.A Tel: (408) 260-3408 FAX: (408) 248-3416

GENERAL DESCRIPTION

The CMI9647 Digital Versatile Disc (DVD)

and/or CD RF preamplifier & filter/equalizer IC is a
highly integrated analog front-end signal processing
IC dedicated to the newly developed DVD player,
DVD-ROM, DVD-R and DVD-RAM applications
(up to 4X). This chip can also be used for existing
CD applications, and has the additional flexibility of
being able to interface with Sanyo, Sankyo and
Hitachi optical pickups units (See Tables 13 and 14,
page 22).

The CMI9647 consists of all the necessary

building blocks for an RF preamplifier &
filter/equalizer (See Figure 1, page 3). It includes an
RF summing amplifier, a VGA amplifier, a
continuous time filter/equalizer, a focus error
detection circuit, and an alignment error detection
circuit. The CMI9647 provides three types of
tracking error detector outputs. These include a one
beam differential amplitude/push-pull tracking error
detector output, a one beam differential phase
tracking error detector output, and a three beam
amplitude tracking error detector output. The
CMI9647 also provides an RF envelope/ripple
detector output and a data dropout detector output for
servo DSP ICs. The CMI9647 has a dual Automatic
Laser Power Control (ALPC) block which supports
either dual or single lens CD/DVD applications. In
addition, there are two reference voltage outputs
(VR2 and VR3), a sub-beam added signal (SBAD)
output, and a three wire serial interface port (SIP)
circuit. The SIP circuit controls the cutoff frequency
of the continuous time filter/equalizer, the high
frequency boost of the continuous time
filter/equalizer, the systematic gain imbalance and
the output offset of the servo related signals, as well
as other analog control functions.

RF CHANNEL & FILTER/EQUALIZER

The RF channel of the CMI9647 takes the

A, B, C, and D I/V amplifier voltage outputs from an
external OPIC and sums them together. The
resultant signal is then low pass filtered (1MHz -
30MHz) to form the RFO signal. The recommended
input voltage level from the external OPIC to the
CMI9647 should be in the range of 0.06V to 0.50V
peak to peak. The gain of the RF summing signal is
adjusted by the variable gain amplifier (VGA)

circuit. The overall VGA input control voltage range
applied to the RFGAIN pin should be in the 0.5V to
3V range, and the overall gain control range for the
RFO output is 14dB. The RF channel input range is
controlled by register 14 bit 3 (See Table 2, page 10).
Setting the RFRNG bit to `1' reduces the overall
gain by 6dB. The input range is as shown in the RF
channel and servo amplifier specifications (See
Table 20, page 27). The outputs of the VGA
amplifier are routed to the built-in continuous time
filter/equalizer. This is a sixth order equiripple
filter/equalizer with a programmable cutoff
frequency from 1MHz to 30MHz. The cutoff
frequency is controlled by 7 bits in the SIP Register.
Coarse tuning can be performed by bit 6 of register 8
(G6), while fine tuning is possible via G[5:0], bit 5
down to 0 of register 8 (See Table 1, page 9). The
filter/equalizer also has a high frequency boost (0dB
to 15dB), controlled by two independent 4 bits
nibbles (SA[3:0], SB[3:0]) from register 9 of the SIP
register (See Table 1, page 9). The typical RF
channel output voltage swing is 1.0V. The output is
typically routed to an external IC for further signal
processing (i.e. auto slicer and data synchronizer
(clock recovery phase locked loop) processing),
before the re-synchronized data and reference clock
(recovered by the data synchronizer PLL) are sent for
further EFM+ decoding, and ECC correction. Table
5.1 (page 15) and Table 5.2 (page 16) show the
relationships between the 3dB cutoff frequency and
the value of the serial port interface register, while
Table 7 (page 17) shows the relationship between the
magnitude of the high frequency boost and the value
of the SIP register.

FOCUS ERROR DETECTION

The CMI9647 provides focus error

detection for cylindrical lens systems using the
astigmatism method. The equation is (A+C)-(B+D).
For a well focused signal, the (A+C) signal is equal
to the (B+D) signal, and thus the focus error output
(FEO) is equal to the pseudo ground voltage (i.e.
VR2=2.1V). If there are pre-existing gain
imbalances in the (A+C) channel with respect to the
(B+D) channel due to either different photo detector
sensitivities or different physical layout designs of
the photo detectors, these pre-existing gain
imbalances or gain offsets can be compensated by

cmi

3777 Stevens Creek Blvd., Suite 320 Santa Clara, CA 95051-7364 U.S.A Tel: (408) 260-3408 FAX: (408) 248-3416

programming the FEBAL register using the SIP
interface (See Table 1, (page 9) Register 2, bits D4
D0). The overall gain balance control range of the
FEO output is

22.5% of the applied gain setting

(See Table 3.1, page 10). In addition, the CMI9647
provides an FEO register to adjust the FEO output
offset voltage (See Table 1 (page 9), Register 2, bits
D7 D5 ). The adjustable offset range of the FEO
output is

±60

0mV with 3 bits of resolution. (See

Table 4, page 14). Register 2 bits D4 D0 as shown
in table 3.4 and 3.5 on pages 12 and 13, control the
FEO output signal amplitude.

The focus error input range is controlled by

TRACKING ERROR DETECTION

To insure backward compatibility, the

CMI9647 provides three types of tracking error
detection, which can be selected by programming the
TEM2 and TEM1 control bits of register 4 (See
Table 8, page 18). The tracking error detection
methods are i.) One beam differential phase
detection (DPDTEO) to support DVD applications;
ii.) Three beam amplitude detection (TBTEO)
method (i.e. (VE1-VF1)) to support backward
compatibility for CD applications; iii.) One beam
differential amplitude/push-pull (OBTEO) detection
method (i.e. (VA+VB)-(VC+VD)) to support both
CD and DVD applications. Like the focus error
circuit, the adjustable output offset range of the one
beam differential amplitude/push-pull detection and
the three beam amplitude detection outputs is

±600

mV with 3 bit resolution (See Table 4, page

14). There is built-in gain control circuitry and gain
imbalance control circuitry in the tracking error
detector blocks. Any pre-existing gain imbalance
between the channels, and the output offset can be
compensated by means of the SIP, via the Tracking
Error Balance (TEBAL) register (See Table 1 (page
9), Register 0,bits D4 D0).

The one-beam and phase detection tracking

error input range is controlled by register 14 bit 2.
Setting the ADRNG bit to "1" reduces the OBTEO
gain by 7dB. The three-beam tracking error input
range is controlled by register 14 bit 1. Setting the
EFRNG bit to "1" reduces the overall gain by 5dB.

The DPD balance is adjusted by delaying

either the (A+C) or (B+D) signals. If DEL[5],
register 13 bit 5, is set to logic 0 then the (A+C)
signal is delayed. If DEL[5], register 13 bit 5, is set
to logic 1 then the (B+D) signal is delayed. The
delay is adjusted in increments of 2.0ns, 1.0ns,
0.7ns, and 0.5ns depending upon the setting of
DPD[1:0], register 13 bits 7 and 6 (See Table 3.2,
page 11). The maximum delay is 31 units (e.g.
31*2.0ns = 62ns for DPD[1:0]=00).

For the DPD tracking error output, the

(A+C) and (B+D) signals are equalized using a
bandpass type filter. The lower 3dB frequency is
controlled by the DPDEQ[1:0] bits, R12[3:2] (See
Table 9, page 18). For 1X DVD set
DPDEQ[1:0]=LL and for 4X DVD set
DPDEQ[1:0]=HH. The upper 3dB frequency is fixed.

The DPDTEO gain is controlled by register

15 bits 5 and 4 as shown in table 3.3 on page 11.

The TEXO and TEO outputs will hold there

voltage when the TEOHOLD pin (pin 40) is set to
logic "1". This can be used to hold the TEO and
TEXO outputs after a drop out condition has been
flagged.

The OBTEO output is also brought out to

pin 33, OBTEOLPF. It is disabled during CD
operation. The OBTEO gain is controlled by register
4 bits D4 D0 (see tables 3.4 and 3.5 on pages 12
and 13). The OBTEOLPF bandwidth is
programmable to 20Khz or 200Khz as shown in
table 9 on page 18.

ALIGNMENT ERROR DETECTION

The CMI9647 has built-in alignment error

detection circuitry. Theoretically, the alignment
error detector block is similar to the focus error
detector block. The main difference is in the
mathematical equation. The alignment error
equation is (VA+VD)-(VB+VC). Like the focus
error detection block, there is a gain imbalance
control as well as gain control in the alignment error
detector block. If there are pre-existing gain
imbalances between the (VA+VD) channels and the
(VB+VC) channels and output offset problems, these
pre-existing gain imbalances and output offsets can
be compensated for, by programming the AEBAL
and AEO registers (See Table 1, Register 1, on page
9) using the SIP interface. The overall gain balance

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