CAT25C32/64

32K/64K-Bit SPI Serial CMOS E

PROM

FEATURES

10 MHz SPI Compatible

1.8 to 6.0 Volt Operation

Hardware and Software Protection

Zero Standby Current

Low Power CMOS Technology

SPI Modes (0,0 &1,1)

Commercial, Industrial and Automotive
Temperature Ranges

1,000,000 Program/Erase Cycles

100 Year Data Retention

Self-Timed Write Cycle

8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOPand
20-Pin TSSOP

64-Byte Page Write Buffer

Block Write Protection
Protect 1/4, 1/2 or all of E

PROM Array

PIN CONFIGURATION

PIN FUNCTIONS

Pin Name

Function

Serial Data Output

SCK

Serial Clock

Write Protect

+1.8V to +6.0V Power Supply

Ground

Chip Select

Serial Data Input

HOLD

Suspends Serial Input

No Connect

BLOCK DIAGRAM

Advanced Information

DESCRIPTION

The CAT25C32/64 is a 32K/64K-Bit SPI Serial CMOS
E

PROM internally organized as 4Kx8/8Kx8 bits.

Catalyst's advanced CMOS Technology substantially
reduces device power requirements. The CAT25C32/
64 features a 64-byte page write buffer. The device
operates via the SPI bus serial interface and is enabled
though a Chip Select (

). In addition to the Chip Select,

the clock input (SCK), data in (SI) and data out (SO) are

required to access the device. The

HOLD

pin may be

used to suspend any serial communication without
resetting the serial sequence. The CAT25C32/64 is
designed with software and hardware write protection
features including Block write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and
20-pin TSSOP packages.

Doc No. 25087-00 8/99 SPI-1

DIP Package (P)

TSSOP Package (U20)

SOIC Package (S)

SENSE AMPS

SHIFT REGISTERS

SPI

CONTROL

LOGIC

WORD ADDRESS

BUFFERS

I/O

CONTROL

PROM

ARRAY

COLUMN

DECODERS

XDEC

HIGH VOLTAGE/

TIMING CONTROL

STATUS

BLOCK

PROTECT

LOGIC

CONTR

OL LOGIC

DATA IN

STORAGE

HOLD

SCK

VCC
HOLD

SCK

VSS

VCC
HOLD

SCK

HOLD

VCC

NC
NC

SCK
SI

2
3
4
5
6
7
8
9

TSSOP Package (U14)

HOLD

VCC

SCK
SI

2
3
4
5
6
7

CAT25C32/64

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Advanced Information

D.C. OPERATING CHARACTERISTICS

= +1.8V to +6.0V, unless otherwise specified.

Limits

Symbol

Parameter

Min.

Typ.

Max.

Units

Test Conditions

CC1

Power Supply Current

= 5V @ 10MHz

(Operating Write)

SO=open; CS=Vss

CC2

Power Supply Current

= 5.0V

(Operating Read)

CLK

= 10MHz

Power Supply Current

= V

(Standby)

= V

or V

Input Leakage Current

Output Leakage Current

OUT

= 0V to V

CS = 0V

(3)

Input Low Voltage

-1

x 0.3

(3)

Input High Voltage

x 0.7

+ 0.5

OL1

Output Low Voltage

0.4

OH1

Output High Voltage

- 0.8

OL2

Output Low Voltage

0.2

1.8V

<2.7V

OH2

Output High Voltage

-0.2

= 150

= -100

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. 55

C to +125

Storage Temperature ....................... 65

C to +150

Voltage on any Pin with

Respect to V

................... 2.0V to +V

+2.0V

with Respect to V

SS ................................

2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25

C) ................................... 1.0W

Lead Soldering Temperature (10 secs) ............ 300

Output Short Circuit Current

(2)

........................ 100 mA

*COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Min.

Max.

Units

Reference Test Method

END

(3)

Endurance

1,000,000

Cycles/Byte

MIL-STD-883, Test Method 1033

(3)

Data Retention

100

Years

MIL-STD-883, Test Method 1008

ZAP

(3)

ESD Susceptibility

2000

Volts

MIL-STD-883, Test Method 3015

LTH

(3)(4)

Latch-Up

100

JEDEC Standard 17

Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V

+0.5V, which may overshoot to V

+2.0V for periods of less than 20 ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V

+1V.

4.5V

<5.5V

= 3.0mA

= -1.6mA

CAT25C32/64

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Advanced Information

Limits

Vcc=

1.8V-6.0V

2.5V-6.0V

4.5V-5.5V

Test

SYMBOL PARAMETER

Min.

Max.

Min.

Max.

Min.

Max.

UNITS

Conditions

Data Setup Time

Data Hold Time

SCK High Time

250

125

SCK Low Time

250

125

SCK

Clock Frequency

MHz

HOLD

to Output Low Z

(1)

Input Rise Time

(1)

Input Fall Time

HOLD

Setup Time

100

HOLD

Hold Time

100

Write Cycle Time

Output Valid from Clock Low

250

Output Hold Time

DIS

Output Disable Time

250

HOLD

to Output High Z

150

100

High Time

500

250

200

CSS

Setup Time

500

250

100

CSH

Hold Time

500

250

100

NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.

A.C. CHARACTERISTICS

Figure 1. Sychronous Data Timing

= 50pF

Note: Dashed Line= mode (1, 1) -- -- -- --

VALID IN

CSS

VIL

HI-Z

CSH

DIS

HI-Z

SCK

tFI

CAT25C32/64

Doc. No. 25087-00 8/99 SPI-1

Advanced Information

FUNCTIONAL DESCRIPTION

The CAT25C32/64 supports the SPI bus data transmis-
sion protocol. The synchronous Serial Peripheral Inter-
face (SPI) helps the CAT25C32/64 to interface directly
with many of today's popular microcontrollers. The
CAT25C32/64 contains an 8-bit instruction register.
(The instruction set and the operation codes are de-
tailed in the instruction set table)

After the device is selected with

going low, the first

byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.

PIN DESCRIPTION

SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C32/64. Input data is latched on the rising edge of the
serial clock.

SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C32/64. During a read cycle,
data is shifted out on the falling edge of the serial clock.

SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
and the 25C32/64. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK.

: Chip Select

is the Chip select pin.

low enables the CAT25C32/

64 and

high disables the CAT25C32/64.

high

takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
write operation is underway). The CAT25C32/64 draws
ZERO current in the Standby mode. A high to low
transition on

is required prior to any sequence being

initiated. A low to high transition on

after a valid write

sequence is what initiates an internal write cycle.

: Write Protect

is the Write Protect pin. The Write Protect pin will

allow normal read/write operations when held high.
When

is tied low and the WPEN bit in the status

going low while

is still low

will interrupt a write to the status register. If the internal
write cycle has already been initiated,

going low will

have no effect on any write operation to the status
register. The

pin function is blocked when the WPEN

bit is set to 0.

HOLD

: Hold

The

HOLD

pin is used to pause transmission to the

CAT25C32/64 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause,

HOLD

must be brought low while SCK

is low. The SO pin is in a high impedance state during the
time the part is paused, and transitions on the SI pins will
be ignored. To resume communication,

HOLD

is brought

high, while SCK is low.

(HOLD

should be held high any

time this function is not being used.)

HOLD

may be tied

high directly to V

or tied to V

through a resistor.

Figure 9 illustrates hold timing sequence.

Instruction

Opcode

Operation

WREN

0000 0110

Enable Write Operations

WRDI

0000 0100

Disable Write Operations

RDSR

0000 0101

Read Status Register

WRSR

0000 0001

Write Status Register

READ

0000 0011

Read Data from Memory

WRITE

0000 0010

Write Data to Memory

INSTRUCTION SET

CAT25C32/64

Doc No. 25087 -00 8/99 SPI-1

Advanced Information

Status Register Bits

Array Address

Protection

BP1

BP0

Protected

None

No Protection

25C32: 0C00-0FFF

Quarter Array Protection

25C64:1800-1FFF

25C32: 800-0FFF

Half Array Protection

25C64:1000-1FFF

25C32: 0000-0FFF

Full Array Protection

25C64:0000-1FFF

BLOCK PROTECTION BITS

Protected

Unprotected

Status

WPEN

WEL

Blocks

Register

Protected

Writable

Low

Protected

Low

Protected

Writable

Protected

High

Protected

High

Protected

Writable

WRITE PROTECT ENABLE OPERATION

WPEN

BP1

BP0

WEL

RDY

STATUS REGISTER

The Status Register indicates the status of the device.

The

RDY

(Ready) bit indicates whether the CAT25C32/

64 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only.

The WEL (Write Enable) bit indicates the status of the
write enable latch . When set to 1, the device is in a Write
Enable state and when set to 0 the device is in a Write
Disable state. The WEL bit can only be set by the WREN
instruction and can be reset by the WRDI instruction.

The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the

array. These bits are non-volatile.

The WPEN (Write Protect Enable) is an enable bit for the

pin. The

pin and WPEN bit in the status register

control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when

low and WPEN bit is set to high. The user cannot write
to the status register (including the block protect bits and
the WPEN bit) and the block protected sections in the
memory array when the chip is hardware write pro-
tected. Only the sections of the memory array that are
not block protected can be written. Hardware write
protection is disabled when either

pin is high or the

WPEN bit is zero.

CAT25C32/64

Doc. No. 25087-00 8/99 SPI-1

Advanced Information

After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continu-
ing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address (1FFFh for 25C64 and FFFh for 25C32) is
reached, the address counter rolls over to 0000h allow-
ing the read cycle to be continued indefinitely. The read
operation is terminated by pulling the

high. To read

the status register, RDSR instruction should be sent.
The contents of the status register are shifted out on the
SO line. The status register may be read at any time
even during a write cycle. Read sequece is illustrated in
Figure 4. Reading status register is illustrated in Figure 5.

Figure 2. WREN Instruction Timing

Figure 3. WRDI Instruction Timing

DEVICE OPERATION

Write Enable and Disable
The CAT25C32/64 contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when V

is applied.

WREN instruction will enable writes (set the latch) to the
device. WRDI instruction will disable writes (reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.

READ Sequence
The part is selected by pulling

low. The 8-bit read

instruction is transmitted to the CAT25C32/64, followed
by the 16-bit address(the three Most Significant Bits are
don't care for 25C64 and four most significant bits are
don't care for 25C32).

Note: Dashed Line= mode (1, 1) -- -- -- --

HIGH IMPEDANCE

CAT25C32/64

Doc No. 25087 -00 8/99 SPI-1

Advanced Information

Figure 4. Read Instruction Timing

Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the

low,

issuing a write instruction via the SI line, followed by the
16-bit address (the three Most Significant Bits are don't
care for 25C64 and four most significant bits are don't
care for 25C32), and then the data to be written. Pro-
gramming will start after the

is brought high. Figure

6 illustrates byte write sequence.

WRITE Sequence
The CAT25C32/64 powers up in a Write Disable state.
Prior to any write instructions, the WREN instruction
must be sent to CAT25C32/64. The device goes into
Write enable state by pulling the

low and then

clocking the WREN instruction into CAT25C32/64. The

must be brought high after the WREN instruction to

enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without

being brought high, the data will not be written to the

array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.

Figure 5. RDSR Instruction Timing

Note: Dashed Line= mode (1, 1) -- -- -- --

BYTE ADDRESS*

*Please check the instruction set table for address

OPCODE

DATA OUT

MSB

HIGH IMPEDANCE

SCK

DATA OUT

MSB

HIGH IMPEDANCE

OPCODE

CAT25C32/64

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Advanced Information

Figure 7. WRSR Instruction Timing

restriction is that the 64 bytes must reside on the same
page. If the address counter reaches the end of the
page and clock continues, the counter will "roll over" to
the first address of the page and overwrite any data that
may have been written. The CAT25C32/64 is automati-
cally returned to the write disable state at the completion
of the write cycle. Figure 8 illustrates the page write
sequence.

To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.

During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register) in-
struction.

The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction.

Page Write
The CAT25C32/64 features page write capability. After
the first initial byte the host may continue to write up to
64 bytes of data to the CAT25C32/64. After each byte
of data is received, six lower order address bits are
internally incremented by one; the high order bits of
address will remain constant. The only

Figure 6. Write Instruction Timing

Note: Dashed Line= mode (1, 1)

Note: Dashed Line= mode (1, 1) -- -- -- --

ADDRESS

OPCODE

DATA IN

HIGH IMPEDANCE

SCK

MSB

HIGH IMPEDANCE

DATA IN

OPCODE

CAT25C32/64

Doc No. 25087 -00 8/99 SPI-1

Advanced Information

Figure 9.

HOLD

Timing

DESIGN CONSIDERATIONS

CAT25C32/64 goes into a write disable mode.

must

be set high after the proper number of clock cycles to
start an internal write cycle. Access to the array during
an internal write cycle is ignored and program-ming
is continued. On power up, SO is in a high impedance.

Figure 8. Page Write Instruction Timing

The CAT25C32/64 powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up

should be brought low

to enter a ready state and receive an instruction. After
a successful byte/page write or status register write the

Notes:
(1) The device used in the above example is a 25C64SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,

Tape & Reel)

ORDERING INFORMATION

Note: Dashed Line = mode (1, 1)

Note: Dashed Line= mode (1, 1) -- -- -- --

ADDRESS

Data
Byte 1

23 24-31

32-39

Data
Byte 2

Data
Byte 3

Data Byte N

OPCODE

7..1

24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1

DATA IN

HIGH IMPEDANCE

SCK

HOLD

tCD

tHD

tCD

tLZ

tHZ

HIGH IMPEDANCE

Package
P = 8-Pin PDIP
S = 8-Pin SOIC
U14= 14-Pin TSSOP
U20 = 20-Pin TSSOP

Prefix

Device #

Suffix

25C64

TE13

Product
Number
25C32: 32K
25C64: 64K

Tape & Reel
TE13: 2000/Reel

Operating Voltage
Blank = 2.5 to 6.0V
1.8 = 1.8 to 6.0V

-1.8

CAT

Temperature Range
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40° to +105°C)*

* -40°C to +125°C is available upon request

Optional
Company ID

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Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 25C64