DESCRIPTION
The CAT1026 and CAT1027 are complete memory and
supervisory solutions for microcontroller-based systems.
A 2k-bit serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together in low power CMOS technology. Memory
interface is via a 400kHz I
2
C bus.
The CAT1026 and CAT1027 provide a precision V
CC
sense circuit with five reset threshold voltage options
that support 5V, 3.3V and 3V systems. The power
supply monitor and reset circuit protects memory and
systems controllers during power up/down and against
brownout conditions. If power supply voltages are out of
tolerance reset signals become active preventing the
system microcontroller, ASIC, or peripherals from
operating.
The CAT1026 features two open drain reset outputs:
one (RESET) drives high and the other (
RESET
) drives
low whenever V
CC
falls below the threshold. Reset
outputs become inactive typically 200 ms after the
supply voltage exceeds the reset threshold value. With
both active high and low reset signals, interface to
microcontrollers and other ICs is simple. CAT1027 has
only a
RESET
output. In addition, the
RESET
pin can be
CAT1026, CAT1027
Dual Voltage Supervisory Circuits with I
2
C Serial 2k-bit CMOS EEPROM
FEATURES
Precision V
CC
power supply voltage monitor
-- 5V, 3.3 V and 3 V systems
-- Five threshold voltage options
Additional voltage monitoring
-- Externally adjustable down to 1.25 V
Watchdog timer (CAT1027 only)
Active high or low reset
-- Valid reset guaranteed to V
CC
= 1 V
400 kHz I
2
C bus
3.0 V to 5.5 V operation
Low power CMOS technology
16-Byte page write buffer
Built-in inadvertent write protection
1,000,000 Program/Erase cycles
Manual reset capability
100 year data retention
8-pin DIP, SOIC, TSSOP, MSOP or TDFN
(3 x 3 mm foot-print) packages
-- TDFN max height is 0.8mm
Industrial and extended temperature ranges
2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 3010, Rev. K
used as an input for push-button manual reset capability.
The CAT1026 and CAT1027 provide an auxiliary voltage
sensor input, V
SENSE
, which is used to monitor a second
system supply. The auxiliary high impedance comparator
drives the open drain output, V
LOW
, whenever the sense
voltage is below 1.25V threshold.
The CAT1027 is designed with a 1.6 second watchdog timer
circuit that resets a system to a known state if software or a
hardware glitch halts or "hangs" the system. The CAT1027
features a watchdog timer interrupt input, WDI.
The on-chip 2k-bit EEPROM memory features a 16-byte
page. In addition, hardware data protection is provided by a
V
CC
sense circuit that prevents writes to memory whenever
V
CC
falls below the reset threshold or until V
CC
reaches the
reset threshold during power up.
Available packages include an 8-pin DIP, 8-pin SOIC, 8-
pin TSSOP, 8-pin TDFN and 8-pin MSOP. The TDFN
package thickness is 0.8mm maximum. TDFN footprint is
3x3mm.
HA
LOGEN FREE
TM
LEAD FREE
2
CAT1026, CAT1027
Doc. No. 3010, Rev. K
Part Dash Minimum
Maximum
Number Threshold
Threshold
-45
4.50
4.75
-42
4.25
4.50
-30
3.00
3.15
-28
2.85
3.00
-25
2.55
2.70
RESET Threshold Options
BLOCK DIAGRAM
PIN CONFIGURATION
(Bottom View)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (RD4, ZD4)
VLOW
VCC
RESET
SCL
SDA
RESET
VSENSE
VSS
CAT1026
1
2
3
4
8
7
6
5
VCC
WDI
SCL
SDA
CAT1027
1
2
3
4
8
7
6
5
VLOW
RESET
VSENSE
VSS
1
2
3
4
8
7
6
5
VCC
RESET
SCL
SDA
VLOW
RESET
VSENSE
VSS
CAT1026
1
2
3
4
8
7
6
5
VCC
WDI
SCL
SDA
CAT1027
VLOW
RESET
VSENSE
VSS
2kbit
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
EEPROM
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
VSS
SDA
RESET
Controller
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
RESET
RESET
(CAT1026)
WDI
(CAT1027)
-
+
VCC
VSENSE
-
+
VREF
VLOW
VREF
Auxiliary Voltage Monitor
VCC Monitor
DIP Package (P, L)
SOIC Package (J, W)
TSSOP Package (U, Y)
MSOP Package (R, Z)
3
CAT1026, CAT1027
Doc No. 3010, Rev. K
PIN DESCRIPTION
RESET/
RESET
RESET
RESET
RESET
RESET
: RESET OUTPUTS
(RESET CAT1026 Only)
These are open drain pins and
RESET
can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull-down
resistor, and the
RESET
pin must be connected through a
pull-up resistor.
SDA:
SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire-ORed with other open drain
or open collector outputs.
SCL:
SERIAL CLOCK
Serial clock input.
V
SENSE
: AUXILIARY VOLTAGE MONITOR INPUT
The V
SENSE
input is a second voltage monitor which
is compared against CAT1026 and CAT1027 internal
reference voltage of 1.25V typically. Whenever the
input voltage is lower than 1.25V, the open drain
VLOW output will be driven low. An external resistor
divider is used to set the voltage level to be sensed.
Connect V
SENSE
to V
CC
if unused.
V
LOW
:
AUXILIARY VOLTAGE MONITOR OUTPUT
This open drain output goes low when V
SENSE
is less
than 1.25V and goes high when V
SENSE
exceeds the
reference voltage.
WDI (CAT1027 Only):
WATCHDOG TIMER INTERRUPT
Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low to
high does not occur every 1.6 seconds, the RESET
outputs will be driven active.
CAT10XX FAMILY OVERVIEW
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For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
PIN FUNCTIONS
Pin Name
Function
RESET
Active Low Reset Input/Output
V
SS
Ground
SDA
Serial Data/Address
SCL
Clock Input
RESET
Active High Reset Output (CAT1026 only)
V
CC
Power Supply
V
SENSE
Auxiliary Voltage Monitor Input
V
LOW
Auxiliary Voltage Monitor Output
WDI
Watchdog Timer Interrupt (CAT1027 only)
OPERATING TEMPERATURE RANGE
Industrial
-40C to 85C
Extended
-40C to 125C
4
CAT1026, CAT1027
Doc. No. 3010, Rev. K
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................. 55
C to +125
C
Storage Temperature ....................... 65
C to +150
C
Voltage on any Pin with
Respect to Ground
(1)
........... 2.0 V to V
CC
+ 2.0 V
V
CC
with Respect to Ground ............ 2.0 V to + 7.0 V
Package Power Dissipation
Capability (T
A
= 25
C) .................................. 1.0 W
DC OPERATING CHARACTERISTICS
V
CC
= 3.0 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Notes:
1.
V
IL
min and V
IH
max are reference values only and are not tested.
2.
This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Lead Soldering Temperature (10 seconds) ...... 300
C
Output Short Circuit Current
(2)
........................ 100 mA
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods may affect device
performance and reliability.
Note:
(1)
The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to
-2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is
V
CC
+0.5 V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2)
Output shorted for no more than one second. No more than one output shorted at a
time.
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CAT1026, CAT1027
Doc No. 3010, Rev. K
CAPACITANCE
T
A
= 25
C, f = 1.0 MHz, V
CC
= 5V
Symbol
Test
Test Conditions
Max
Units
C
OUT
(1)
Output Capacitance
V
OUT
= 0 V
8
pF
C
IN
(1)
Input Capacitance
V
IN
= 0 V
6
pF
AC CHARACTERISTICS
V
CC
= 3.0 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Notes:
1.
This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
2.
Test Conditions according to "AC Test Conditions" table.
3.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
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