2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
5V and 3.3V Supply Voltage Monitor and Reset Circuit
Doc. No. 25089, Rev. A
CAT1232LP/CAT1832
FEATURES
s
Selectable reset voltage tolerance
-- CAT1232LP for 5V supply
-- CAT1832 for 3.3V supply
s
Selectable watchdog period:
150ms, 600ms or 1.2 sec
s
Two reset outputs
-- Active high, push-pull reset output
-- Active low, open-drain reset output
(CAT1232LP)
-- Active low, push-pull reset output (CAT1832)
s
Debounced manual push-button reset
s
Compact SOIC and MSOP packages
DESCRIPTION
The CAT1232LP and CAT1832 microprocessor
supervisors can halt and restart a "hung-up" or "stalled"
microprocessor, restart a microprocessor after a power
failure, and debounce a manual/push-button micro-
processor reset switch. The devices are drop in
replacements for the Maxim/Dallas Semiconductor
DS1232LP and DS1832 supervisors
Precision reference and comparator circuits monitor the
5V or 3.3V system power supply voltage, V
CC
. During
power-up or when the power supply falls outside
selectable tolerance limits, both the RESET and
RESET
become active. After the power supply voltage rises
above the RESET threshold voltage, the reset signals
remain active for a minimum of 250ms, allowing the
power supply and system processor to stabilize. The
trip-point tolerance input, TOL, selects the trip level
tolerance to be either 5% or 10% for the CAT1232LP 5V
supply and 10% or 20% for the CAT1832 3.3V supply.
Each device has a push-pull, active HIGH reset output.
The CAT1232LP also has an open drain, active LOW
reset output while the CAT1832 also has a push-pull,
active LOW reset output.
A debounced manual reset input activates the reset
outputs and holds them active for a minimum period of
250ms after being released.
Also included is a watchdog timer to reset a
microprocessor that has stopped due to a software or
hardware failure. Three watchdog time-out periods are
selectable: 150ms, 600ms and 1.2sec. If the
ST
input is
not strobed low before the watchdog time out period
expires, the reset signals become active for a minimum
of 250ms.
APPLICATIONS
s
Microprocessor Systems
s
Portable Equipment
s
Controllers
s
Single Board Computers
s
Instrumentations
s
Telecommunications
FUNCTIONAL DIAGRAM
ST
RESET
PBRST
40k
TOL
V
CC
+
Reference
VCC
RESET
TD
Push Button Debounce
Watchdog Timebase Selection
Reset &
Watchdog Timer
(CAT1232LP)
Watchdog Transition Detector
RESET
(CAT1832)
Tolerance Selection
2
CAT1232LP/CAT1832
Doc. No. 25089, Rev. A
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ORDERING INFORMATION
PIN CONFIGURATION
PIN DESCRIPTION
VCC
ST
RESET
RESET
8-Lead SOIC/MSOP/DIP
1
2
3
4
8
7
6
5
PBRST
TD
TOL
GND
16-Lead SOIC
8
GND
7
NC
6
TOL
5
NC
4
TD
3
NC
2
PBRST
1
NC
9
RESET
10 NC
11 RESET
12 NC
13 ST
14 NC
15 VCC
16 NC
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CAT1232LP/CAT1832
Doc. No. 25089, Rev. A
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, 1.0V
V
CC
5.5V and over the operating temperature range of -40
C to +85
C. All
voltages are referenced to ground.
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
....................................... -0.5V to 7.0V
Voltage on
ST
and TD ................. -0.5V to V
CC
+ 0.5V
Voltage on
PBRST
,
RESET
and RESET ............................ -0.5V to V
CC
+ 0.5V
Notes:
(1)
PBRST
is internally pulled HIGH to V
CC
through a nominal 40k
resistor (R
PU
).
(2)
RESET
is an open drain output on the CAT1232LP.
(3) RESET remains within 0.5V of V
CC
on power-down until V
CC
falls
below 2V. RESET remains within 0.5V of ground on power-down
until V
CC
falls below 2.0V.
Maximum Junction Temperature ...................... 125
C
Storage Temperature Range ............ -65
C to +150
C
Lead Soldering Temperature (10 sec) .............. 300
C
Operating Temperature Range ........... -40
C to +85
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(4) Must not exceed the minimum watchdog time-out period (t
TD
).
The watchdog circuit cannot be disabled. To avoid a reset,
ST
must be strobed.
(5) Measured with V
CC
2.7V.
(6) Measured with V
CC
< 2.7V.
4
CAT1232LP/CAT1832
Doc. No. 25089, Rev. A
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
TYPICAL CHARACTERISTICS
For the CAT1232LP, V
CC
= 5V and T
AMB
= 25
C unless otherwise stated.
Threshold Voltage vs. Temperature (10% TOL)
Threshold Voltage vs. Temperature (5% TOL)
Supply Current vs. Temperature
Reset Active Time vs. Temperature
Reset Active Time Waveform
Transient Response
4.610
4.615
4.620
4.625
4.630
-50
0
50
100
TEMPERATURE (C)
THRESHOLD VOLTAGE (V)
TOL = GND (5%)
4.430
4.435
4.440
4.445
4.450
-50
0
50
100
TEMPERATURE (
C)
THRESHOLD VOLTAGE (V
)
TOL = Vcc (10%)
0
10
20
30
40
-50
0
50
100
TEMPERATURE (
C)
SUPPLY CURRENT (
A)
Vcc = 4.5V
Vcc = 5.5V
300
400
500
600
700
800
-50
0
50
100
TEMPERATURE (
C)
RESET ACTIVE TIME (ms)
Vcc = 5.5V
Vcc = 4.5V
TD = open
5
CAT1232LP/CAT1832
Doc. No. 25089, Rev. A
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
APPLICATION INFORMATION
SUPPLY VOLTAGE MONITOR
Reset Signal Polarity and Output Stage Structure
RESET
is an active LOW signal. It is developed with an
open drain driver in the CAT1232LP. A pull-up resistor
is required, typical values are 10k
to 50k
. The
CAT1832 uses a CMOS push-pull output stage for the
RESET
.
RESET is an active High signal developed by a CMOS
push-pull output stage and is the logical opposite to
RESET
.
Trip Point Tolerance Selection
The TOL input is used to select the V
CC
trip point
threshold. This selection is made connecting the TOL
input to ground or V
CC
. Connecting TOL to Ground
makes the V
CC
trip threshold 4.62V for the CAT1232LP
and 2.88V for the CAT1832.
Connecting TOL to VCC makes the VCC trip threshold
4.37V for the CAT1232LP and 2.55V for the CAT1832.
After V
CC
has risen above the trip point set by TOL,
RESET and
RESET
remain active for a minimum time
period of 250ms.
On power-down, once V
CC
falls below the reset threshold
the RESET outputs will remain active and are guaranteed
valid down to a V
CC
level of 1.0V.
e
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r
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A
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M
O
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X
A
M
P
L
2
3
2
1
T
A
C
V
=
L
O
T
C
C
%
0
1
5
2
.
4
7
3
.
4
9
4
.
4
P
L
2
3
2
1
T
A
C
D
N
G
=
L
O
T
%
5
0
5
.
4
2
6
.
4
4
7
.
4
2
3
8
1
T
A
C
V
=
L
O
T
C
C
%
0
2
7
4
.
2
5
5
.
2
4
6
.
2
2
3
8
1
T
A
C
=
L
O
T
D
N
G
%
0
1
0
8
.
2
8
8
.
2
7
9
.
2
Figure 1. Timing Diagram: Power Up
Figure 2. Timing Diagram: Power Down
V
CCTP(MAX)
V
CCTP
V
CCTP(MIN)
V
CC
RESET
RESET
t
R
t
RPU
V
OH
V
OL
V
CCTP(MAX)
V
CCTP
V
CCTP(MIN)
V
CC
RESET
RESET
t
F
V
OH
V
OL
t
RPD
Manual Reset Operation
Push-button input,
PBRST
, allows the user to issue
reset signals. The pushbutton input is debounced and is
pulled high through an internal 40k
resistor.
When
PBRST
is held low for the minimum time of 20 ms,
both resets become active and remain active for a
minimum time period of 250ms after
PBRST
returns
high.
No external pull-up resistor is required, since
PBRST
is
pulled high by an internal 40k
resistor.
PBRST
can be driven from a TTL or CMOS logic line or
short-ed to ground with a mechanical switch.
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