1
CAT1320, CAT1321
Supervisory Circuits with I
2
C Serial 32K CMOS EEPROM
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 20585, Rev. 00
HA
LOGEN FREE
TM
LEAD FREE
FEATURES
I
Precision power supply voltage monitor
-- 5V, 3.3V and 3V systems
- +5.0V (+/- 5%, +/- 10%)
- +3.3V (+/- 5%, +/- 10%)
- +3.0V (+/- 10%)
I
Active low reset, CAT1320
I
Active high reset, CAT1321
I
Valid reset guaranteed at V
CC
=1V
I
400kHz I
2
C bus
I
3.0V to 5.5V operation
I
Low power CMOS technology
I
64-Byte page write buffer
I
1,000,000 Program/Erase cycles
I
100 year data retention
I
8-pin DIP, SOIC, TSSOP and TDFN packages
I
Industrial temperature range
PIN CONFIGURATION
DESCRIPTION
The CAT1320 and CAT1321 are complete memory and
supervisory solutions for microcontroller-based systems.
A 32kbit serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together in low power CMOS technology. Memory
interface is via a 400kHz I
2
C bus.
The CAT1320 provides a precision V
CC
sense circuit
and drives an open drain output,
RESET low whenever
V
CC
falls below the reset threshold voltage.
The CAT1321 provides a precision VCC sense circuit
that drives an open drain output, RESET high whenever
V
CC
falls below the reset threshold voltage.
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals become
active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive
typically 200 ms after the supply voltage exceeds the reset
threshold level. With both active high and low reset options,
interface to microcontrollers and other ICs is simple. In
addition, the
RESET (CAT1320) pin can be used as an
input for push-button manual reset capability.
The CAT1320/21 memory features a 64-byte page. In
addition, hardware data protection is provided by a V
CC
sense circuit that prevents writes to memory whenever V
CC
falls below the reset threshold or until V
CC
reaches the reset
threshold during power up.
Available packages include an 8-pin DIP, SOIC, TSSOP
and 4.9 x 3mm TDFN.
PDIP (P, L) SOIC (J, W)
TDFN PACKAGE: 4.9MM X 3MM
(RD2, ZD2)
TSSOP (U, Y)
A0
VCC
RESET
SCL
SDA
A1
A2
VSS
CAT1320
1
2
3
4
8
7
6
5
VCC
RESET
SCL
SDA
CAT1321
1
2
3
4
8
7
6
5
A0
A1
A2
VSS
A0
VCC
RESET
SCL
SDA
A1
A2
VSS
CAT1320
1
2
3
4
8
7
6
5
CAT1321
1
2
3
4
8
7
6
5
VCC
RESET
SCL
SDA
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
RESET
SCL
SDA
CAT1320
A0
A1
A2
VSS
VCC
RESET
SCL
SDA
CAT1321
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
2
CAT1320, CAT1321
Advance Information
Doc. No. 25085, Rev. 00
PIN DESCRIPTION
RESET/
RESET
RESET
RESET
RESET
RESET: RESET OUTPUTS
These are open-drain pins and
RESET can also be used
as a manual reset trigger input. By forcing a reset condition
on the pin the device will initiate and maintain a reset
condition. The RESET pin must be connected through a
pull-down resistor and the
RESET pin must be connected
through a pull-up resistor.
SDA:
SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to trans-
fer all data into and out of the device. The SDA pin is an
open drain output and can be wire-ORed with other open
drain or open collector outputs.
BLOCK DIAGRAM -- CAT1320, CAT1321
PIN FUNCTIONS
Pin Name
Function
RESET
Active Low Reset Input/Output (CAT1320)
V
SS
Ground
SDA
Serial Data/Address
SCL
Clock Input
RESET
Active High Reset Output (CAT1321)
V
CC
Power Supply
OPERATING TEMPERATURE RANGE
Industrial
-40C to 85C
Part Dash Minimum
Maximum
Number Threshold
Threshold
-45
4.50
4.75
-42
4.25
4.50
-30
3.00
3.15
-28
2.85
3.00
-25
2.55
2.70
Threshold Voltage Options
SCL:
SERIAL CLOCK
Serial clock input.
A0, A1, A2:
DEVICE ADDRESS INPUTS
When hardwired, up to eight CAT1320/21 devices may
be addressed on a single bus system (refer to Device
Addressing). When the pins are left unconnected, the
default values are zeros.
32kbit
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
EEPROM
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
VSS
SDA
RESET Controller
Precision
Vcc Monitor
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
RESET (CAT1320)
RESET (CAT1321)
A0
A1
A2
3
Advance Information
CAT1320, CAT1321
Doc No. 25085, Rev. 00
D.C. OPERATING CHARACTERISTICS
V
CC
= +3.0V to +5.5V and over the recommended temperature conditions unless otherwise specified.
Notes:
1.
This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
2.
V
IL
min and V
IH
max are reference values only and are not tested.
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias .................... -40
C to +85C
Storage Temperature ........................ -65
C to +105C
Voltage on any Pin with
Respect to Ground
(1)
............. -0.5V to +V
CC
+2.0V
V
CC
with Respect to Ground ................ -0.5V to +7.0V
Package Power Dissipation
Capability (T
A
= 25
C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(1)
........................ 100 mA
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Note:
(1) Output shorted for no more than one second. No more than
one output shorted at a time.
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
n
i
M
p
y
T
x
a
M
s
t
i
n
U
I
I
L
t
n
e
r
r
u
C
e
g
a
k
a
e
L
t
u
p
n
I
V
N
I
c
c
V
o
t
D
N
G
=
2
-
0
1
A
I
O
L
t
n
e
r
r
u
C
e
g
a
k
a
e
L
t
u
p
t
u
O
V
N
I
c
c
V
o
t
D
N
G
=
0
1
-
0
1
A
I
1
C
C
)
e
t
i
r
W
(
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
f
L
C
S
z
H
k
0
0
4
=
V
C
C
V
5
.
5
=
3
A
m
I
2
C
C
)
d
a
e
R
(
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
f
L
C
S
z
H
k
0
0
4
=
V
C
C
V
5
.
5
=
1
A
m
I
B
S
t
n
e
r
r
u
C
y
b
d
n
a
t
S
,
V
5
.
5
=
c
c
V
V
N
I
c
c
V
r
o
D
N
G
=
0
4
A
V
L
I
2
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
5
.
0
-
c
c
V
x
3
.
0
V
V
H
I
2
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
c
c
V
x
7
.
0
5
.
0
+
c
c
V
V
V
L
O
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
,
A
D
S
(
T
E
S
E
R
)
I
L
O
A
m
3
=
V
C
C
V
0
.
3
=
4
.
0
V
V
H
O
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
)
T
E
S
E
R
(
I
H
O
A
m
4
.
0
-
=
V
C
C
V
0
.
3
=
-
c
c
V
5
7
.
0
V
V
H
T
d
l
o
h
s
e
r
h
T
t
e
s
e
R
5
4
-
x
2
3
1
T
A
C
V
(
C
C
)
V
5
=
0
5
.
4
5
7
.
4
V
2
4
-
x
2
3
1
T
A
C
V
(
C
C
)
V
5
=
5
2
.
4
0
5
.
4
0
3
-
x
2
3
1
T
A
C
V
(
C
C
)
V
3
.
3
=
0
0
.
3
5
1
.
3
8
2
-
x
2
3
1
T
A
C
V
(
C
C
)
V
3
.
3
=
5
8
.
2
0
0
.
3
5
2
-
x
2
3
1
T
A
C
V
(
C
C
)
V
3
=
5
5
.
2
0
7
.
2
V
D
I
L
A
V
R
1
V
d
il
a
V
t
u
p
t
u
O
t
e
s
e
R
C
C
e
g
a
t
l
o
V
0
0
.
1
V
V
T
R
1
s
i
s
e
r
e
t
s
y
H
d
l
o
h
s
e
r
h
T
t
e
s
e
R
5
1
V
m
4
CAT1320, CAT1321
Advance Information
Doc. No. 25085, Rev. 00
CAPACITANCE
T
A
= 25
C, f = 1.0 MHz, V
CC
= 5V
Symbol
Test
Test Conditions
Max
Units
C
OUT
(1)
Output Capacitance
V
OUT
= 0V
8
pF
C
IN
(1)
Input Capacitance
V
IN
= 0V
6
pF
A.C. CHARACTERISTICS
V
CC
= 3.0V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Notes:
1.
This parameter is characterized initially and after a design or process change that affects
the parameter. Not 100% tested.
2.
Test Conditions according to "AC Test Conditions" table.
3.
The write cycle time is the time from a valid stop condition of a write sequence to the end of
the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled,
SDA is allowed to remain high and the device does not respond to its slave address.
e
l
c
y
C
e
t
i
r
W
&
d
a
e
R
y
r
o
m
e
M
2
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
n
i
M
x
a
M
s
t
i
n
U
f
L
C
S
y
c
n
e
u
q
e
r
F
k
c
o
l
C
0
0
4
z
H
k
t
P
S
1
e
k
i
p
S
r
e
t
li
F
t
u
p
n
I
)
L
C
S
,
A
D
S
(
n
o
i
s
s
e
r
p
p
u
S
0
0
1
s
n
t
W
O
L
d
o
i
r
e
P
w
o
L
k
c
o
l
C
3
.
1
s
t
H
G
I
H
d
o
i
r
e
P
h
g
i
H
k
c
o
l
C
6
.
0
s
t
R
1
e
m
i
T
e
s
i
R
L
C
S
d
n
a
A
D
S
0
0
3
s
n
t
F
1
e
m
i
T
ll
a
F
L
C
S
d
n
a
A
D
S
0
0
3
s
n
t
A
T
S
;
D
H
e
m
i
T
d
l
o
H
n
o
i
t
i
d
n
o
C
t
r
a
t
S
6
.
0
s
t
A
T
S
;
U
S
e
m
i
T
p
u
t
e
S
n
o
i
t
i
d
n
o
C
t
r
a
t
S
)
t
r
a
t
S
d
e
t
a
e
p
e
R
a
r
o
f
(
6
.
0
s
t
T
A
D
;
D
H
e
m
i
T
d
l
o
H
t
u
p
n
I
a
t
a
D
0
s
n
t
T
A
D
;
U
S
e
m
i
T
p
u
t
e
S
t
u
p
n
I
a
t
a
D
0
0
1
s
n
t
O
T
S
;
U
S
e
m
i
T
p
u
t
e
S
n
o
i
t
i
d
n
o
C
p
o
t
S
6
.
0
s
t
A
A
d
il
a
V
t
u
O
a
t
a
D
o
t
w
o
L
L
C
S
0
0
9
s
n
t
H
D
e
m
i
T
d
l
o
H
t
u
O
a
t
a
D
0
5
s
n
t
F
U
B
1
a
e
r
o
f
e
B
e
e
r
F
e
b
t
s
u
m
s
u
B
e
h
t
e
m
i
T
t
r
a
t
S
n
a
C
n
o
i
s
s
i
m
s
n
a
r
T
w
e
N
3
.
1
s
t
C
W
3
)
e
g
a
P
r
o
e
t
y
B
(
e
m
i
T
e
l
c
y
C
e
t
i
r
W
5
s
m
5
Advance Information
CAT1320, CAT1321
Doc No. 25085, Rev. 00
RESET CIRCUIT A.C. CHARACTERISTICS
Notes:
1.
Test Conditions according to "AC Test Conditions" table.
2.
Power-up, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to "AC Test Conditions" Table
3.
Power-Down, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to "AC Test Conditions" Table
4.
V
CC
Glitch Reference Voltage = V
THmin
; Based on characterization data
5.
This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6.
t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified memory operation can be initiated.
AC TEST CONDITIONS
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
N
END
(1)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
T
DR
(1)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
V
ZAP
(1)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
I
LTH
(1)(2)
Latch-Up
JEDEC Standard 17
100
mA
s
e
g
a
t
l
o
v
e
s
l
u
p
t
u
p
n
I
V
2
.
0
C
C
V
8
.
0
o
t
C
C
s
e
m
i
t
ll
a
f
d
n
a
e
s
i
r
t
u
p
n
I
s
n
0
1
s
e
g
a
t
l
o
v
e
c
n
e
r
e
f
e
r
t
u
p
n
I
V
3
.
0
C
C
V
7
.
0
,
C
C
s
e
g
a
t
l
o
v
e
c
n
e
r
e
f
e
r
t
u
p
t
u
O
V
5
.
0
C
C
d
a
o
L
t
u
p
t
u
O
I
:
e
c
r
u
o
S
t
n
e
r
r
u
C
L
O
;
A
m
3
=
C
L
F
p
0
0
1
=
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
t
s
e
T
s
n
o
i
t
i
d
n
o
C
n
i
M
p
y
T
x
a
M
s
t
i
n
U
t
T
S
R
U
P
t
u
o
e
m
i
T
t
e
s
e
R
2
e
t
o
N
0
3
1
0
0
2
0
7
2
s
m
t
D
P
R
V
H
T
y
a
l
e
D
t
u
p
t
u
o
T
E
S
E
R
o
t
3
e
t
o
N
5
s
t
H
C
T
I
L
G
V
C
C
h
t
d
i
W
e
s
l
u
P
t
c
e
j
e
R
h
c
t
il
G
5
,
4
e
t
o
N
0
3
s
n
h
c
t
il
G
R
M
y
t
i
n
u
m
m
I
h
c
t
il
G
t
e
s
e
R
l
a
u
n
a
M
5
e
t
o
N
0
0
1
s
n
t
W
R
M
h
t
d
i
W
e
s
l
u
P
R
M
5
e
t
o
N
5
s
G
N
I
M
I
T
P
U
-
R
E
W
O
P
6
,
5
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
t
s
e
T
s
n
o
i
t
i
d
n
o
C
n
i
M
p
y
T
x
a
M
s
t
i
n
U
t
R
U
P
n
o
i
t
a
r
e
p
O
d
a
e
R
o
t
p
U
-
r
e
w
o
P
0
7
2
s
m
t
W
U
P
n
o
i
t
a
r
e
p
O
e
t
i
r
W
o
t
p
U
-
r
e
w
o
P
0
7
2
s
m
Notes:
1.
This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
2.
Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V
CC
+ 1V.
PDF 
ZIP