1
CAT22C10
256-Bit Nonvolatile CMOS Static RAM
FEATURES
s
Single 5V Supply
s
Fast RAM Access Times:
200ns
300ns
s
Infinite E
2
PROM to RAM Recall
s
CMOS and TTL Compatible I/O
s
Power Up/Down Protection
s
100,000 Program/Erase Cycles (E
2
PROM)
s
Low CMOS Power Consumption:
Active: 40mA Max.
Standby: 30
A Max.
s
JEDEC Standard Pinouts:
18-pin DIP
16-pin SOIC
s
10 Year Data Retention
s
Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT22C10 NVRAM is a 256-bit nonvolatile memory
organized as 64 words x 4 bits. The high speed Static
RAM array is bit for bit backed up by a nonvolatile
E
2
PROM array which allows for easy transfer of data
from RAM array to E
2
PROM (STORE) and from
E
2
PROM to RAM (RECALL). STORE operations are
completed in 10ms max. and RECALL operations typi-
cally within 1.5
s. The CAT22C10 features unlimited
RAM write operations either through external RAM
PIN CONFIGURATION
PIN FUNCTIONS
Pin Name
Function
A
0
A
5
Address
I/O
0
I/O
3
Data In/Out
WE
Write Enable
CS
Chip Select
RECALL
Recall
STORE
Store
V
CC
+5V
V
SS
Ground
NC
No Connect
writes or internal recalls from E
2
PROM. Internal false
store protection circuitry prohibits STORE operations
when V
CC
is less than 3.0V.
The CAT22C10 is manufactured using Catalyst's ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles (E
2
PROM)
and has a data retention of 10 years. The device is
available in JEDEC approved 18-pin plastic DIP and 16-
pin SOIC packages.
SOIC Package (J)
DIP Package (P)
1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
NC
A4
A3
A2
Vss
A1
CS
STORE
A0
NC
Vcc
A5
I/O3
I/O2
I/O1
I/O0
WE
RECALL
1
2
3
4
5
6
7
8
9
1 4
13
11
10
12
1 5
1 6
1 7
1 8
1
2
3
4
5
6
7
8
1 4
13
11
10
9
12
1 5
1 6
A1
A2
A3
A4
A0
A5
Vcc
I/O4
I/O3
I/O2
I/O1
Vss
WE
CS
STORE
RECALL
22C10 F01
22C10 F02
Doc. No. 25018-0A 2/98 N-1
CAT22C10
2
Doc. No. 25018-0A 2/98 N-1
MODE SELECTION
(1)(2)(3)
Input
Mode
CS
CS
CS
CS
CS
WE
WE
WE
WE
WE
RECALL
RECALL
RECALL
RECALL
RECALL
STORE
STORE
STORE
STORE
STORE
I/O
Standby
H
X
H
H
Output High-Z
RAM Read
L
H
H
H
Output Data
RAM Write
L
L
H
H
Input Data
(E
2
PROM
RAM)
X
H
L
H
Output High-Z RECALL
(E
2
PROM
RAM)
H
X
L
H
Output High-Z RECALL
(RAM
E
2
PROM)
X
H
H
L
Output High-Z STORE
(RAM
E
2
PROM)
H
X
H
L
Output High-Z STORE
BLOCK DIAGRAM
POWER-UP TIMING
(4)
Symbol
Parameter
Min.
Max.
Units
VCCSR
V
CC
Slew Rate
0.5
0.005
V/ms
Note:
(1)
RECALL
signal has priority over
STORE
signal when both are applied at the same time.
(2)
STORE
is inhibited when
RECALL
is active.
(3) The store operation is inhibited when V
CC
is below
3.0V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
ROW
SELECT
COLUMN SELECT
CONTROL
LOGIC
READ/WRITE
CIRCUITS
RECALL
E
2
PROM ARRAY
STORE
A0
A1
A2
A3
A4
A5
STORE
RECALL
CS
WE
I/O0 I/O1 I/O2 I/O3
STATIC RAM
ARRAY
5153 FHD F02
CAT22C10
3
Doc. No. 25018-0A 2/98 N-1
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55
C to +125
C
Storage Temperature ....................... 65
C to +150
C
Voltage on Any Pin with
Respect to Ground
(2)
.............. -2.0 to +VCC +2.0V
V
CC
with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25
C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(3)
........................ 100 mA
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Reference Test Method
N
END
(1)
Endurance
100,000
Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR
(1)
Data Retention
10
Years
MIL-STD-883, Test Method 1008
V
ZAP
(1)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
I
LTH
(1)(4)
Latch-Up
100
mA
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
V
CC
= +5V
10%, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
I
CC
Current Consumption
40
mA
All Inputs = 5.5V
(Operating)
T
A
= 0
C
All I/O's Open
I
SB
Current Consumption
30
A
CS = V
CC
(Standby)
All I/O's Open
I
LI
Input Current
10
A
0
V
IN
5.5V
I
LO
Output Leakage Current
10
A
0
V
OUT
5.5V
V
IH
High Level Input Voltage
2
V
CC
V
V
IL
Low Level Input Voltage
0
0.8
V
V
OH
High Level Output Voltage
2.4
V
I
OH
= 2mA
V
OL
Low Level Output Voltage
0.4
V
I
OL
= 4.2mA
V
DH
RAM Data Holding Voltage
1.5
5.5
V
V
CC
CAPACITANCE T
A
= 25
C, f = 1.0 MHz, V
CC
= 5V
Symbol
Parameter
Max.
Unit
Conditions
C
I/O
(1)
Input/Output Capacitance
10
pF
V
I/O
= 0V
C
IN
(1)
Input Capacitance
6
pF
V
IN
= 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to V
CC
+1V.
CAT22C10
4
Doc. No. 25018-0A 2/98 N-1
A.C. CHARACTERISTICS, Read Cycle
V
CC
= +5V
10%, unless otherwise specified.
22C10-20
22C10-30
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
Conditions
t
RC
Read Cycle Time
200
300
ns
C
L
= 100pF
t
AA
Address Access Time
200
300
ns
+1TTL gate
t
CO
CS Access Time
200
300
ns
V
OH
= 2.2V
t
OH
Output Data Hold Time
0
0
ns
V
OL
= 0.65V
t
LZ
(1)
CS Enable Time
0
0
ns
V
IH
= 2.2V
t
HZ
(1)
CS Disable Time
100
100
ns
V
IL
= 0.65V
A.C. CHARACTERISTICS, Write Cycle
V
CC
= +5V
10%, unless otherwise specified.
22C10-20
22C10-30
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
Conditions
t
WC
Write Cycle Time
200
300
ns
t
CW
CS Write Pulse Width
150
150
ns
t
AS
Address Setup Time
50
50
ns
C
L
= 100pF
t
WP
Write Pulse Width
150
150
ns
+1TTL gate
t
WR
Write Recovery Time
25
25
ns
V
OH
= 2.2V
t
DW
Data Valid Time
100
100
ns
V
OL
= 0.65V
t
DH
Data Hold Time
0
0
ns
V
IH
= 2.2V
t
WZ
(1)
Output Disable Time
100
100
ns
V
IL
= 0.65V
t
OW
Output Enable Time
0
0
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
CAT22C10
5
Doc. No. 25018-0A 2/98 N-1
A.C. CHARACTERISTICS, Store Cycle
V
CC
= +5V
10%, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Max.
Units
Conditions
t
STC
Store Time
10
ms
t
STP
Store Pulse Width
200
ns
C
L
= 100pF + 1TTL gate
t
STZ
(1)
Store Disable Time
100
ns
V
OH
= 2.2V, V
OL
= 0.65V
t
OST
(1)
Store Enable Time
0
ns
V
IH
= 2.2V, V
IL
= 0.65V
A.C. CHARACTERISTICS, Recall Cycle
V
CC
= +5V
10%, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Max.
Units
Conditions
t
RCC
Recall Cycle Time
1.4
s
t
RCP
Recall Pulse Width
300
ns
C
L
= 100pF + 1TTL gate
t
RCZ
Recall Disable Time
100
ns
V
OH
= 2.2V, V
OL
= 0.65V
t
ORC
Recall Enable Time
0
ns
V
IH
= 2.2V, V
IL
= 0.65V
t
ARC
Recall Data Access Time
1.1
s
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
CAT22C10
6
Doc. No. 25018-0A 2/98 N-1
DEVICE OPERATION
The configuration of the CAT22C10 allows a common
address bus to be directly connected to the address
inputs. Additionally, the Input/Output (I/O) pins can be
directly connected to a common I/O bus if the bus has
less than 1 TTL load and 100pF capacitance. If not, the
I/O path should be buffered.
When the chip select (
CS
) pin goes low, the device is
activated. When CS is forced high, the device goes into
the standby mode and consumes very little current. With
the nonvolatile functions inhibited, the device operates
like a Static RAM. The Write Enable (
WE
) pin selects a
write operation when
WE
is low and a read operation
when
WE
is high. In either of these modes, an array byte
(4 bits) can be addressed uniquely by using the address
lines (A
0
A
5
), and that byte will be read or written to
through the Input/Output pins (I/O
0
I/O
3
).
The nonvolatile functions are inhibited by holding the
STORE
input and the
RECALL
input high. When the
RECALL
input is taken low, it initiates a recall operation
which transfers the contents of the entire E
2
PROM array
into the Static RAM. When the
STORE
input is taken low,
it initiates a store operation which transfers the entire
Static RAM array contents into the E
2
PROM array.
Standby Mode
The chip select (
CS
) input controls all of the functions of
the CAT22C10. When a high level is supplied to the
CS
pin, the device goes into the standby mode where the
outputs are put into a high impendance state and the
power consumption is drastically reduced. With I
SB
less
than 100
A in standby mode, the designer has the
flexibility to use this part in battery operated systems.
Read
When the chip is enabled (
CS
= low), the nonvolatile
functions are inhibited (
STORE
= high and
RECALL
=
high). With the Write Enable (
WE
) pin held high, the data
in the Static RAM array may be accessed by selecting an
address with input pins A
0
A
5
. This will occur when the
outputs are connected to a bus which is loaded by no
more than 100pF and 1 TTL gate. If the loading is greater
than this, some additional buffering circuitry is recom-
mended.
Figure 1. Read Cycle Timing
5153 FHD F06
ADDRESS
CS
DATA I/O
tRC
tCO
tAA
tLZ
tOH
tHZ
HIGH-Z
DATA VALID
CAT22C10
7
Doc. No. 25018-0A 2/98 N-1
Write
With the chip enabled and the nonvolatile functions
inhibited, the Write Enable (
WE
) pin will select the write
mode when driven to a low level. In this mode, the
address must be supplied for the byte being written.
After the set-up time (t
AS
), the input data must be
supplied to pins I/O
0
I/O
3
. When these conditions, in-
Figure 2. Write Cycle Timing
5153 FHD F04
Figure 3. Early Write Cycle Timing
5153 FHD F05
cluding the write pulse width time (t
WP
) are met, the data
will be written to the specified location in the Static RAM.
A write function may also be initiated from the standby
mode by driving
WE
low, inhibiting the nonvolatile func-
tions, supplying valid addresses, and then taking
CS
low
and supplying input data.
tWC
tAS
tWR
DATA VALID
CS
DATA IN
ADDRESS
WE
tWP
tDW
tCW
tDH
DATA OUT
HIGH-Z
tWC
tAS
tWR
DATA VALID
CS
DATA IN
ADDRESS
WE
tWP
tDW
tCW
tDH
DATA OUT
tWZ
tOW
HIGH-Z
CAT22C10
8
Doc. No. 25018-0A 2/98 N-1
Recall
At anytime, except during a store operation, taking the
RECALL
pin low will initiate a recall operation. This is
independent of the state of
CS
,
WE
, or A
0
A
5
. After the
RECALL
pin has been held low for the duration of the
Recall Pulse Width (t
RCP
), the recall will continue inde-
pendent of any other inputs. During the recall, the entire
contents of the E
2
PROM array is transferred to the Static
RAM array. The first byte of data may be externally
accessed after the recalled data access time from end of
recall (t
ARC
) is met. After this, any other byte may be
accessed by using the normal read mode.
If the
RECALL
pin is held low for the entire Recall Cycle
time (t
RCC
), the contents of the Static RAM may be
immediately accessed by using the normal read mode.
A recall operation can be performed an unlimited num-
ber of times without affecting the integrity of the data.
The outputs I/O
0
I/O
3
will go into the high impedance
state as long as the
RECALL
signal is held low.
Store
At any time, except during a recall operation, taking the
STORE
pin low will initiate a store operation. This takes
place independent of the state of
CS
,
WE
or A
0
A
5
. The
STORE
pin must be held low for the duration of the Store
Pulse Width (t
STP
) to ensure that a store operation is
initiated. Once initiated, the
STORE
pin becomes a
"Don't Care", and the store operation will complete its
transfer of the entire contents of the Static RAM array
into the E
2
PROM array within the Store Cycle time
(t
STC
). If a store operation is initiated during a write cycle,
the contents of the addressed Static RAM byte and its
corresponding byte in the E
2
PROM array will be un-
known.
During the store operation, the outputs are in a high
impedance state. A minimum of 100,000 store opera-
tions can be performed reliably and the data written into
the E
2
PROM array has a minimum data retention time
of 10 years.
DATA PROTECTION DURING POWER-UP AND
POWER-DOWN
The CAT22C10 has on-chip circuitry which will prevent
a store operation from occurring when V
CC
falls below
3.0V typ. This function eliminates the potential hazard of
spurious signals initiating a store operation when the
system power is below 3.0V typ.
Figure 4. Recall Cycle Timing
5153 FHD F08
5153 FHD F07
Figure 5. Store Cycle Timing
CS
DATA I/O
RECALL
ADDRESS
DATA UNDEFINED
DATA VALID
HIGH-Z
tRCZ
tORC
tARC
tRCP
tRCC
STORE
DATA I/O
tSTZ
tOST
HIGH-Z
tSTP
tSTC
CAT22C10
9
Doc. No. 25018-0A 2/98 N-1
22C10 F08
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a 22C10JI-20TE13 (SOIC, Industrial Temperature, 200ns Access Time, Tape & Reel)
Prefix
Device #
Suffix
22C10
J
I
-TE13
Product
Number
Tape & Reel
TE13: 2000/Reel
Package
P: PDIP
J: SOIC (JEDEC)
-20
Speed
20: 200ns
30: 300ns
CAT
Temperature Range
Blank = Commercial (0 - 70C)
I = Industrial (-40 - 85C)
A = Automotive (-40 - 105C)*
* -40 to +125C is available upon request
Optional
Company ID
CAT22C10
10
Doc. No. 25018-0A 2/98 N-1
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