1
A1
A2
VSS
A1
A2
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A0
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
VSS
A0
DESCRIPTION
The CAT24AC128 is a 128kbit Serial CMOS EEPROM
internally organized as 16,384 words of 8 bits each.
Catalyst's advanced CMOS technology substantially
reduces device power requirements. The CAT24AC128
features a 64-byte page write buffer. The device operates
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
I
Commercial, industrial and extended
automotive temperature ranges
I
Write protect feature
Entire array protected when WP at V
IH
I
1,000,000 program/erase cycles
I
100 year data retention
I
8-Pin DIP, 8-Pin SOIC (JEDEC/EIAJ) or
14-pin TSSOP
via the I
2
C bus serial interface and is available in 8-pin
DIP, 8-pin SOIC or 14-pin TSSOP packages. Three
device address inputs allows up to 8 devices to share a
common 2-wire I
2
C bus.
PIN CONFIGURATION
BLOCK DIAGRAM
I
400kHz (2.5V) and 100kHz (1.8V) I
2
C bus
compatibility
I
1.8 to 5.5 volt operation
I
Low power CMOS technology
I
Schmitt trigger filtered inputs for noise
suppression
I
64-Byte page write buffer
I
Self-timed write cycle with auto-clear
FEATURES
DIP Package (P, L)
SOIC Package (J, K, W, X)
2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
STATE COUNTERS
E
2
PROM
256X512
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
VSS
WP
SCL
SDA
256
512
SLAVE
ADDRESS
COMPARATORS
A0
A1
A2
Doc. No. 1028, Rev. I
TSSOP Package (U14, Y14)
A1
NC
NC
A2
A0
SDA
WP
NC
NC
NC
SCL
NC
VSS
V CC
14
13
12
11
1
2
3
4
5
6
7
10
9
8
CAT24AC128
128kbit I
2
C Serial CMOS EEPROM With Three Chip Address Input Pins
HA
LOGEN FREE
TM
LEAD FREE
PIN FUNCTIONS
Pin Name
Function
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
V
CC
+1.8V to +5.5V Power Supply
V
SS
Ground
A0 - A2
Device Address Inputs
CAT24AC128
2
Doc. No. 1028, Rev. I
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
I
CC1
Power Supply Current - Read
f
SCL
= 100 KHz
1
mA
V
CC
= 5V
I
CC2
Power Supply Current - Write
f
SCL
= 100 KHz
3
mA
V
CC
= 5V
I
SB
(5)
Standby Current
V
IN
= GND or V
CC
1
A
V
CC
= 5V
I
LI
Input Leakage Current
V
IN
= GND to V
CC
3
A
I
LO
Output Leakage Current
V
OUT
= GND to V
CC
3
A
V
IL
Input Low Voltage
1
V
CC
x 0.3
V
V
IH
Input High Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output Low Voltage (V
CC
= +3.0V)
I
OL
= 3.0 mA
0.4
V
V
OL2
Output Low Voltage (V
CC
= +1.8V)
I
OL
= 1.5 mA
0.5
V
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55
C to +125C
Storage Temperature ....................... 65
C to +150C
Voltage on Any Pin with
Respect to Ground
(1)
........... 2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25
C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(2)
........................ 100mA
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
CAPACITANCE T
A
= 25
C, f = 1.0 MHz, V
CC
= 5V
Symbol
Test
Conditions
Min
Typ
Max
Units
C
I/O
(3)
Input/Output Capacitance (SDA)
V
I/O
= 0V
8
pF
C
IN
(3)
Input Capacitance (SCL, WP, A0, A1, A2)
V
IN
= 0V
6
pF
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V
CC
+1V.
(5) Maximum standby current (I
SB
) = 10
A for the Extended Automotive temperature range.
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Max.
Units
N
END
(3)
Endurance
1,000,000
Cycles/Byte
T
DR
(3)
Data Retention
100
Years
V
ZAP
(3)
ESD Susceptibility
2000
Volts
I
LTH
(3)(4)
Latch-up
100
mA
CAT24AC128
3
Doc. No. 1028, Rev. I
Power-Up Timing
(1)(2)
Symbol
Parameter
Min
Typ
Max
Units
t
PUR
Power-Up to Read Operation
1
ms
t
PUW
Power-Up to Write Operation
1
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During
the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave
address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
FUNCTIONAL DESCRIPTION
The CAT24AC128 supports the I
2
C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24AC128
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or receiver,
but the Master device controls which mode is activated.
A.C. CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
V
CC
= 1.8 V - 5.5 V
V
CC
= 2.5 V - 5.5 V
Min
Max
Min
Max
Units
F
SCL
Clock Frequency
100
400
kHz
t
AA
SCL Low to SDA Data Out
0.1
3.5
0.05
0.9
s
and ACK Out
t
BUF
(1)
Time the Bus Must be Free Before
4.7
1.2
s
a New Transmission Can Start
t
HD:STA
Start Condition Hold Time
4.0
0.6
s
t
LOW
Clock Low Period
4.7
1.2
s
t
HIGH
Clock High Period
4.0
0.6
s
t
SU:STA
Start Condition Setup Time
4.0
0.6
s
(for a Repeated Start Condition)
t
HD:DAT
Data In Hold Time
0
0
ns
t
SU:DAT
Data In Setup Time
100
100
ns
t
R
(1)
SDA and SCL Rise Time
1.0
0.3
s
t
F
(1)
SDA and SCL Fall Time
300
300
ns
t
SU:STO
Stop Condition Setup Time
4.7
0.6
s
t
DH
Data Out Hold Time
100
50
ns
t
WR
Write Cycle Time
5
5
ms
t
SP
Input Suppression (SDA, SCL)
100
100
ns
CAT24AC128
4
Doc. No. 1028, Rev. I
Figure 3. Start/Stop Timing
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
I
2
C BUS PROTOCOL
The features of the I
2
C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24AC128 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
entire memory is write protected. When left floating,
memory is unprotected.
A0, A1, A2: Device Address Inputs
These inputs set the device address when cascading
multiple devices. When these pins are left floating the
default values are zeroes. A maximum of eight devices
can be cascaded.
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
START BIT
SDA
STOP BIT
SCL
CAT24AC128
5
Doc. No. 1028, Rev. I
1
0
1
0
A2
A1
A0
R/W
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The next three significant bits (A2, A1, A0)
are the device address bits and define which device the
master is accessing. Up to eight CAT24AC128 devices
may be individually addressed by the system. The last
bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24AC128 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24AC128 then performs a Read or Write operation
depending on the state of the R/
W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT24AC128 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
Figure 4. Acknowledge Timing
Figure 5. Slave Address Bits
When the CAT24AC128 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24AC128 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/
W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24AC128. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24AC128 acknowledges once
more and the Master generates the STOP condition. At
this time, the device begins an internal programming
cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24AC128 writes up to 64 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
A2
A1
A0
*A0, A1 and A2 must compare to its corresonding hard wired inputs (pins 1, 2 and 3).
ACKNOWLEDGE
1
START
SCL FROM
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
CAT24AC128
6
Doc. No. 1028, Rev. I
to send up to 63 additional bytes. After each byte has
been transmitted, CAT24AC128 will respond with an
acknowledge, and internally increment the six low order
address bits by one. The high order bits remain
unchanged.
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter `wraps around',
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24AC128 in a single write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24AC128 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24AC128 is still busy with the
write operation, no ACK will be returned. If
CAT24AC128 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to V
CC
, the entire memory array is
protected and becomes read only. The CAT24AC128
will accept both slave and byte addresses, but the
memory location accessed is protected from
programming by the device's failure to send an
acknowledge after the first byte of data is received.
READ OPERATIONS
The READ operation for the CAT24AC128 is initiated in
the same manner as the write operation with one
exception, that R/
W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
Immediate/Current Address Read
The CAT24AC128's address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N+1. If N=E (where E=16383),
then the counter will `wrap around' to address 0 and
continue to clock out data. After the CAT24AC128
receives its slave address information (with the R/
W bit
set to one), it issues an acknowledge, then transmits the
8 bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
Selective/Random Address Read
Selective/Random READ operations allow the Master
Figure 7. Page Write Timing
Figure 6. Byte Write Timing
A15A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
DATA
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7A0
BYTE ADDRESS
A
C
K
*
*
A15A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7A0
BYTE ADDRESS
DATA n+63
DATA
A
C
K
S
T
O
P
A
C
K
DATA n
A
C
K
P
A
C
K
*
*
*
=Don't Care Bit
*
=Don't Care Bit
CAT24AC128
7
Doc. No. 1028, Rev. I
device to select at random any memory location for a
READ operation. The Master device first performs a
`dummy' write operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After CAT24AC128 acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/
W bit set to one. The
CAT24AC128 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24AC128 sends the initial 8-bit
byte requested, the Master will respond with an
acknowledge which tells the device it requires more
Figure 8. Current Address Read Timing
data. The CAT24AC128 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24AC128 is
outputted sequentially with data from address N followed
by data from address N+1. The READ operation address
counter increments all of the CAT24AC128 address bits
so that the entire memory array can be read during one
operation. If more than E (where E=16383) bytes are
read out, the counter will `wrap around' and continue to
clock out data bytes.
Figure 9. Random Address Read Timing
*
=Don't Care Bit
24AC128 F08
SCL
SDA
8TH BIT
STOP
NO ACK
DATA OUT
8
9
SLAVE
ADDRESS
S
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
N
O
A
C
K
DATA
S
T
O
P
P
A15A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7A0
BYTE ADDRESS
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
A
R
T
DATA
P
S
T
O
P
*
*
CAT24AC128
8
Doc. No. 1028, Rev. I
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT24AC128KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt
Operating Voltage, Tape & Reel)
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA). For additional
information, please contact your Catalyst sales office.
Figure 10. Sequential Current Address Read Timing
DATA n+x
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
S
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
24AC128
L: PDIP (Lead-free, Halogen-free)
X: SOIC, EIAJ (Lead-free, Halogen-free)
W: SOIC, JEDEC (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GX: SOIC, EIAJ (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
Blank: 2.5V - 5.5V
1.8: 1.8V - 5.5V
Rev A
(2)
Die Revision
A15A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7A0
BYTE ADDRESS
SLAVE
ADDRESS
S
A
C
K
S
T
A
R
T
*
*
DATA n+x
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
Figure 11. Sequential Random Address Read Timing
CAT24AC128
9
Doc. No. 1028, Rev. I
Notes:
1.
Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
2.
All linear dimensions are in inches and parenthetically in millimeters.
0.180 (4.57) MAX
0.015 (0.38)
0.100 (2.54)
BSC
0.014 (0.36)
0.022 (0.56)
0.245 (6.17)
0.295 (7.49)
0.045 (1.14)
0.060 (1.52)
0.110 (2.79)
0.150 (3.81)
0.120 (3.05)
0.150 (3.81)
0.300 (7.62)
0.325 (8.26)
0.310 (7.87)
0.380 (9.65)
0.355 (9.02)
0.400 (10.16)
8-LEAD 300 MIL WIDE PLASTIC DIP (P, L)
8-LEAD 150 MIL WIDE SOIC (J, W)
Notes:
1.
Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2.
All linear dimensions are in inches and parenthetically in millimeters.
0.1497 (3.80)
0.1574 (4.00)
0.2284 (5.80)
0.2440 (6.20)
0.0532 (1.35)
0.0688 (1.75)
0.0040 (0.10)
0.0098 (0.25)
0.050 (1.27) BSC
0.013 (0.33)
0.020 (0.51)
0 --8
0.0075 (0.19)
0.0098 (0.25)
0.0099 (0.25)
0.0196 (0.50)
X 45
0.016 (0.40)
0.050 (1.27)
0.1890 (4.80)
0.1968 (5.00)
CAT24AC128
10
Doc. No. 1028, Rev. I
Note:
1.
All linear dimensions are in inches and parenthetically in millimeters.
0.205 (5.20)
0.213 (5.40)
0.303 (7.70)
0.318 (8.10)
4 REF
0.008 (0.20)
0.025 (0.65)
0.0137 (0.35)
0.0177 (0.45)
0.080 (2.03)
MAX
0.205 (5.15)
0.210 (5.35)
0.0267 (0.68)
0.0303 (0.77)
0.046 (1.17)
0.054 (1.37)
8-LEAD 210 MIL WIDE SOIC (K, X)
14-LEAD TSSOP (U14, Y14)
7.72 TYP
4.16 TYP
(1.78 TYP)
0.42 TYP
0.65 TYP
LAND PATTERN RECOMMENDATION
-B-
3.2
6.4
A
B
C
0.2
14
8
4.4 + 0.1
ALL LEAD TIPS
PIN #1 IDENT.
1
7
ALL LEAD TIPS
1.1 MAX TYP
0.1 C
(0.9)
0.10 + 0.05 TYP
0.19 - 0.30 TYP
0.3 M A B S C S
0.65 TYP
SEE DETAIL A
0.09 - 0.20 TYP
0.6+0.1
SEATING PLANE
GAGE PLANE
0.25
0
o
- 8
o
DETAIL A
-C-
-D-
Dimension D
Pkg
Min
Max
14
4.9
5.1
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Publication #:
1028
Revison:
I
Issue date:
06/23/05
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2
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REVISION HISTORY
Date
Rev.
Reason
07/7/2004
G
Added Die Revision to Ordering Information
Started revision history
07/27/2004
H
Updated DC Operating Characteristics table and notes
06/23/2005
I
Update Features
Update Pin Functions
Update Reliability Characteristics
Update D.C. Operating Characteristics
Update A.C. Characteristics
Update Read Operations
Update Figures 8, 9, 10
Add Figure 11
Update Ordering Information
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