1
CAT24C00
128-bit Serial EEPROM
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
PIN CONFIGURATION
BLOCK DIAGRAM
PIN FUNCTIONS
Pin Name
Function
SDA
Serial Data/Address
SCL
Serial Clock
NC
No Connect
V
CC
1.8 V to 5.5 V Power Supply
V
SS
Ground
DIP Package (P, L)
SOIC Package (J, W)
FEATURES
I
400 kHz I
2
C bus compatible*
I
1.8 to 5.5 volt operation
I
Low power CMOS technology
I
Self-timed write cycle with auto-clear
I
1,000,000 Program/erase cycles
I
100 year data retention
I
8-pin DIP, 8-pin SOIC, 8 pin TSSOP and SOT-23
I
Industrial and Extended Temperature Ranges
DESCRIPTION
The CAT24C00 is a 128-bit Serial CMOS EEPROM
internally organized as 16 words of 8 bits each. Catalyst's
advanced CMOS technology substantially reduces
device power requirements. The device operates via the
I
2
C bus serial interface and is available in 8-pin DIP,
8-pin SOIC, 8-pin TSSOP and 5-pin SOT-23.
2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
TSSOP Package (U, Y)
Doc. No. 1027, Rev. N
SOT-23 (TP, TB)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
NC
NC
NC
VSS
VCC
NC
SCL
SDA
NC
NC
NC
VSS
VCC
NC
SCL
SDA
8
7
6
5
1
2
3
4
NC
NC
NC
VSS
VCC
NC
SCL
SDA
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
STATE COUNTERS
E
2
PROM
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
VSS
SCL
SDA
SCL
VSS
SDA
VCC
NC
1
2
3
5
4
HA
LOGEN FREE
TM
LEAD FREE
CAT24C00
2
Doc. No. 1027, Rev. N
CAPACITANCE
T
A
= 25
C, f = 1.0 MHz, V
CC
= 5 V
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
C
I/O
(3)
Input/Output Capacitance (SDA)
V
I/O
= 0 V
8
pF
C
IN
(3)
Input Capacitance (SCL)
V
IN
= 0 V
6
pF
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
I
CC
Power Supply Current
f
SCL
= 400 kHz
2
mA
I
SB
(5)
Standby Current (V
CC
= 5.0 V)
V
IN
= GND or V
CC
1
A
I
LI
Input Leakage Current
V
IN
= GND to V
CC
10
A
I
LO
Output Leakage Current
V
OUT
= GND to V
CC
10
A
V
IL
Input Low Voltage
1
V
CC
x 0.3
V
V
IH
Input High Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output Low Voltage (V
CC
= 3.0 V)
I
OL
= 3 mA
0.4
V
V
OL2
Output Low Voltage (V
CC
= 1.8 V)
I
OL
= 1.5 mA
0.5
V
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Typ
Max
Units
N
END
(3)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
T
DR
(3)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
V
ZAP
(3)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
I
LTH
(3)(4)
Latch-up
JEDEC Standard 17
100
mA
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55
C to +125C
Storage Temperature ....................... 65
C to +150C
Voltage on Any Pin with
Respect to Ground
(1)
............ 2.0 V to V
CC
+ 2.0 V
V
CC
with Respect to Ground ............. 2.0 V to +7.0 V
Package Power Dissipation
Capability (T
A
= 25
C) .................................. 1.0 W
Lead Soldering Temperature (10 seconds) ...... 300
C
Output Short Circuit Current
(2)
....................... 100 mA
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Note:
(1) The minimum DC input voltage is 0.5 V. During transitions, inputs may undershoot to 2.0 V for periods of less than 20 ns. Maximum
DC voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1 V to V
CC
+ 1 V.
(5) Maximum standby current (I
SB
) = 10
A for the Extended Automotive temperature range.
CAT24C00
3
Doc. No. 1027, Rev. N
Write Cycle Limits
Symbol
Parameter
Min
Typ
Max
Units
t
WR
Write Cycle Time
5
ms
A.C. CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8 V - 6.0 V
2.5 V - 6.0 V
Min Max Min
Max
Units
F
SCL
Clock Frequency
100
400
kHz
T
I
(1)
Noise Suppression Time
100
100
ns
Constant at SCL, SDA Inputs
t
AA
SCL Low to SDA Data Out
3.5
1
s
and ACK Out
t
BUF
(1)
Time the Bus Must be Free Before
4.7
1.2
s
a New Transmission Can Start
t
HD:STA
Start Condition Hold Time
4
0.6
s
t
LOW
Clock Low Period
4.7
1.2
s
t
HIGH
Clock High Period
4
0.6
s
t
SU:STA
Start Condition Setup Time
4.7
0.6
s
(for a Repeated Start Condition)
t
HD:DAT
Data In Hold Time
0
0
ns
t
SU:DAT
Data In Setup Time
50
50
ns
t
R
(1)
SDA and SCL Rise Time
1
0.3
s
t
F
(1)
SDA and SCL Fall Time
300
300
ns
t
SU:STO
Stop Condition Setup Time
4
0.6
s
t
DH
Data Out Hold Time
100
100
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Power-Up Timing
(1)(2)
Symbol
Parameter
Min
Typ
Max
Units
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
1
ms
CAT24C00
4
Doc. No. 1027, Rev. N
FUNCTIONAL DESCRIPTION
The CAT24C00 supports the I
2
C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24C00 operates as
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated.
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT24C00 serial clock input pin is used to clock all
data transfers into or out of the device. This is an input
pin.
SDA:
Serial Data/Address
The CAT24C00 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
I
2
C BUS PROTOCOL
The following defines the features of the I
2
C bus protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
Figure 3. Start/Stop Timing
5020 FHD F05
5020 FHD F04
5020 FHD F03
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
START BIT
SDA
STOP BIT
SCL
CAT24C00
5
Doc. No. 1027, Rev. N
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24C00 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24C00 (see Fig. 5). The next three
significant bits are "don't care" bits. The last bit of the
slave address specifies whether a Read or Write operation
is to be performed. When this bit is set to 1, a Read
operation is selected, and when set to 0, a Write operation
is selected.
After the Master sends a START condition and the slave
address byte, the CAT24C00 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24C00 then performs a Read or Write operation
depending on the state of the R/
W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT24C00 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT24C00 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line
for an acknowledge. Once it receives this acknowledge,
the CAT24C00 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
WRITE OPERATION
Byte Write
In the Write mode, the Master device sends the START
condition and the slave address information (with the R/
W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends the byte
address that is to be written into the address pointer of
the CAT24C00. After receiving another acknowledge
from the Slave, the Master device transmits the data
byte to be written into the addressed memory location.
The CAT24C00 acknowledges once more and the
Master generates the STOP condition, at which time the
device begins its internal programming cycle to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request
from the Master device.
After a write command, the internal address counter
will continue to point to the same address location
that was just written. If a stop bit is transmitted to the
device at any point in the write sequence before the
entire sequence is complete, then the command will
abort and no data will be written. If more than eight
Figure 4. Acknowledge Timing
5020 FHD F06
ACKNOWLEDGE
1
START
SCL FROM
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
CAT24C00
6
Doc. No. 1027, Rev. N
bits are transmitted before the stop bit is sent, then
the device will clear the previously loaded byte and
begin loading the data buffer again. If more than one
data byte is transmitted to the device and a stop bit
is sent before a full eight bits of data have been
transmitted, then the write command will abort and
no data will be written.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host's write operation,
the CAT24C00 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24C00 is still busy with
the write operation, no ACK will be returned. If the
CAT24C00 has completed the write operation, an ACK
will be returned and the host can then proceed with the
next read or write operation.
READ OPERATIONS
The READ operation for the CAT24C00 is initiated in the
same manner as the write operation with the one
exception that the R/
W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
The device's address counter contains the address of
the last byte accessed, incremented by one. In other
words, if the last READ access was to address N, the
READ immediately following would access data from
address N+1. If N=15, then the counter will 'wrap around'
to address 0 and continue to clock out data.
Figure 5. Slave Address Bits
1
0
1
0
X X X
R/W
CAT24C00
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a `dummy'
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24C00 acknowledges the word
address, the Master device resends the START condition
and the slave address, this time with the R/
W bit is set to
one. The CAT24C00 then responds with its acknowledge
and sends the 8-bit byte requested. To end the Read
Operation the master device does not send an
acknowledge but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the immediate Address READ or Selective READ
operations. After the CAT24C00 sends initial 8-bit byte
requested, the Master will respond with an acknowledge
which tells the device it requires more data. The
CAT24C00 will continue to output an 8-bit byte for each
acknowledge sent by the Master. The operation is
terminated when the Master fails to respond with an
acknowledge, thus sending the STOP condition.
The data being transmitted from the CAT24C00 is
outputted sequentially with data from address N followed
by data from address N+1. The READ operation address
counter increments all of the CAT24C00 address bits so
that the entire memory array can be read during one
operation. If more than 16 bytes are read out, the counter
will "wrap around" and continue to clock out data bytes.
CAT24C00
7
Doc. No. 1027, Rev. N
Figure 6. Byte Write Timing
BYTE
ADDRESS
SLAVE
ADDRESS
S
A
C
K
A
C
K
DATA
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
Figure 7. Immediate Address Read Timing
Figure 9. Sequential Read Timing
Figure 8. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+x
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BYTE
ADDRESS (n)
S
A
C
K
DATA n
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
SDA LINE S
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE
ADDRESS
DATA
A
C
K
S
T
O
P
P
N
O
A
C
K
CAT24C00
8
Doc. No. 1027, Rev. N
Notes:
(1) The device used in the above example is a CAT24C00JI-TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage,
Tape & Reel)
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWB). For additional
information, please contact your Catalyst sales office.
ORDERING INFORMATION
Prefix
Device #
Suffix
24C00
J
I
TE13
Product Number
24C00: 128 Bit
Tape & Reel
TE13: 2000/Reel
Package
P: PDIP
J : SOIC (JEDEC)
U: TSSOP
Operating Voltage
Blank: 1.8 V - 5.5 V
X
CAT
Temperature Range
I = Industrial (-40 to 85 C)
Optional
Company ID
TP: SOT23
L : PDIP (Lead free, Halogen free)
TB: SOT23 (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
E = Extended (-40 to 125 C)
Rev B
(2)
Die Revision
CAT24C00
9
Doc. No. 1027, Rev. N
REVISION HISTORY
Date
Rev.
Reason
9/24/2003
H
Eliminated commercial temperature range class
Updated marking
10/30/2003
I
Eliminated automotive temperature reange
12/9/2003
J
Changed Industrial temp range designation from
"Blank" to "I"
12/23/2003
K
Eliminatd Commercial and Automotive temp ranges
from Features on front page of data sheet
12/29/2003
L
Moved DC Operating Characteristics typ numbers
for VOL1 and VOL2 to max column
Changed 1.8V to 1.8V - 6.0V for AC Characteristics
Changed 4.5V - 5.5V to 2.5V - 6.0V for AC
Characteristics
7/7/2004
M
Added Die Revision to Ordering Information
7/27/2004
N
Updated DC Operating Characteristics chart and
notes
CAT24C00
10
Doc. No. 1027, Rev. N
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP TM
AE
2
TM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Publication #:
1027
Revison:
N
Issue date:
7/27/04
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