1
24C1601 BLOCK
CAT24C163(16K), CAT24C083(8K)
CAT24C043(4K), CAT24C023(2K)
Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer
DESCRIPTION
The CAT24CXX3 is a single chip solution to three
popular functions of EEPROM memory, precision reset
controller and watchdog timer. The 24C163(16K),
24C083(8K), 24C043(4K) and 24C023(2K) feature a I
2
C
Serial CMOS EEPROM Catalyst advanced CMOS tech-
nology substantially reduces device power requirements.
The 24CXX3 features a 16-byte page and is available in
8-pin DIP or 8-pin SOIC packages.
The reset function of the 24CXX3 protects the system
during brown out and power up/down conditions. During
system failure the watchdog timer feature protects the
microcontroller with a reset signal. 24CXX3 features
active low reset on pin 2 and active high reset on pin 7.
24CXX3 features watchdog timer on the WDI input pin
(pin 1).
Pin Name
Function
SDA
Serial Data/Address
RESET/
RESET
Reset I/O
SCL
Clock Input
Vcc
Power Supply
V
SS
Ground
WDI
Watchdog Timer Input
WP
Write Protect
PIN FUNCTIONS
PIN CONFIGURATION
24CXX3
BLOCK DIAGRAM
*All products offered in P and J packages
Advanced
FEATURES
s
Watchdog Timer Input (WDI)
s
Programmable Reset Threshold
s
400 KHz I2C Bus Compatible
s
2.7 to 6 Volt Operation
s
Low Power CMOS Technology
s
16 - Byte Page Write Buffer
s
Built-in inadvertent write protection
--
V
CC
Lock Out
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
E
2
PROM
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
VSS
WP
SDA
RESET Controller
High
Precision
Vcc Monitor
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
WDI RESET/
RESET
WATCHDOG
1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
s
Active High or Low Reset Outputs
-- Precision Power Supply Voltage Monitoring
--
5V, 3.3V and 3V options
s
1,000,000 Program/Erase Cycles
s
100 Year Data Retention
s
8-Pin DIP or 8-Pin SOIC
s
Commercial, Industrial and Automotive
Temperature Ranges
WDI
VCC
RESET
SCL
SDA
RESET
WP
VSS
Doc. No. 25080-00 3/98 M-1
CAT24C163/083/043/023
2
Advanced
Doc. No. 25080-00 3/98 M-1
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias....................55
C to +125
C
Storage Temperature........................ 65
C to +150
C
Voltage on Any Pin with
Respect to Ground
(1)
..............2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground..................2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25
C)1.0W.................................1.0W
Lead Soldering Temperature (10 secs)...............300
C
Output Short Circuit Current
(2)
..........................100mA
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol Parameter
Min.
Max. Units Reference Test Method
N
END
(3)
Endurance 1,000,000 Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR
(3)
Data Retention 100 Years
MIL-STD-883, Test Method 1008
V
ZAP
(3)
ESD Susceptibility 2000 Volts
MIL-STD-883, Test Method 3015
I
LTH
(3)(4)
Latch-up 100 mA
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.7V to +6.0V, unless otherwise specified.
Symbol Parameter Min. Typ. Max.
Units Test Conditions
I
CC
Power Supply Current
3
mA f
SCL
= 100 KHz
Isb
Standby Current
40
A
Vcc=3.3V
50
A Vcc=5
I
LI
Input Leakage Current
2
A V
IN
=G
ND
or V
CC
I
LO
Output Leakage Current
10
A V
IN
=G
ND
or V
CC
V
IL
Input Low Voltage 1 V
CC
x 0.3 V
V
IH
Input High Voltage
V
CC
x 0.7 V
CC
+ 0.5 V
V
OL
Output Low Voltage (SDA)
0.4 V I
OL
= 3 mA, V
CC
= 3.0V
Limits
CAPACITANCE T
A
= 25
C, f = 1.0 MHz, V
CC
= 5V
Symbol Test
Max.
Units
Conditions
C
I/O
(3)
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
(3)
Input Capacitance (SCL)
6
pF
V
IN
= 0V
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V
CC
+1V.
CAT24C163/083/043/023
3
Advanced
Doc. No. 25080-00 3/98 M-1
A.C. CHARACTERISTICS
V
CC
=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
V
CC
=2.7V - 6V
V
CC
=4.5V - 5.5V
Min.
Max.
Min.
Max.
Units
F
SCL
Clock Frequency
100
400
kHz
T
I
(1)
Noise Suppression Time
200
200
ns
Constant at SCL, SDA Inputs
t
AA
SCL Low to SDA Data Out
3.5
1
s
and ACK Out
t
BUF
(1)
Time the Bus Must be Free Before
4.7
1.2
s
a New Transmission Can Start
t
HD:STA
Start Condition Hold Time
4
0.6
s
t
LOW
Clock Low Period
4.7
1.2
s
t
HIGH
Clock High Period
4
0.6
s
t
SU:STA
Start Condition Setup Time
4.7
0.6
s
(for a Repeated Start Condition)
t
HD:DAT
Data In Hold Time
0
0
ns
t
SU:DAT
Data In Setup Time
50
50
ns
t
R
(1)
SDA and SCL Rise Time
1
0.3
s
t
F
(1)
SDA and SCL Fall Time
300
300
ns
t
SU:STO
Stop Condition Setup Time
4
0.6
s
t
DH
Data Out Hold Time
100
100
ns
Power-Up Timing
(1)(2)
Symbol
Parameter
Max.
Units
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Write Cycle Limits
Symbol
Parameter
Min.
Typ.
Max
Units
t
WR
Write Cycle Time
10
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
CAT24C163/083/043/023
4
Advanced
Doc. No. 25080-00 3/98 M-1
RESET CIRCUIT CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
t
GLITCH
Glitch Reject Pulse Width
100
ns
V
RT
Reset Threshold Hystersis
15
mV
V
OLRS
Reset Output Low Voltage (I
OLRS
=1mA)
0.4
V
V
OHRS
Reset Output High Voltage
Vcc-0.75
V
Reset Threshold (Vcc=5V)
4.50
4.75
(24CXXX-45)
Reset Threshold (Vcc=5V)
4.25
4.50
(24CXXX-42)
Reset Threshold (Vcc=3.3V)
3.00
3.15
(24CXXX-30)
Reset Threshold (Vcc=3.3V)
2.85
3.00
(24CXXX-28)
Reset Threshold (Vcc=3V)
2.55
2.70
(24CXXX-25)
t
PURST
Power-Up Reset Timeout
130
270
ms
t
RPD
V
TH
to RESET Output Delay
5
s
V
RVALID
RESET Output Valid
1
V
V
V
TH
CAT24C163/083/043/023
5
Advanced
Doc. No. 25080-00 3/98 M-1
PIN DESCRIPTIONS
WDI: WATCHDOG INPUT
If there is no transition on the WDI for more than 1.6
seconds, the watchdog timer times out.
WP: WRITE PROTECT
If the pin is tied to V
CC
the entire memory array becomes
Write Protected (READ only). When the pin is tied to V
SS
or left floating normal read/write operations are allowed
to the device.
SCL: SERIAL CLOCK
The serial clock input clocks all data transferred into or
out of the device.
RESET/
RESET
RESET
RESET
RESET
RESET
: RESET I/O
These are open drain pins and can be used as reset
trigger inputs. By forcing a reset condition on the pins the
device will initiate and maintain a reset condition for
approximately 200ms. RESET pin must be connected
through a pull-down and
RESET
pin must be connected
through a pull-up device.
SDA: SERIAL DATA/ADDRESS
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
Reset Controller Description
The CAT24CXXX provides a precision RESET control-
ler that ensures correct system operation during brown-
out and power up/down conditions. It is configured
Figure 1. RESET Output Timing
with open drain RESET outputs. During power-up, the
RESET outputs remain active until V
CC
reaches the
V
TH
threshold and will continue driving the outputs for
approximately 200ms (t
PURST
) after reaching V
TH.
After
the t
PURST
timeout interval, the device will cease to drive
reset outputs. At this point the reset outputs will be pulled
up or down by their respective pull up/pull down devices.
During power-down, the RESET outputs will begin driv-
ing active when V
CC
falls below V
TH.
The RESET
outputs will be valid so long as V
CC
is >1.0V (V
RVALID
).
The RESET pins are I/Os; therefore, the CAT24CXXX
can act as a signal conditioning circuit for an externally
applied reset. The inputs are level triggered; that is, the
RESET input in the 24CXXX will initiate a reset timeout
after detecting a high and the
RESET
input in the
24CXXX will initiate a reset timeout after detecting a low.
Watchdog Timer
The Watchdog Timer provides an independent protec-
tion for microcontrollers. During a system failure, the
CAT24CXXX will respond with a reset signal after a
time-out interval of 1.6 seconds for a lack of activity. The
24CXX3 is designed with a WDI input pin for the Watch-
dog Timer function. For the 24CXX3, if the microcontroller
does not toggle the WDI input pin within 1.6 seconds, the
Watchdog Timer times out. This will generate a reset
condition on reset outputs. The Watchdog Timer is
cleared by any transition on WDI.
As long as the reset signal is asserted, the Watchdog
Timer will not count and will stay cleared.
DEVICE OPERATION
GLITCH
t
V
CC
PURST
t
PURST
t
RPD
t
RVALID
V
V
TH
RESET
RESET
RPD
t
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