www.docs.chipfind.ru
1
2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
Doc. No. 1073, Rev. D
HA
LOGEN FREE
TM
LEAD FREE
CAT24FC01
1-kb I
2
C Serial EEPROM
* Catalyst Semiconductor is licensed by Philips Corporation to carry
the I
2
C Bus Protocol.
PIN CONFIGURATION
BLOCK DIAGRAM
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
V
CC
1.8 V to 5.5 V Power Supply
V
SS
Ground
DIP Package (P, L)
TSSOP Package (U, Y)
SOIC Package (J, W)
FEATURES
I
400 kHz (2.5 V) and 100 kHz (1.8 V) I
2
C bus
compatible
I
1.8 to 5.5 volt operation
I
Low power CMOS technology
I
16-byte page write buffer
I
Industrial and extended temperature ranges
I
Self-timed write cycle with auto-clear
I
1,000,000 program/erase cycles
I
100 year data retention
I
8-pin DIP, 8-pin SOIC, 8-pin TSSOP and MSOP
packages
- "Green" package option available
I
256 x 8 memory organization
I
Hardware write protect
DESCRIPTION
The CAT24FC01 is a 1-kb Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. Catalyst's
advanced CMOS technology substantially reduces
device power requirements.
The CAT24FC01 features a 16-byte page write buffer.
The device operates via the I
2
C bus serial interface and
is available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and
MSOP packages.
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
E
2
PROM
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
VSS
SCL
A0
A1
A2
SDA
WP
MSOP Package (R, Z)
1
2
3
4
8
7
6
5
A0
A1
A2
VSS
VCC
WP
SCL
SDA
A2
A0
A1
VSS
A0
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A1
A2
VSS
VCC
WP
SCL
SDA
8
7
6
5
VCC
WP
SCL
SDA
A2
A0
A1
VSS
1
2
3
4
CAT24FC01
2
Doc. No. 1073, Rev. D
CAPACITANCE T
A
= 25
C, f = 400 kHz, V
CC
= 5 V
Symbol
Test
Conditions
Min
Typ
Max
Units
C
I/O
(3)
Input/Output Capacitance (SDA)
V
I/O
= 0 V
8
pF
C
IN
(3)
Input Capacitance (other pins)
V
IN
= 0 V
6
pF
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Typ
Max
Units
N
END
(3)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
T
DR
(3)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
V
ZAP
(3)
ESD Susceptibility
MIL-STD-883, Test Method 3015
4000
Volts
I
LTH
(3)(4)
Latch-up
JEDEC Standard 17
100
mA
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
55
C to +125C
Storage Temperature ....................... 65
C to +150C
Voltage on Any Pin with
Respect to Ground
(1)
............ 2.0 V to V
CC
+ 2.0 V
V
CC
with Respect to Ground ............. 2.0 V to +7.0 V
Package Power Dissipation
Capability (T
A
= 25
C) .................................. 1.0 W
Note:
(1) The minimum DC input voltage is 0.5 V. During transitions, inputs may undershoot to 2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1.0 V to V
CC
+ 1.0 V.
(5) Maximum standby current (I
SB
) = 10
A for the Extended Automotive temperature range.
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
I
CC
Power Supply Current (Read)
f
SCL
= 100 kHz
1
mA
I
CC
Power Supply Current (Write)
f
SCL
= 100 kHz
3
mA
I
SB
(5)
Standby Current (V
CC
= 5.0 V)
V
IN
= GND or V
CC
1
A
I
LI
Input Leakage Current
V
IN
= GND to V
CC
1
A
I
LO
Output Leakage Current
V
OUT
= GND to V
CC
1
A
V
IL
Input Low Voltage
1
V
CC
x 0.3
V
V
IH
Input High Voltage
V
CC
x 0.7
V
CC
+ 1.0
V
V
OL1
Output Low Voltage (V
CC
= 3.0 V)
I
OL
= 3 mA
0.4
V
V
OL2
Output Low Voltage (V
CC
= 1.8 V)
I
OL
= 1.5 mA
0.5
V
Lead Soldering Temperature (10 seconds) ...... 300
C
Output Short Circuit Current
(2)
....................... 100 mA
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
CAT24FC01
3
Doc No. 1073, Rev. D
Write Cycle Limits
Symbol
Parameter
MinTyp
Max
Un
its
t
WR
Write Cycle Time
5
ms
A.C. CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8 V - 5.5 V
2.5 V - 5.5 V
MinMax
Min Max
Un
its
F
SCL
Clock Frequency
0
100
0
400
kHz
T
I
(1)
Noise Suppression Time
100
100
ns
Constant at SCL, SDA Inputs
t
AA
SCL Low to SDA Data Out
3.5
0.9
s
and ACK Out
t
BUF
(1)
Time the Bus Must be Free Before
4.7
1.3
s
a New Transmission Can Start
t
HD:STA
Start Condition Hold Time
4
0.6
s
t
LOW
Clock Low Period
4.7
1.3
s
t
HIGH
Clock High Period
4
0.6
s
t
SU:STA
Start Condition Setup Time
4.7
0.6
s
(for a Repeated Start Condition)
t
HD:DAT
Data In Hold Time
0
0
ns
t
SU:DAT
Data In Setup Time
250
100
ns
t
R
(1)
SDA and SCL Rise Time
1
0.3
s
t
F
(1)
SDA and SCL Fall Time
300
300
ns
t
SU:STO
Stop Condition Setup Time
4
0.6
s
t
DH
Data Out Hold Time
100
100
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Power-Up Timing
(1)(2)
Symbol
Parameter
MinTyp
Max
Un
its
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
1
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
CAT24FC01
4
Doc. No. 1073, Rev. D
FUNCTIONAL DESCRIPTION
The CAT24FC01 supports the I
2
C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24FC01 operates as
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated. A maximum of
8 devices may be connected to the bus as determined by
the device address inputs A0, A1, and A2.
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT24FC01 serial clock input pin is used to clock all
data transfers into or out of the device. This is an input pin.
SDA: Serial Data/Address
The CAT24FC01 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading multiple
devices. A maximum of eight devices can be cascaded
when using the device.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT24FC01 when this pin is tied
to V
CC
, the entire array of memory is write protected.
When left floating, memory is unprotected.
Figure 3. Start/Stop Timing
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
START BIT
SDA
STOP BIT
SCL
CAT24FC01
5
Doc No. 1073, Rev. D
I
2
C BUS PROTOCOL
The following defines the features of the I
2
C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC01 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 for the CAT24FC01 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits
and define which device the Master is accessing. Up to
eight CAT24FC01 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24FC01 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC01 then performs a Read or a Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24FC01 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
When the CAT24FC01 begins a READ mode, it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24FC01 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Figure 4. Acknowledge Timing
Figure 5. Slave Address Bits
1
DEVICE ADDRESS
0
1
0
A2
A1
A0
R/W
Normal Read and Write
ACKNOWLEDGE
1
START
SCL FROM
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
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