2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
CAT24FC17
16-kb I
2
C Serial EEPROM
Doc. No. 1077, Rev. F
* Catalyst Semiconductor is licensed by Philips Corporation
to carry the I
2
C Bus Protocol.
PIN CONFIGURATION
BLOCK DIAGRAM
PIN FUNCTIONS
Pin Name
Function
NC
No Connect
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
V
CC
2.5 V to 5.5 V Power Supply
V
SS
Ground
DIP Package (P, L, GL)
TSSOP Package (U, Y, GY)
SOIC Package (J, W, GW)
FEATURES
I
400 kHz (2.5 V) I
2
C bus compatible
I
2.5 to 5.5 volt operation
I
Low power CMOS technology
I
16-byte page write buffer
I
Industrial and extended temperature ranges
I
Self-timed write cycle with auto-clear
I
1,000,000 program/erase cycles
I
100 year data retention
I
8-pin DIP, 8-pin SOIC, 8-pin TSSOP, 8-pin MSOP
and TDFN packages
- "Green" package option available
I
256 x 8 Memory organization
I
Hardware write protect
- Top 1/2 array protected when WP at V
IH
DESCRIPTION
The CAT24FC17 is a 16-kb Serial CMOS EEPROM
internally organized as 2048 words of 8 bits each.
Catalyst's advanced CMOS technology substantially
reduces device power requirements. The CAT24FC17
features a 16-byte page write buffer. The device operates
via the I
2
C bus serial interface has a special write
protection feature and is available in 8-pin DIP, SOIC,
TSSOP, MSOP and TDFN packages.
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
STATE COUNTERS
E
2
PROM
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
VSS
SCL
SDA
WP
TDFN Package
(RD4, ZD4, GD4)
8
7
6
5
1
2
3
4
NC
NC
NC
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
NC
NC
NC
VSS
VCC
WP
SCL
SDA
MSOP Package (R, Z, GZ)
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
NC
NC
NC
VSS
NC
NC
NC
VSS
8
7
6
5
VCC
WP
SCL
SDA
1
2
3
4
NC
NC
NC
VSS
CAT24FC17
2
Doc. No. 1077, Rev. F
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAPACITANCE T
A
= 25
C, f = 400 kHz, V
CC
= 5 V
Symbol
Test
Conditions
Min
Typ
Max
Units
C
I/O
(3)
Input/Output Capacitance (SDA)
V
I/O
= 0 V
8
pF
C
IN
(3)
Input Capacitance (other pins)
V
IN
= 0 V
6
pF
RELIABILITY CHARACTERISTICS
(3)
Symbol
Parameter
Min
Typ
Max
Units
N
END
Endurance
1,000,000
Cycles/Byte
T
DR
Data Retention
100
Years
V
ZAP
ESD Susceptibility
4000
Volts
I
LTH
(4)
Latch-up
100
mA
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
55
C to +125C
Storage Temperature ....................... 65
C to +150C
Voltage on Any Pin with
Respect to Ground
(1)
............ 2.0 V to V
CC
+ 2.0 V
V
CC
with Respect to Ground ............. 2.0 V to +7.0 V
Package Power Dissipation
Capability (T
A
= 25
C) .................................. 1.0 W
Note:
(1) The minimum DC input voltage is 0.5 V. During transitions, inputs may undershoot to 2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according tp appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1.0 V to V
CC
+ 1.0 V.
(5) Maximum standby current (I
SB
) = 10
A for the Extended Automotive temperature range.
D.C. OPERATING CHARACTERISTICS
V
CC
= 2.5 V to 5.5 V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
I
CC
Power Supply Current (Read)
f
SCL
= 400 kHz
1
mA
I
CC
Power Supply Current (Write)
f
SCL
= 400 kHz
3
mA
I
SB
(5)
Standby Current (V
CC
= 5.0 V)
V
IN
= GND or V
CC
1
A
I
LI
Input Leakage Current
V
IN
= GND to V
CC
1
A
I
LO
Output Leakage Current
V
OUT
= GND to V
CC
1
A
V
IL
Input Low Voltage
1
V
CC
x 0.3
V
V
IH
Input High Voltage
V
CC
x 0.7
V
CC
+ 1.0
V
V
OL
Output Low Voltage (V
CC
= 3.0 V)
I
OL
= 3 mA
0.4
V
Lead Soldering Temperature (10 seconds) ...... 300
C
Output Short Circuit Current
(2)
....................... 100 mA
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
CAT24FC17
3
Doc No. 1077, Rev. F
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Write Cycle Limits
Symbol
Parameter
Min
Typ
Max
Units
t
WR
Write Cycle Time
5
ms
A.C. CHARACTERISTICS
V
CC
= 2.5 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
2.5 V - 5.5 V
Min
Max
Units
F
SCL
Clock Frequenc
400
kHz
T
I
(1)
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
t
AA
SCL Low to SDA Data Out and ACK Out
900
ns
t
BUF
(1)
Time the Bus Must be Free Before a New Transmission
1300
ns
Can Start
t
HD:STA
Start Condition Hold Time
600
ns
t
LOW
Clock Low Period
1300
ns
t
HIGH
Clock High Period
600
ns
t
SU:STA
Start Condition Setup Time
600
ns
(for a Repeated Start Condition)
t
HD:DAT
Data In Hold Time
0
ns
t
SU:DAT
Data In Setup Time
100
ns
t
R
(1)
SDA and SCL Rise Time
300
ns
t
F
(1)
SDA and SCL Fall Time
300
ns
t
SU:STO
Stop Condition Setup Time
600
ns
t
DH
Data Out Hold Time
100
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Power-Up Timing
(1)(2)
Symbol
Parameter
Min
Typ
Max
Units
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
1
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
CAT24FC17
4
Doc. No. 1077, Rev. F
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FUNCTIONAL DESCRIPTION
The CAT24FC17 supports the I
2
C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24FC17 operates as
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated.
START BIT
SDA
STOP BIT
SCL
Figure 3. Start/Stop Timing
Figure 2. Write Cycle Timing
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
Figure 1. Bus Timing
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT24FC17 serial clock input pin is used to clock all
data transfers into or out of the device. This is an input
pin.
SDA: Serial Data/Address
The CAT24FC17 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to V
CC
, the
upper half of the memory array is write protected. When
left floating or tied to V
SS,
normal read/write operations
are allowed.
CAT24FC17
5
Doc No. 1077, Rev. F
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
I
2
C BUS PROTOCOL
The following defines the features of the I
2
C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC17 monitor the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 for the CAT24FC17 (see Fig. 5). The next three
significant bits (A10, A9, A8) are the memory array
address bits. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24FC17 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC17 then performs a Read or a Write operation
depending on the state of the R/
W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24FC17 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
When the CAT24FC17 begins a READ mode, it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24FC17 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Figure 4. Acknowledge Timing
Figure 5. Slave Address Bits
ACKNOWLEDGE
1
START
SCL FROM
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
1
DEVICE ADDRESS
0
1
0
A10
A9
A8
R/W
Normal Read and Write
CAT24FC17
6
Doc. No. 1077, Rev. F
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/
W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24FC17. After receiving another
acknowledge from the Slave, the Master device transmits
the data byte to be written into the addressed memory
location. The CAT24FC17 acknowledges once more
and the Master generates the STOP condition, at which
time the device begins its internal programming to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24FC17 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT24FC17 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter `wraps
around', and previously transmitted data will be
overwritten.
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24FC17 in a single write cycle.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host's write operation,
the CAT24FC17 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24FC17 is still busy with
the write operation, no ACK will be returned. If the
CAT24FC17 has completed the write operation, an ACK
will be returned and the host can then proceed with the
next read or write operation.
WRITE PROTECTION
The CAT24FC17 is designed with a hardware protect
pin that enables the user to protect the upper half of the
memory. The hardware protection feature of the
CAT24FC17 is designed into the part to provide added
flexibility to the design engineers. The write protection
feature of CAT24FC17 allows the user to protect against
inadvertent programming of memory locations 400 H to
7 FFH. If the WP pin is tied to Vcc, the upper half of the
memory array is protected and becomes read only. If the
WP pin is left floating or tied to Vss, the device can be
written into.
Figure 7. Page Write Timing
BYTE
ADDRESS
SLAVE
ADDRESS
S
A
C
K
A
C
K
DATA
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+P
BYTE
ADDRESS (n)
A
C
K
A
C
K
DATA n
A
C
K
S
T
O
P
S
A
C
K
DATA n+1
A
C
K
S
T
A
R
T
P
SLAVE
ADDRESS
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
*
Figure 6. Byte Write Timing
CAT24FC17
7
Doc No. 1077, Rev. F
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
READ OPERATIONS
The READ operation for the CAT24FC17 is initiated in
the same manner as the write operation with the one
exception that the R/
W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
The CAT24FC17's address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to address
N, the READ immediately following would access data
from address N + 1. If N = 2047 for 24FC17, then the
counter will `wrap around' to address 0 and continue to
clock out data. After the CAT24FC17 receives its slave
address information (with the R/
W bit set to one), it
issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a `dummy'
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24FC17 acknowledge the word
address, the Master device resends the START condition
and the slave address, this time with the R/
W bit set to
one. The CAT24FC17 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24FC17 sends the initial 8-bit
data requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24FC17 will continue to output a byte for
each acknowledge sent by the Master. The operation
will terminate operation when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from the CAT24FC17 is
outputted sequentially with data from address N followed
by data from address N + 1. The READ operation
address counter increments all of the CAT24FC17
address bits so that the entire memory array can be read
during one operation. If more than the 2047 bytes are
read out, the counter will "wrap around" and continue to
clock out data bytes.
Figure 8. Immediate Address Read Timing
SCL
8
9
SDA
8TH BIT
STOP
NO ACK
DATA OUT
SLAVE
ADDRESS
S
A
C
K
DATA
N
O
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
CAT24FC17
8
Doc. No. 1077, Rev. F
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 9. Selective Read Timing
Figure 10. Sequential Read Timing
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BYTE
ADDRESS (n)
S
A
C
K
DATA n
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+x
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
CAT24FC17
9
Doc No. 1077, Rev. F
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a 24FC17JI-TE13 REV-F (SOIC, Industrial Temperature, 2.5 Volt to 5.5 Volt Operating
Voltage, Tape & Reel).
Prefix
Device #
Suffix
24FC17
J
I
Product
Number
Package
CAT
Temperature Range
I = Indust ri
Optional
Company ID
P: PDIP
J: SOIC, JEDEC
R: MSOP
U: TSSOP
RD4: TDFN
L: PDIP (Lead-free, Halogen-free)
W: SOIC, JEDEC (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
Z: MSOP (Lead-free, Halogen-free)
ZD4: TDFN (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GZ: MSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GD4: TDFN (Lead-free, Halogen-free, NiPdAu lead plating)
TE13
Tape & Reel
REV-F
Die Revision
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.caalyst-semiconductor.com
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP TM
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2
TM
MiniPotTM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Publication #:
1077
Revison:
F
Issue date:
08/02/05
REVISION HISTORY
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