2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
CAT24FC65, CAT24FC66
64K-Bit I
2
C Serial CMOS EEPROM with Partial Array Write Protection
Doc. No. 1047, Rev. H
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
V
CC
+2.5V to +5.5V Power Supply
V
SS
Ground
NC
No Connect
DESCRIPTION
The CAT24FC65/66 is a 64k-bit Serial CMOS EEPROM
internally organized as 8,192 words of 8 bits each.
Catalyst's advanced CMOS technology substantially
reduces device power requirements.
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
The CAT24FC65/66 features a 64-byte page write
buffer. The device operates via the I
2
C bus serial
interface and is available in 8-pin DIP, SOIC, TSSOP
and TDFN packages.
PIN CONFIGURATION
BLOCK DIAGRAM
I
Fast mode I
2
C bus compatible*
I
Max clock frequency:
- 400KHz for VCC=2.5V to 5.5V
I
Schmitt trigger filtered inputs for
noise suppression
I
Low power CMOS technology
I
64-byte page write buffer
I
Self-timed write cycle with auto-clear
I
Industrial and automotive temperature ranges
FEATURES
DIP Package (P, L, GL)
I
5 ms max write cycle time
I
Write protect feature
Bottom 1/4 array protected when WP at V
IH
(CAT24FC65)
Top 1/4 array protected when WP at V
IH
(CAT24FC66)
I
1,000,000 program/erase cycles
I
100 year data retention
I
8-pin DIP, 8-pin SOIC (JEDEC), 8-pin SOIC
(EIAJ), 8-pin TSSOP and TDFN packages
TDFN Package (RD2, ZD2)
1
2
3
4
8
7
6
5
A0
A1
A2
VSS
VCC
WP
SCL
SDA
(Top View)
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
EEPROM
128X512
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
VSS
WP
SCL
SDA
128
512
A0
A1
A2
A1
A2
VSS
A1
A2
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A0
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
VSS
A0
A1
A2
A0
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
VSS
TSSOP Package (U, Y, GY)
SOIC Package
(J, W, K, X, GW, GX)
CAT24FC65/66
2
Doc. No. 1047, Rev. H
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55
C to +125C
Storage Temperature ....................... 65
C to +150C
Voltage on Any Pin with
Respect to Ground
(1)
........... 2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... 2.0V to +7.0V
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V
CC
+1V.
(5) Standby current (I
SB
) = 10
A max at extended temperature range.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
I
CC1
Power Supply Current - Read
f
SCL
= 400 KHz
400
A
V
CC
=5V
I
CC2
Power Supply Current - Write
f
SCL
= 400KHz
3
mA
V
CC
=5V
I
SB
(5)
Standby Current
V
IN
= GND or V
CC
1
A
V
CC
=5V
I
LI
Input Leakage Current
V
IN
= GND to V
CC
1
A
I
LO
Output Leakage Current
V
OUT
= GND to V
CC
1
A
V
IL
Input Low Voltage
-0.5
V
CC
x 0.3
V
V
IH
Input High Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output Low Voltage (V
CC
= +3.0V)
I
OL
= 3.0 mA
0.4
V
RELIABILITY CHARACTERISTICS
(3)
Symbol
Parameter
Min
Typ
Max
Units
N
END
Endurance
1,000,000
Cycles/Byte
T
DR
Data Retention
100
Years
V
ZAP
ESD Susceptibility
4000
Volts
I
LTH
(4)
Latch-up
100
mA
CAPACITANCE T
A
= 25
C, f = 1.0 MHz, V
CC
= 5V
Symbol
Test
Conditions
Min
Typ
Max
Units
C
I/O
(3)
Input/Output Capacitance (SDA)
V
I/O
= 0V
8
pF
C
IN
(3)
Input Capacitance (SCL, WP, A0, A1)
V
IN
= 0V
6
pF
Z
WPL
WP Input Impedance
V
IN
0.5V
5
70
k
Z
WPH
WP Input Impedance
V
IN
>0.7VxV
CC
500
k
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +5.5V, unless otherwise specified.
Package Power Dissipation
Capability (Ta = 25
C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(2)
........................ 100mA
CAT24FC65/66
3
Doc No. 1047, Rev. H
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Note:
(1) AC measurement conditions:
RL (connects to V
CC
): 0.3V
CC
to 0.7 V
CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V
CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
A.C. CHARACTERISTICS
V
CC
= +2.5V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Power-Up Timing
(2)(3)
Symbol
Parameter
Min
Typ
Max
Units
t
PUR
Power-Up to Read Operation
1
ms
t
PUW
Power-Up to Write Operation
1
ms
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
V
5
.
5
-
V
5
.
2
=
C
C
V
n
i
M
x
a
M
s
t
i
n
U
F
L
C
S
y
c
n
e
u
q
e
r
F
k
c
o
l
C
0
0
4
z
H
k
t
A
A
t
u
O
K
C
A
d
n
a
t
u
O
a
t
a
D
A
D
S
o
t
w
o
L
L
C
S
0
5
0
0
9
s
n
t
F
U
B
)
2
(
n
o
i
s
s
i
m
s
n
a
r
T
w
e
N
a
e
r
o
f
e
B
e
e
r
F
e
b
t
s
u
M
s
u
B
e
h
t
e
m
i
T
t
r
a
t
S
n
a
C
0
0
3
1
s
n
t
A
T
S
:
D
H
e
m
i
T
d
l
o
H
n
o
i
t
i
d
n
o
C
t
r
a
t
S
0
0
6
s
n
t
W
O
L
d
o
i
r
e
P
w
o
L
k
c
o
l
C
0
0
3
1
s
n
t
H
G
I
H
d
o
i
r
e
P
h
g
i
H
k
c
o
l
C
0
0
6
s
n
t
A
T
S
:
U
S
)
n
o
i
t
i
d
n
o
C
t
r
a
t
S
d
e
t
a
e
p
e
R
a
r
o
f
(
e
m
i
T
p
u
t
e
S
n
o
i
t
i
d
n
o
C
t
r
a
t
S
0
0
6
s
n
t
T
A
D
:
D
H
e
m
i
T
d
l
o
H
n
I
a
t
a
D
0
s
n
t
T
A
D
:
U
S
e
m
i
T
p
u
t
e
S
n
I
a
t
a
D
0
0
1
s
n
t
R
)
2
(
e
m
i
T
e
s
i
R
L
C
S
d
n
a
A
D
S
0
0
3
s
n
t
F
)
2
(
e
m
i
T
ll
a
F
L
C
S
d
n
a
A
D
S
0
0
3
s
n
t
O
T
S
:
U
S
e
m
i
T
p
u
t
e
S
n
o
i
t
i
d
n
o
C
p
o
t
S
0
0
6
s
n
t
H
D
e
m
i
T
d
l
o
H
t
u
O
a
t
a
D
0
5
s
n
t
R
W
e
m
i
T
e
l
c
y
C
e
t
i
r
W
5
s
m
t
P
S
)
L
C
S
,
A
D
S
(
n
o
i
s
s
s
e
r
p
p
u
S
t
u
p
n
I
0
5
s
n
t
P
W
;
U
S
e
m
i
T
p
u
t
e
S
P
W
0
0
6
s
n
t
P
W
;
D
H
e
m
i
T
d
l
o
H
P
W
0
0
3
1
s
n
CAT24FC65/66
4
Doc. No. 1047, Rev. H
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FUNCTIONAL DESCRIPTION
The CAT24FC65/66 supports the I
2
C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24FC65/66
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or receiver,
but the Master device controls which mode is activated.
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
bottom/top (CAT24FC65/CAT24FC66)1/4 of memory
is write protected. When left floating, memory is
unprotected.
A0, A1, A2: Device Address Inputs
These pins are hardwired or left connected. When
hardwired, up to eight CAT24FC65/66's may be
addressed on a single bus system. When the pins are
left unconnected, the default values are zero.
Figure 3. Start/Stop Timing
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
START BIT
SDA
STOP BIT
SCL
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
CAT24FC65/66
5
Doc No. 1047, Rev. H
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
The features of the I
2
C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC65/66 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The CAT24FC65/66 uses the next three
bits as address bits. The address bits A2, A1 and A0
Figure 4. Acknowledge Timing
Figure 5. Slave Address Bits
ACKNOWLEDGE
1
START
SCL FROM
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
allow as many as eight devices on the same bus. These
bits must compare to their hardwired input pins. The last
bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24FC65/66 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC65/66 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT24FC65/66 responds with an acknowledge
after receiving a START condition and its slave address.
If the device has been selected along with a write
operation, it responds with an acknowledge after receiving
each 8-bit byte.
When the CAT24FC65/66 begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24FC65/66 will continue to
I
2
C BUS PROTOCOL
1
0
1
0
A2
A1
A0
R/W
CAT24FC65/66
6
Doc. No. 1047, Rev. H
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/
W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24FC65/66. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24FC65/66 acknowledges
once more and the Master generates the STOP condi-
tion. At this time, the device begins an internal program-
ming cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24FC65/66 writes up to 64 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 63 additional bytes. After each byte has
been transmitted, CAT24FC65/66 will respond with an
acknowledge, and internally increment the six low order
address bits by one. The high order bits remain un-
changed.
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter `wraps around',
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24FC65/66 in a single write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24FC65/66 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24FC65/66 is still busy with the
write operation, no ACK will be returned. If
CAT24FC65/66 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to V
CC
, the entire memory array is
protected and becomes read only. The CAT24FC65/66
will accept both slave and byte addresses, but the
memory location accessed is protected from program-
ming by the device's failure to send an acknowledge
after the first byte of data is received.
Figure 7. Page Write Timing
Figure 6. Byte Write Timing
*
=Don't Care Bit
*
=Don't Care Bit
A15A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
DATA
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7A0
BYTE ADDRESS
A
C
K
***
A15A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7A0
BYTE ADDRESS
DATA n+63
DATA
A
C
K
S
T
O
P
A
C
K
DATA n
A
C
K
P
A
C
K
***
CAT24FC65/66
7
Doc No. 1047, Rev. H
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
READ OPERATIONS
The READ operation for the CAT24FC65/66 is initiated
in the same manner as the write operation with one
exception, that R/
W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
Immediate/Current Address Read
The CAT24FC65/66's address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N+1. If N=E (where E=8,191),
then the counter will `wrap around' to address 0 and
continue to clock out data. After the CAT24FC65/66
receives its slave address information (with the R/
W bit
set to one), it issues an acknowledge, then transmits the
8 bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
`dummy' write operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After CAT24FC65/66 acknowledges,
the Master device sends the START condition and the
slave address again, this time with the R/
W bit set to one.
The CAT24FC65/66 then responds with its acknowledge
and sends the 8-bit byte requested. The master device
does not send an acknowledge but will generate a STOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24FC65/66 sends the initial 8-
bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24FC65/66 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24FC65/66 is
outputted sequentially with data from address N followed
by data from address N+1. The READ operation address
counter increments all of the CAT24FC65/66 address
bits so that the entire memory array can be read during
one operation. If more than E (where E=8,191) bytes are
read out, the counter will `wrap around' and continue to
clock out data bytes.
Figure 8. Immediate Address Read Timing
SCL
SDA
8TH BIT
STOP
NO ACK
DATA OUT
8
9
SLAVE
ADDRESS
S
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
N
O
A
C
K
DATA
S
T
O
P
P
CAT24FC65/66
8
Doc. No. 1047, Rev. H
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 9. Selective Read Timing
Figure 10. Sequential Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+x
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
*
=Don't Care Bit
A15A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7A0
BYTE ADDRESS
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
A
R
T
DATA
P
S
T
O
P
***
CAT24FC65/66
9
Doc No. 1047, Rev. H
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a 24FC66JI-TE13 REV-D (SOIC, Industrial Temperature, 2.5 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
Temperature Range
I = Industrial (-40C to 85C)
A = Automotive (-40C to 105C)
Prefix
Device #
Suffix
J
I
TE13
Product
Number
24FC65
24FC66
Tape & Reel
Package
P: PDIP
K: SOIC, EIAJ
J: SOIC, JEDEC
U: TSSOP
RD2: TDFN
L: PDIP (Lead-free, Halogen-free)
W: SOIC, JEDEC (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
X: SOIC, EIAJ (Lead-free, Halogen-free)
ZD2: TDFN (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GX: SOIC, EIAJ (Lead-free, Halogen-free, NiPdAu lead plating)
REV-D
Die Revision
-1.8
Operating Voltage
Blank: 2.5 to 5.5V
24FC66
CAT
Optional
Company ID
E = Extended (-40C to 125C)
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.caalyst-semiconductor.com
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP TM
AE
2
TM
MiniPotTM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
REVISION HISTORY
e
t
a
D
n
o
i
s
i
v
e
R
s
t
n
e
m
m
o
C
3
0
/
8
2
/
7
0
A
e
u
s
s
I
l
a
i
t
i
n
I
4
0
/
6
2
/
2
0
B
)
s
a
e
r
a
ll
a
n
i
d
e
t
a
d
p
u
(
e
g
a
k
c
a
p
P
O
S
S
T
n
i
p
-
8
d
e
d
d
A
4
0
/
2
0
/
4
0
C
n
o
i
t
a
n
g
i
s
e
d
t
e
e
h
s
a
t
a
d
d
e
t
a
n
i
m
il
E
4
0
/
6
1
/
5
0
D
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
g
n
i
t
a
r
e
p
O
.
C
.
D
e
t
a
d
p
U
s
t
i
m
i
L
e
l
c
y
C
e
t
i
r
W
&
d
a
e
R
e
t
a
d
p
U
n
o
i
t
a
m
r
o
f
n
I
g
n
i
r
e
d
r
O
e
t
a
d
p
U
y
r
o
t
s
i
H
n
o
i
s
i
v
e
R
e
t
a
d
p
U
r
e
b
m
u
N
v
e
R
e
t
a
d
p
U
4
0
/
7
0
/
6
0
E
s
t
i
m
i
L
e
l
c
y
C
e
t
i
r
W
&
d
a
e
R
e
t
a
d
p
U
4
0
/
5
2
/
8
0
F
s
e
t
o
n
d
n
a
n
o
i
t
a
m
r
o
f
n
I
g
n
i
r
e
d
r
O
e
t
a
d
p
U
5
0
/
4
2
/
3
0
G
s
e
r
u
t
a
e
F
e
t
a
d
p
U
n
o
i
t
p
i
r
c
s
e
D
e
t
a
d
p
U
s
n
o
i
t
c
n
u
F
n
i
P
e
t
a
d
p
U
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
y
t
il
i
b
a
il
e
R
e
t
a
d
p
U
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
g
n
i
t
a
r
e
p
O
.
C
.
D
e
t
a
d
p
U
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
.
C
.
A
e
t
a
d
p
U
n
o
i
t
a
m
r
o
f
n
I
g
n
i
r
e
d
r
O
e
t
a
d
p
U
5
0
/
3
0
/
8
0
H
n
o
i
t
a
r
u
g
i
f
n
o
C
n
i
P
e
t
a
d
p
U
n
o
i
t
a
m
r
o
f
n
I
g
n
i
r
e
d
r
O
e
t
a
d
p
U
Publication #:
1047
Revison:
H
Issue date:
08/03/05
PDF 
ZIP