1
CAT24WC164
16K-Bit Serial EEPROM, Cascadable
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
PIN CONFIGURATION
BLOCK DIAGRAM
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
V
CC
+1.8V to +6.0V Power Supply
V
SS
Ground
DIP Package (P, L)
SOIC Package (J, W)
5020 FHD F01
FEATURES
I
400 kHz I
2
C bus compatible*
I
1.8 to 6.0 volt operation
I
Low power CMOS technology
I
Write protect feature
- Entire array protected when WP at V
IH
I
Page write buffer
I
Self-timed write cycle with auto-clear
I
1,000,000 program/erase cycles
I
100 year data retention
I
8-pin DIP, 8-pin SOIC, 8-pin MSOP or
8 pin TSSOP
(Also available in "Green" packages)
I
Industrial, automotive and
extended temperature ranges
DESCRIPTION
The CAT24WC164 is a16K-bit, cascadable Serial CMOS
EEPROM internally organized as 2048 words of 8 bits
each. Catalyst's advanced CMOS technology substan-
tially reduces device power requirements. The
CAT24WC164 features a 16-byte page write buffer. The
device operates via the I
2
C bus serial interface, has a
special write protection feature, and is available in 8-pin
DIP, 8-pin SOIC, 8-pin TSSOP and 8-lead MSOP.
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
TSSOP Package (U, Y)
Doc. No. 1026, Rev. I
MSOP Package (R, Z)
VCC
SCL
SDA
1
2
3
4
8
7
6
5
VSS
A2
A0
A1
TEST
HA
LOGEN FREE
TM
LEAD FREE
A2
A0
A1
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A1
A2
VSS
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
E
2
PROM
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
VSS
WP
SCL
A0
A1
A2
SDA
8
7
6
5
VCC
WP
SCL
SDA
A2
A0
A1
VSS
1
2
3
4
CAT24WC164
2
Doc. No. 1026, Rev. I
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Typ
Max
Units
N
END
(3)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
T
DR
(3)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
V
ZAP
(3)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
I
LTH
(3)(4)
Latch-up
JEDEC Standard 17
100
mA
CAPACITANCE
T
A
= 25
C, f = 1.0 MHz, V
CC
= 5V
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
C
I/O
(3)
Input/Output Capacitance (SDA)
V
I/O
= 0V
8
pF
C
IN
(3)
Input Capacitance
V
IN
= 0V
6
pF
(A0, A1, A2, SCL, WP)
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
I
CC
Power Supply Current
f
SCL
= 100 kHz
3
mA
I
SB
(5)
Standby Current (V
CC
= 5.0V)
V
IN
= GND or V
CC
1
A
I
LI
Input Leakage Current
V
IN
= GND to V
CC
10
A
I
LO
Output Leakage Current
V
OUT
= GND to V
CC
10
A
V
IL
Input Low Voltage
1
V
CC
x 0.3
V
V
IH
Input High Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output Low Voltage (V
CC
= 3.0V)
I
OL
= 3 mA
0.4
V
V
OL2
Output Low Voltage (V
CC
= 1.8V)
I
OL
= 1.5 mA
0.5
V
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55
C to +125C
Storage Temperature ....................... 65
C to +150C
Voltage on Any Pin with
Respect to Ground
(1)
........... 2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25
C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(2)
........................ 100mA
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V
CC
+1V.
(5) Maximum standby current (I
SB
) = 10
A for the Automotive and Extended Automotive temperature range.
CAT24WC164
3
Doc. No. 1026, Rev. I
Write Cycle Limits
Symbol
Parameter
Min
Typ
Max
Units
t
WR
Write Cycle Time
5
ms
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8 V - 6.0 V 2.5 V - 6.0 V
Min Max
Min
Max
Units
F
SCL
Clock Frequency
100
400
kHz
T
I
(1)
Noise Suppression Time
200
200
ns
Constant at SCL, SDA Inputs
t
AA
SCL Low to SDA Data Out
3.5
1
s
and ACK Out
t
BUF
(1)
Time the Bus Must be Free Before
4.7
1.2
s
a New Transmission Can Start
t
HD:STA
Start Condition Hold Time
4
0.6
s
t
LOW
Clock Low Period
4.7
1.2
s
t
HIGH
Clock High Period
4
0.6
s
t
SU:STA
Start Condition Setup Time
4.7
0.6
s
(for a Repeated Start Condition)
t
HD:DAT
Data In Hold Time
0
0
ns
t
SU:DAT
Data In Setup Time
50
50
ns
t
R
(1)
SDA and SCL Rise Time
1
0.3
s
t
F
(1)
SDA and SCL Fall Time
300
300
ns
t
SU:STO
Stop Condition Setup Time
4
0.6
s
t
DH
Data Out Hold Time
100
100
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Power-Up Timing
(1)(2)
Symbol
Parameter
Min
Typ
Max
Units
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
1
ms
CAT24WC164
4
Doc. No. 1026, Rev. I
FUNCTIONAL DESCRIPTION
The CAT24WC164 supports the I
2
C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC164
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated. A
maximum of 8 devices may be connected to the bus as
determined by the device address inputs A0, A1, and A2.
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT24WC164 serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.
SDA:
Serial Data/Address
The CAT24WC164 bidirectional serial data/address pin
is used to transfer data into and out of the device. The
SDA pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
A0, A1, A2:
Device Address Inputs
These inputs set device address when cascading multiple
devices. When these pins are left floating the default
values are zeros.
A maximum of eight devices can be cascaded. If only
one CAT24WC164 is addressed on the bus, all three
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
Figure 3. Start/Stop Timing
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
START BIT
SDA
STOP BIT
SCL
CAT24WC164
5
Doc. No. 1026, Rev. I
address pins (A0, A1and A2) can be left floating or
connected to V
SS
.
The CAT24WC164 can be made compatible with the
CAT24WC16 by tying A2, A1 and A0 to VSS or by
leaving A2, A1 and A0 float.
WP:
Write Protect
If the WP pin is tied to V
CC
the entire memory array
becomes Write Protected (READ only). When the WP
pin is tied to V
SS
or left floating normal read/write
operations are allowed to the device.
I
2
C BUS PROTOCOL
The following defines the features of the I
2
C bus protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC164 monitor the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The most
significant bit of the 8-bit slave address is fixed as 1. (see
Fig. 5). The next three significant bits (A2, A1, A0) are
the device address bits and define which device or which
part of the device the Master is accessing (The A1 bit
must be the compliment of the A1 input pin signal). Up
to eight CAT24WC164 devices may be individually
addressed by the system. The next three bits are used
as the three most significant bits of the data word
address. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC164 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC164 then performs a Read or Write operation
depending on the state of the R/
W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowl-
edging device pulls down the SDA line during the ninth
clock cycle, signaling that it received the 8 bits of data.
The CAT24WC164 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
Figure 4. Acknowledge Timing
ACKNOWLEDGE
1
START
SCL FROM
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
PDF 
ZIP