1
CAT25C03/05/09/17/33
2K/4K/8K/16K/32K SPI Serial CMOS E
2
PROM
FEATURES
s
10 MHz SPI Compatible
s
1.8 to 6.0 Volt Operation
s
Hardware and Software Protection
s
Zero Standby Current
s
Low Power CMOS Technology
s
SPI Modes (0,0 &1,1)
s
Commercial, Industrial and Automotive
Temperature Ranges
s
1,000,000 Program/Erase Cycles
s
100 Year Data Retention
s
Self-Timed Write Cycle
s
8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP
s
Page Write Buffer
s
Write Protection
Protect First Page, Last Page, Any 1/4 Array
or Lower 1/2 Array
PIN CONFIGURATION
DIP Package (P)
SOIC Package (S16)
PIN FUNCTIONS
Pin Name
Function
SO
Serial Data Output
SCK
Serial Clock
WP
Write Protect
V
CC
+1.8V to +6.0V Power Supply
V
SS
Ground
CS
Chip Select
SI
Serial Data Input
HOLD
Suspends Serial Input
NC
No Connect
BLOCK DIAGRAM
1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Advanced
DESCRIPTION
The CAT25C03/05/09/17/33 is a 2K/4K/8K/16K/32K-Bit
SPI Serial CMOS E
2
PROM internally organized as
256x8/512x8/1024x8/2048x8/4096x8 bits. Catalyst's
advanced CMOS Technology substantially reduces de-
vice power requirements. The CAT25C03/05 features a
16-byte page write buffer. The 25C09/17/33 features a
32-byte page write buffer.The device operates via the
SPI bus serial interface and is enabled though a Chip
Select (
CS
). In addition to the Chip Select, the clock
input (SCK), data in (SI) and data out (SO) are required
to access the device. The
HOLD
pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C03/05/09/17/33 is de-
signed with software and hardware write protection
features. The device is available in 8-pin DIP, 8-pin
SOIC, 16-pin SOIC, 8-pin TSSOP and 14-pin TSSOP
packages.
TSSOP Package (U14)
SENSE AMPS
SHIFT REGISTERS
SPI
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
I/O
CONTROL
E
2
PROM
ARRAY
COLUMN
DECODERS
XDEC
HIGH VOLTAGE/
TIMING CONTROL
SO
25C128 F02
STATUS
REGISTER
BLOCK
PROTECT
LOGIC
CONTR
OL LOGIC
DATA IN
STORAGE
SI
CS
WP
HOLD
SCK
SOIC Package (S)
VSS
SO
WP
VCC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
CS
SO
WP
CS
VCC
SCK
SI
1
2
3
4
8
7
6
5
VSS
HOLD
CS
NC
1
2
3
4
14
13
12
11
NC
NC
NC
5
6
7
10
9
8
NC
SCK
V
SS
SI
NC
WP
VCC
HOLD
SO
15
16
NC
NC
CS
WP
HOLD
VCC
NC
NC
NC
NC
SO
NC
NC
V
SS
SCK
SI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TSSOP Package (U)
8
7
6
5
VCC
WP
SCL
CS
VSS
1
2
3
4
SO
HOLD
SI
Doc. No. 25068-00 2/98
2
CAT25C03/05/09/17/33
Doc. No. 25068-00 2/98
Advanced
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
CC1
Power Supply Current
5
mA
V
CC
= 5V @ 5MHz
(Operating Write)
SO=open; CS=Vss
I
CC2
Power Supply Current
0.4
mA
V
CC
= 5.5V
(Operating Read)
F
CLK
= 5MHz
I
SB
Power Supply Current
0
A
CS
= V
CC
(Standby)
V
IN
= V
SS
or V
CC
I
LI
Input Leakage Current
2
A
I
LO
Output Leakage Current
3
A
V
OUT
= 0V to V
CC
,
CS = 0V
V
IL
(3)
Input Low Voltage
-1
V
CC
x 0.3
V
V
IH
(3)
Input High Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output Low Voltage
0.4
V
V
OH1
Output High Voltage
V
CC
- 0.8
V
V
OL2
Output Low Voltage
0.2
V
1.8V
V
CC
<2.7V
V
OH2
Output High Voltage
V
CC
-0.2
V
I
OL
= 150
A
I
OH
= -100
A
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55
C to +125
C
Storage Temperature ....................... 65
C to +150
C
Voltage on any Pin with
Respect to Ground
(1)
............ 2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25
C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(2)
........................ 100 mA
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Reference Test Method
N
END
(3)
Endurance
1,000,000
Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR
(3)
Data Retention
100
Years
MIL-STD-883, Test Method 1008
V
ZAP
(3)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
I
LTH
(3)(4)
Latch-Up
100
mA
JEDEC Standard 17
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V
CC
+1V.
4.5V
V
CC
<5.5V
I
OL
= 3.0mA
I
OH
= -1.6mA
3
CAT25C03/05/09/17/33
Doc. No. 25068-00 2/98
Advanced
Limits
1.8, 2.5
4.5V-5.5V
Test
SYMBOL PARAMETER
Min.
Max.
Min.
Max.
UNITS
Conditions
t
SU
Data Setup Time
50
10
ns
V
IH
= 2.4V
t
H
Data Hold Time
50
20
ns
C
L
= 100pF
t
WH
SCK High Time
200
40
ns
V
OL
= 0.8V
t
WL
SCK Low Time
200
40
ns
V
OH
= 2.0v
f
SCK
Clock Frequency
DC
2
DC
10
MHz
t
LZ
HOLD
to Output Low Z
50
50
ns
t
RI
(1)
Input Rise Time
2
2
s
t
FI
(1)
Input Fall Time
2
2
s
t
HD
HOLD
Setup Time
100
40
ns
t
CD
HOLD
HOLD Time
100
40
ns
C
L
= 100pF
t
WC
Write Cycle Time
10
5
ms
t
V
Output Valid from Clock Low
200
80
ns
t
HO
Output HOLD Time
0
0
ns
t
DIS
Output Disable Time
250
75
ns
t
HZ
HOLD
to Output High Z
100
50
ns
t
CS
CS
High Time
250
100
ns
t
CSS
CS
Setup Time
250
100
ns
t
CSH
CS
HOLD Time
250
100
ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
A.C. CHARACTERISTICS
Figure 1. Sychronous Data Timing
C
L
= 50pF
VALID IN
V
IH
V
IL
t
CSS
V
IH
V
IL
V
IH
VIL
V
OH
V
OL
HI-Z
t
SU
t
H
t
WH
t
WL
t
V
t
CS
t
CSH
t
HO
t
DIS
HI-Z
CS
SCK
SI
SO
4
CAT25C03/05/09/17/33
Doc. No. 25068-00 2/98
Advanced
FUNCTIONAL DESCRIPTION
The CAT25C03/05/09/17/33 supports the SPI bus data
transmission protocol. The synchronous Serial Periph-
eral Interface (SPI) helps the CAT25C03/05/09/17/33 to
interface directly with many of today's popular
microcontrollers. The CAT25C03/05/09/17/33 contains
an 8-bit instruction register. (The instruction set and the
operation codes are detailed in the instruction set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C03/05/09/17/33. Input data is latched on the rising
edge of the serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C03/05/09/17/33. During a
read cycle, data is shifted out on the falling edge of the
serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
and the 25C03/05/09/17/33. Opcodes, byte addresses,
or data present on the SI pin are latched on the rising
edge of the SCK. Data on the SO pin is updated on the
falling edge of the SCK.
CS
CS
CS
CS
CS
: Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25C03/
05/09/17/33 and
CS
high disables the CAT25C03/05/
09/17/33.
CS
high takes the SO output pin to high
impedance and forces the devices into a Standby Mode
(unless an internal write operation is underway) The
CAT25C03/05/09/17/33 draws ZERO current in the
Standby mode. A high to low transition on
CS
is required
prior to any sequence being initiated. A low to high
transition on
CS
after a valid write sequence is what
initiates an internal write cycle.
WP
WP
WP
WP
WP
: Write Protect
WP
is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When
WP
is tied low, all write operations to the device
are inhibited.
WP
going low while
CS
is still low will
interrupt a write to the status register. If the internal write
cycle has already been initiated,
WP
going low will have
no effect on any write operation to the status register.
HOLD
HOLD
HOLD
HOLD
HOLD
: Hold
HOLD
is the HOLD pin. The
HOLD
pin is used to pause
transmission to the CAT25C03/05/09/17/33 while in the
middle of a serial sequence without having to re-transmit
entire sequence at a later time. To pause,
HOLD
must be
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 X011
(1)
Read Data from Memory
WRITE
0000 X010
(1)
Write Data to Memory
INSTRUCTION SET
Note:
(1) X=O for 25C03, 25C09, 25C17 and 25C33. X=A8 for 25C05
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Power-Up Timing
(2)(3)
Symbol
Parameter
Max.
Units
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
1
ms
5
CAT25C03/05/09/17/33
Doc. No. 25068-00 2/98
Advanced
7
6
5
4
3
2
1
0
0
0
0
0
0
IDL2
IDL1
IDL0
STATUS REGISTER
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication,
HOLD
is brought high, while SCK is low.
(
HOLD
should be held high any time this function is not
being used.)
HOLD
may be tied high directly to V
CC
or
tied to V
CC
through a resistor. Figure 9 illustrates hold
timing sequence.
IDL2
IDL1
IDL0
0
0
0
Non-Protection
0
0
1
Q1 Protected
0
1
0
Q2 Protected
0
1
1
Q3 Protected
1
0
0
Q4 Protected
1
0
1
H1 Protected
1
1
0
P0 Protected
1
1
1
Pn Protected
25C03
25C05
25C09
25C17
25C33
Q1
00-3F
000-07F 000-0FF
000-1FF
000-3FF
Q2
40-7F
080-0FF 100-1FF
200-3FF
400-7FF
Q3
80-BF
100-17F 200-2FF
400-5FF
800-BFF
Q4
C0-FF
180-1FF 300-3FF
600-7FF
C00-FFF
H1
00-7F
000-0FF 000-1FF
000-3FF
000-7FF
P0
00-0F
000-00F 000-01F
000-01F
000-01F
Pn
F0-FF
1F0-1FF 3E0-3FF 7E0-7FF
FE0-FFF
STATUS REGISTER
The status register defines the protection status of the
device. The register features three protection bits which
allow the user to protect the desirable part of the memory
array. There are seven different variations for the protec-
tion mechanism. The protection can vary from one page
to as much as half of the entire array. These areas and
associated address ranges are protected by configuring
the protection bits of the status register through WRSR
instruction. Once the three protection bits are set, the
associated memory can be read but not written until the
protection bits are reset.
MEMORY PROTECTION
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