08-CAT28C256 DS
1
CAT28C256
32K-Bit Parallel EEPROM
FEATURES
s
Fast Read Access Times: 120/150ns
s
Low Power CMOS Dissipation:
Active: 25 mA Max.
Standby: 150
A Max.
s
Simple Write Operation:
On-Chip Address and Data Latches
Self-Timed Write Cycle with Auto-Clear
s
Fast Write Cycle Time:
5ms Max
s
CMOS and TTL Compatible I/O
s
Hardware and Software Write Protection
s
Automatic Page Write Operation:
1 to 64 Bytes in 5ms
Page Load Timer
s
End of Write Detection:
Toggle Bit
DATA Polling
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
s
Commerical, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28C256 is a fast, low power, 5V-only CMOS
parallel E
2
PROM organized as 32K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and V
CC
power up/down write protection eliminate
additional timing and protection hardware.
DATA
Polling
and Toggle status bits signal the start and end of the self-
timed write cycle. Additionally, the CAT28C256 features
hardware and software write protection.
The CAT28C256 is manufactured using Catalyst's ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
BLOCK DIAGRAM
5096 FHD F02
2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ROW
DECODER
COLUMN
DECODER
HIGH VOLTAGE
GENERATOR
A6A14
CE
OE
WE
A0A5
I/O0I/O7
I/O BUFFERS
32,768 x 8
E
2
PROM
ARRAY
64 BYTE PAGE
REGISTER
VCC
DATA POLLING
AND
TOGGLE BIT
Doc. No. 1004, Rev. A
CAT28C256
2
Doc. No. 1004, Rev. A
5096 FHD F01
PIN CONFIGURATION
TSOP Package (8mm X 13.4mm) (T13)
28C256 F03
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
I/O6
I/O5
I/O4
GND
I/O2
A1
A2
VCC
WE
A8
A9
A11
OE
A7
A6
A5
A4
A3
A10
I/O7
A12
16
15
CE
I/O3
I/O1
I/O0
A0
A14
PLCC Package (N)
DIP Package (P)
I/O2
VSS
I/O6
I/O5
13
14
20
19
18
17
9
10
11
12
24
23
22
21
A1
A0
I/O0
I/O1
OE
A10
CE
I/O7
A5
A4
A3
A2
5
6
7
8
1
2
3
4
A14
A12
A7
A6
A9
A11
28
27
26
25
VCC
WE
A13
A8
A6
A5
A4
A3
5
6
7
8
A2
A1
A0
NC
9
10
11
12
I/O0
13
A8
A9
A11
NC
29
28
27
26
OE
A10
CE
25
24
23
22
I/O7
21
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
14 15 16 17 18 19 20
4
3
2
1 32 31 30
A
7
A
12
A
14
NC
V
CC
WE
A
13
I/O4
I/O3
16
15
I/O6
PIN FUNCTIONS
Pin Name
Function
A
0
A
14
Address Inputs
I/O
0
I/O
7
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
Pin Name
Function
WE
Write Enable
V
CC
5V Supply
V
SS
Ground
NC
No Connect
CAT28C256
3
Doc. No. 1004, Rev. A
D.C. OPERATING CHARACTERISTICS
V
CC
= 5V
10%, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
CC
V
CC
Current (Operating, TTL)
30
mA
CE = OE = V
IL
, f=8MH
z
All I/O's Open
I
CCC
(5)
V
CC
Current (Operating, CMOS)
25
mA
CE = OE = V
ILC
, f=8MH
z
All I/O's Open
I
SB
V
CC
Current (Standby, TTL)
1
mA
CE = V
IH
, All I/O's Open
I
SBC
(6)
V
CC
Current (Standby, CMOS)
150
A
CE = V
IHC
,
All I/O's Open
I
LI
Input Leakage Current
10
10
A
V
IN
= GND to V
CC
I
LO
Output Leakage Current
10
10
A
V
OUT
= GND to V
CC
,
CE = V
IH
V
IH
(6)
High Level Input Voltage
2
V
CC
+0.3
V
V
IL
(5)
Low Level Input Voltage
0.3
0.8
V
V
OH
High Level Output Voltage
2.4
V
I
OH
= 400
A
V
OL
Low Level Output Voltage
0.4
V
I
OL
= 2.1mA
V
WI
Write Inhibit Voltage
3.5
V
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55
C to +125
C
Storage Temperature ....................... 65
C to +150
C
Voltage on Any Pin with
Respect to Ground
(2)
........... 2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25
C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(3)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Test Method
N
END
(1)
Endurance
100,000
Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR
(1)
Data Retention
100
Years
MIL-STD-883, Test Method 1008
V
ZAP
(1)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
I
LTH
(1)(4)
Latch-Up
100
mA
JEDEC Standard 17
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to V
CC
+1V.
(5) V
ILC
= 0.3V to +0.3V.
(6) V
IHC
= V
CC
0.3V to V
CC
+0.3V.
CAT28C256
4
Doc. No. 1004, Rev. A
28C256-12
28C256-15
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
t
RC
Read Cycle Time 120
150
ns
t
CE
CE
Access Time
120
150
ns
t
AA
Address Access Time
120
150
ns
t
OE
OE
Access Time
50
70
ns
t
LZ
(1)
CE
Low to Active Output 0
0
ns
t
OLZ
(1)
OE
Low to Active Output 0
0
ns
t
HZ
(1)(2)
CE
High to High-Z Output
50
50
ns
t
OHZ
(1)(2)
OE
High to High-Z Output
50
50
ns
t
OH
(1)
Output Hold from Address Change 0
0
ns
MODE SELECTION
Mode
CE
WE
OE
I/O
Power
Read
L
H
L
D
OUT
ACTIVE
Byte Write (
WE
Controlled)
L
H
D
IN
ACTIVE
Byte Write (
CE
Controlled)
L
H
D
IN
ACTIVE
Standby, and Write Inhibit
H
X
X
High-Z
STANDBY
Read and Write Inhibit
X
H
H
High-Z
ACTIVE
CAPACITANCE T
A
= 25
C, f = 1.0 MHz, V
CC
= 5V
Symbol
Test
Max.
Units
Conditions
C
I/O
(1)
Input/Output Capacitance
10
pF
V
I/O
= 0V
C
IN
(1)
Input Capacitance
6
pF
V
IN
= 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
A.C. CHARACTERISTICS, Read Cycle
V
CC
=5V + 10%, Unless otherwise specified
CAT28C256
5
Doc. No. 1004, Rev. A
Note:
(1)
This parameter is tested initially and after a design or process change that affects the parameter.
(2)
Input rise and fall times (10% and 90%) < 10 ns.
(3)
A write pulse of less than 20ns duration will not initiate a write cycle.
(4)
A timer of duration t
BLC
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within t
BLC
max. stops the timer.
5096 FHD F04
Figure 1. A.C. Testing Input/Output Waveform(2)
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
CL = 100 pF
OUT
CL INCLUDES JIG CAPACITANCE
Figure 2. A.C. Testing Load Circuit (example)
INPUT PULSE LEVELS
REFERENCE POINTS
2.0 V
0.8 V
2.4 V
0.45 V
5096 FHD F03
A.C. CHARACTERISTICS, Write Cycle
V
CC
=5V+10%, unless otherwise specified
28C256-12 28C256-15
Symbol Parameter Min. Max. Min. Max.
Units
t
WC
Write Cycle Time
5
5
ms
t
AS
Address Setup Time
0
0
ns
t
AH
Address Hold Time
50
50
ns
t
CS
CE
Setup Time
0
0
ns
t
CH
CE
Hold Time
0
0
ns
t
CW
(3)
CE
Pulse Time
100
100
ns
t
OES
OE
Setup Time
0
0
ns
t
OEH
OE
Hold Time
0
0
ns
t
WP
(3)
WE
Pulse Width
100
100
ns
t
DS
Data Setup Time
50
50
ns
t
DH
Data Hold Time
10
10
ns
t
INIT
(1)
Write Inhibit Period After Power-up
5
10
5
10
ms
t
BLC
(1)(4)
Byte Load Cycle Time
0.1
100
0.1
100
s
CAT28C256
6
Doc. No. 1004, Rev. A
ADDRESS
CE
OE
WE
tRC
DATA OUT
DATA VALID
DATA VALID
tCE
tOE
tOH
tAA
tOHZ
tHZ
VIH
HIGH-Z
tLZ
tOLZ
DEVICE OPERATION
Read
Data stored in the CAT28C256 is transferred to the data
bus when
WE
is held high, and both
OE
and
CE
are
held low. The data bus is set to a high impedance state
when either
CE
or
OE
goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Byte Write
A write cycle is executed when both
CE
and
WE
are low,
and
OE
is high. Write cycles can be initiated using either
WE
or
CE
, with the address input being latched on the
falling edge of
WE
or
CE
, whichever occurs last. Data,
conversely, is latched on the rising edge of
WE
or
CE
,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Figure 3. Read Cycle
Figure 4. Byte Write Cycle [WE Controlled]
ADDRESS
CE
OE
WE
DATA OUT
tAS
DATA IN
DATA VALID
HIGH-Z
tCS
tAH
tCH
tWC
tOEH
tBLC
tDH
tDS
tOES
tWP
5096 FHD F06
28C256 F06
CAT28C256
7
Doc. No. 1004, Rev. A
Page Write
The page write mode of the CAT28C256 (essentially an
extended BYTE WRITE mode) allows from 1 to 64 bytes
of data to be programmed within a single E
2
PROM write
cycle. This effectively reduces the byte-write time by a
factor of 64.
Following an initial WRITE operation (
WE
pulsed low, for
t
WP
, and then high) the page write mode can begin by
issuing sequential
WE
pulses, which load the address
and data bytes into a 64 byte temporary buffer. The page
address where data is to be written, specified by bits A
6
to A
14
, is latched on the last falling edge of
WE
. Each
byte within the page is defined by address bits A
0
to A
5
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within t
BLC MAX
of the rising edge of the
preceding
WE
pulse. There is no page write window
limitation as long as
WE
is pulsed low within t
BLC MAX
.
Upon completion of the page write sequence,
WE
must
stay high a minimum of t
BLC MAX
for the internal auto-
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
which writes new data back into the cell. A page write will
only write data to the locations that were addressed and
will not rewrite the entire page.
Figure 5. Byte Write Cycle [CE Controlled]
5096 FHD F07
Figure 6. Page Mode Write Cycle
OE
CE
WE
ADDRESS
I/O
tWP
tBLC
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
BYTE n+2
LAST BYTE
tWC
5096 FHD F10
ADDRESS
CE
OE
WE
DATA OUT
tAS
DATA IN
DATA VALID
HIGH-Z
tAH
tWC
tOEH
tDH
tDS
tOES
tBLC
tCH
tCS
tCW
CAT28C256
8
Doc. No. 1004, Rev. A
WE
CE
OE
I/O6
tOEH
tOE
tOES
tWC
(1)
(1)
ADDRESS
CE
WE
OE
I/O7
DIN = X
DOUT = X
DOUT = X
tOE
tOEH
tWC
tOES
DATA Polling
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O
7
(I/O
0
I/O
6
are indeterminate) until the programming cycle is com-
plete. Upon completion of the self-timed write cycle, all
I/O's will output true data during a read cycle.
Toggle Bit
In addition to the DATA Polling feature of the CAT28C256,
the device offers an additional method for determining
the completion of a write cycle. While a write cycle is in
progress, reading data from the device will result in I/O
6
toggling between one and zero. However, once the write
is complete, I/O
6
stops toggling and valid data can be
read from the device.
Figure 7. DATA Polling
28C256 F10
Figure 8. Toggle Bit
28C256 F11
Note:
(1)
Beginning and ending state of I/O
6
is indeterminate.
CAT28C256
9
Doc. No. 1004, Rev. A
Note:
(1)
Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
BLC
Max., after SDP activation.
HARDWARE DATA PROTECTION
The following is a list of hardware data protection fea-
tures that are incorporated into the CAT28C256.
(1) V
CC
sense provides for write protection when V
CC
falls below 3.5V min.
(2) A power on delay mechanism, t
INIT
(see AC charac-
teristics), provides a 5 to 10 ms delay before a write
sequence, after V
CC
has reached 3.5V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
SOFTWARE DATA PROTECTION
The CAT28C256 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28C256 is
in the standard operating mode).
Figure 9. Write Sequence for Activating Software
Data Protection
Figure 10. Write Sequence for Deactivating
Software Data Protection
WRITE DATA:
AA
ADDRESS:
5555
WRITE DATA:
55
ADDRESS:
2AAA
WRITE DATA:
80
ADDRESS:
5555
WRITE DATA:
AA
ADDRESS:
5555
WRITE DATA:
55
ADDRESS:
2AAA
WRITE DATA:
20
ADDRESS:
5555
5096 FHD F08
5096 FHD F09
SOFTWARE DATA
PROTECTION ACTIVATED
(12)
WRITE DATA:
XX
WRITE LAST BYTE
TO
LAST ADDRESS
TO ANY ADDRESS
WRITE DATA:
AA
ADDRESS:
5555
WRITE DATA:
55
ADDRESS:
2AAA
WRITE DATA:
A0
ADDRESS:
5555
(1)
CAT28C256
10
Doc. No. 1004, Rev. A
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
write timing specifications (Figure 11). Once this is done,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transi-
tions. This gives the user added inadvertent write pro-
tection on power-up in addition to the hardware protec-
tion provided.
To allow the user the ability to program the device with
an E
2
PROM programmer (or for testing purposes) there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
5096 FHD F13
CE
WE
tWP
AA
5555
55
2AAA
A0
5555
DATA
ADDRESS
tBLC
tWC
BYTE OR
PAGE
WRITES
ENABLED
Figure 12. Resetting Software Data Protection Timing
CE
WE
AA
5555
55
2AAA
DATA
ADDRESS
tWC
80
5555
AA
5555
55
2AAA
20
5555
SDP
RESET
DEVICE
UNPROTECTED
5096 FHD F14
ORDERING INFORMATION
Notes:
(1)
The device used in the above example is a CAT28C256NI-15T (PLCC, Industrial temperature, 150ns Access Time, Tape & Reel).
28C256 F16
Speed
12: 120ns
15: 150ns
Prefix
Device #
Suffix
28C256
Product
Number
CAT
Optional
Company
ID
N
I
T
Tape & Reel
T: 500/Reel
Package
P: PDIP
N: PLCC
T13: TSOP (8mmx13.4mm)
-15
Temperature Range
Blank = Commercial (0C to +70C)
I = Industrial (-40C to +85C)
A = Automotive (-40 to +105C)*
* -40C to +125C is available upon request
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #:
1004
Revison:
A
Issue date:
05/16/01
Type:
Final
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