1
CAT28C64B
64K-Bit CMOS PARALLEL E
2
PROM
FEATURES
s
Fast Read Access Times:
120/150ns
s
Low Power CMOS Dissipation:
Active: 25 mA Max.
Standby: 100
A Max.
s
Simple Write Operation:
On-Chip Address and Data Latches
Self-Timed Write Cycle with Auto-Clear
s
Fast Write Cycle Time:
5ms Max.
s
CMOS and TTL Compatible I/O
s
Hardware and Software Write Protection
DESCRIPTION
The CAT28C64B is a fast, low power, 5V-only CMOS
Parallel E
2
PROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA
Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C64B features hardware and software write pro-
tection.
5094 FHD F02
ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ROW
DECODER
COLUMN
DECODER
HIGH VOLTAGE
GENERATOR
A5A12
CE
OE
WE
A0A4
I/O0I/O7
I/O BUFFERS
8,192 x 8
E
2
PROM
ARRAY
32 BYTE PAGE
REGISTER
VCC
DATA POLLING
AND
TOGGLE BIT
BLOCK DIAGRAM
s
Commercial, Industrial and Automotive
Temperature Ranges
s
Automatic Page Write Operation:
1 to 32 Bytes in 5ms
Page Load Timer
s
End of Write Detection:
Toggle Bit
DATA
DATA
DATA
DATA
DATA
Polling
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
The CAT28C64B is manufactured using Catalyst's ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC-
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC, or, 32-
pin PLCC package .
1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25006-0A 2/98 P-1
CAT28C64B
2
Doc. No. 25006-0A 2/98 P-1
PIN CONFIGURATION
A6
A5
A4
A3
5
6
7
8
A2
A1
A0
NC
9
10
11
12
I/O0
13
A8
A9
A11
NC
29
28
27
26
OE
A10
CE
25
24
23
22
I/O7
21
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
14 15 16 17 18 19 20
4
3
2
1 32 31 30
A
7
A
12
NC
NC
V
CC
WE
NC
I/O6
TOP VIEW
5094 FHD F01
I/O2
VSS
I/O6
I/O5
13
14
20
19
18
17
9
10
11
12
24
23
22
21
A1
A0
I/O0
I/O1
OE
A10
CE
I/O7
A5
A4
A3
A2
5
6
7
8
1
2
3
4
NC
A12
A7
A6
A9
A11
28
27
26
25
VCC
WE
NC
A8
I/O4
I/O3
16
15
PLCC Package (N)
SOIC Package (J, K)
DIP Package (P)
I/O2
VSS
I/O6
I/O5
13
14
20
19
18
17
9
10
11
12
24
23
22
21
A1
A0
I/O0
I/O1
OE
A10
CE
I/O7
A5
A4
A3
A2
5
6
7
8
1
2
3
4
NC
A12
A7
A6
A9
A11
28
27
26
25
VCC
WE
NC
A8
I/O4
I/O3
16
15
28C64B F03
TSOP Package (8mm x 13.4mm) (T13)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
I/O6
I/O5
I/O4
GND
I/O2
A1
A2
VCC
NC
WE
NC
A8
A9
A11
OE
A7
A6
A5
A4
A3
A10
I/O7
A12
16
15
CE
I/O3
I/O1
I/O0
A0
PIN FUNCTIONS
Pin Name
Function
Pin Name
Function
A
0
A
12
Address Inputs
WE
Write Enable
I/O
0
I/O
7
Data Inputs/Outputs
V
CC
5 V Supply
CE
Chip Enable
V
SS
Ground
OE
Output Enable
NC
No Connect
CAT28C64B
3
Doc. No. 25006-0A 2/98 P-1
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55
C to +125
C
Storage Temperature ....................... 65
C to +150
C
Voltage on Any Pin with
Respect to Ground
(2)
........... 2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25
C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(3)
........................ 100 mA
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Test Method
N
END
(1)
Endurance
10
5
Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR
(1)
Data Retention
100
Years
MIL-STD-883, Test Method 1008
V
ZAP
(1)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
I
LTH
(1)(4)
Latch-Up
100
mA
JEDEC Standard 17
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to V
CC
+1V.
MODE SELECTION
Mode
CE
WE
OE
I/O
Power
Read
L
H
L
D
OUT
ACTIVE
Byte Write (WE Controlled)
L
H
D
IN
ACTIVE
Byte Write (CE Controlled)
L
H
D
IN
ACTIVE
Standby, and Write Inhibit
H
X
X
High-Z
STANDBY
Read and Write Inhibit
X
H
H
High-Z
ACTIVE
CAPACITANCE T
A
= 25
C, f = 1.0 MHz, V
CC
= 5V
Symbol
Test
Max.
Units
Conditions
C
I/O
(1)
Input/Output Capacitance
10
pF
V
I/O
= 0V
C
IN
(1)
Input Capacitance
6
pF
V
IN
= 0V
CAT28C64B
4
Doc. No. 25006-0A 2/98 P-1
D.C. OPERATING CHARACTERISTICS
V
CC
= 5V
10%, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
CC
V
CC
Current (Operating, TTL)
30
mA
CE
=
OE
= V
IL
,
f = 1/t
RC
min, All I/O's Open
I
CCC
(1)
V
CC
Current (Operating, CMOS)
25
mA
CE
=
OE
= V
ILC
,
f = 1/t
RC
min, All I/O's Open
I
SB
V
CC
Current (Standby, TTL)
1
mA
CE
= V
IH
, All I/O's Open
I
SBC
(2)
V
CC
Current (Standby, CMOS)
100
A
CE
= V
IHC
,
All I/O's Open
I
LI
Input Leakage Current
10
10
A
V
IN
= GND to V
CC
I
LO
Output Leakage Current
10
10
A
V
OUT
= GND to V
CC
,
CE
= V
IH
V
IH
(2)
High Level Input Voltage
2
V
CC
+0.3
V
V
IL
(1)
Low Level Input Voltage
0.3
0.8
V
V
OH
High Level Output Voltage
2.4
V
I
OH
= 400
A
V
OL
Low Level Output Voltage
0.4
V
I
OL
= 2.1mA
V
WI
Write Inhibit Voltage
3.5
V
Note:
(1) V
ILC
= 0.3V to +0.3V.
(2) V
IHC
= V
CC
0.3V to V
CC
+0.3V.
CAT28C64B
5
Doc. No. 25006-0A 2/98 P-1
A.C. CHARACTERISTICS, Read Cycle
V
CC
= 5V
10%, unless otherwise specified.
28C64B-12
28C64B-15
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
t
RC
Read Cycle Time
120
150
ns
t
CE
CE
Access Time
120
150
ns
t
AA
Address Access Time
120
150
ns
t
OE
OE
Access Time
60
70
ns
t
LZ
(1)
CE
Low to Active Output
0
0
ns
t
OLZ
(1)
OE
Low to Active Output
0
0
ns
t
HZ
(1)(2)
CE
High to High-Z Output
50
50
ns
t
OHZ
(1)(2)
OE
High to High-Z Output
50
50
ns
t
OH
(1)
Output Hold from Address Change
0
0
ns
Figure 1. A.C. Testing Input/Output Waveform(3)
INPUT PULSE LEVELS
REFERENCE POINTS
2.0 V
0.8 V
2.4 V
0.45 V
5096 FHD F03
Figure 2. A.C. Testing Load Circuit (example)
5096 FHD F04
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) Input rise and fall times (10% and 90%) < 10 ns.
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
CL = 100 pF
OUT
CL INCLUDES JIG CAPACITANCE
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