1
CAT28F001
1 Megabit CMOS Boot Block Flash Memory
FEATURES
s
Fast Read Access Time: 70/90/120/150 ns
s
On-Chip Address and Data Latches
s
Blocked Architecture
-- One 8 KB Boot Block w/ Lock Out
Top or Bottom Locations
-- Two 4 KB Parameter Blocks
-- One 112 KB Main Block
s
Low Power CMOS Operation
s
12.0V
5% Programming and Erase Voltage
s
Automated Program & Erase Algorithms
s
High Speed Programming
s
Commercial, Industrial and Automotive
Temperature Ranges
28F001 F01
s
Deep Powerdown Mode
-- 0.05
A I
CC
Typical
-- 0.8
A I
PP
Typical
s
Hardware Data Protection
s
Electronic Signature
s
100,000 Program/Erase Cycles and 10 Year
Data Retention
s
JEDEC Standard Pinouts:
-- 32 pin DIP
-- 32 pin PLCC
-- 32 pin TSOP
s
Reset/Deep Power Down Mode
I/O0I/O7
I/O BUFFERS
CE, OE LOGIC
SENSE
AMP
DATA
LATCH
ERASE VOLTAGE
SWITCH
COMMAND
REGISTER
CE
OE
WE
VOLTAGE VERIFY
SWITCH
ADDRESS LA
TCH
Y-DECODER
X-DECODER
Y-GATING
8K-BYTE BOOT BLOCK
4K-BYTE PARAMETER BLOCK
4K-BYTE PARAMETER BLOCK
112K-BYTE MAIN BLOCK
A0A16
WRITE STATE
MACHINE
ADDRESS
COUNTER
STATUS
REGISTER
COMP
ARA
T
O
R
PROGRAM VOLTAGE
SWITCH
RP
BLOCK DIAGRAM
DESCRIPTION
The CAT28F001 is a high speed 128K X 8 bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after sale
code updates.
The CAT28F001 has a blocked architecture with one 8
KB Boot Block, two 4 KB Parameter Blocks and one 112
KB Main Block. The Boot Block section can be at the top
or bottom of the memory map and includes a reprogram-
ming write lock out feature to guarantee data integrity. It
is designed to contain secure code which will bring up
the system minimally and download code to other loca-
tions of CAT28F001.
The CAT28F001 is designed with a signature mode
which allows the user to identify the IC manufacturer and
device type. The CAT28F001 is also designed with on-
Chip Address Latches, Data Latches, Programming and
Erase Algorithms.
The CAT28F001 is manufactured using Catalyst's ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, PLCC or TSOP packages.
1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Licensed Intel
second source
Doc. No. 25071-00 2/98 F-1
CAT28F001
2
Doc. No. 25071-00 2/98 F-1
PIN CONFIGURATION
DIP Package (P)
TSOP Package (Standard Pinout) (T)
28F001 F03
PIN FUNCTIONS
Pin Name
Type
Function
A
0
A
16
Input
Address Inputs for
memory addressing
I/O
0
I/O
7
I/O
Data Input/Output
CE
Input
Chip Enable
OE
Input
Output Enable
WE
Input
Write Enable
V
CC
Voltage Supply
V
SS
Ground
V
PP
Program/Erase
Voltage Supply
RP
Input
Power Down
28F001 F02
PLCC Package (N)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
A4
A5
A6
A7
A12
A15
A16
VPP
VCC
WE
RP
A14
A13
A8
A9
A11
I/O0
I/O1
I/O2
VSS
I/O6
I/O5
I/O4
I/O3
13
14
15
16
20
19
18
17
9
10
11
12
24
23
22
21
A3
A2
A1
A0
OE
A10
CE
I/O7
A7
A6
A5
A4
5
6
7
8
1
2
3
4
VPP
A16
A15
A12
A13
A8
A9
A11
28
27
26
25
32
31
30
29
VCC
WE
RP
A14
A7
A6
A5
A4
5
6
7
8
A3
A2
A1
A0
9
10
11
12
I/O0
13
A14
A13
A8
A9
29
28
27
26
A11
OE
A10
CE
25
24
23
22
I/O7
21
I/O
1
I/O
2
V
SS
I/O
3
I/O
4
I/O
5
I/O
6
14 15 16 17 18 19 20
4
3
2
1 32 31 30
A
12
A
15
A
16
V
PP
V
CC
WE
RP
CAT28F001
3
Doc. No. 25071-00 2/98 F-1
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................... 55
C to +95
C
Storage Temperature ....................... 65
C to +150
C
Voltage on Any Pin with
Respect to Ground
(1)
........... 2.0V to +V
CC
+ 2.0V
(Except A
9
,
RP
,
OE
, V
CC
and V
PP
)
Voltage on Pin A
9
,
RP
AND
OE
with
Respect to Ground
(1)
................... 2.0V to +13.5V
V
PP
with Respect to Ground
during Program/Erase
(1)
.............. 2.0V to +14.0V
V
CC
with Respect to Ground
(1)
............ 2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25
C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Test Method
N
END
(3)
Endurance
100K
Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR
(3)
Data Retention
10
Years
MIL-STD-883, Test Method 1008
V
ZAP
(3)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
I
LTH
(3)(4)
Latch-Up
100
mA
JEDEC Standard 17
CAPACITANCE T
A
= 25
C, f = 1.0 MHz
Limits
Symbol
Test
Min
Max.
Units
Conditions
C
IN
(3)
Input Pin Capacitance
8
pF
V
IN
= 0V
C
OUT
(3)
Output Pin Capacitance
12
pF
V
OUT
= 0V
C
VPP
(3)
V
PP
Supply Capacitance
25
pF
V
PP
= 0V
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V
CC
+1V.
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
CAT28F001
4
Doc. No. 25071-00 2/98 F-1
D.C. OPERATING CHARACTERISTICS
V
CC
= +5V
10%, unless otherwise specified
Limits
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
I
LI
Input Leakage Current
1.0
A
V
IN
= V
CC
or V
SS
V
CC
= 5.5V
I
LO
Output Leakage Current
10
A
V
OUT
= V
CC
or V
SS
,
V
CC
= 5.5V
I
SB1
V
CC
Standby Current CMOS
100
A
CE = V
CC
0.2V = RP
V
CC
= 5.5V
I
SB2
V
CC
Standby Current TTL
1.5
mA
CE = RP = V
IH
, V
CC
= 5.5V
I
PPD
V
PP
Deep Powerdown Current
1.0
A
RP = GND
0.2V
I
CC1
V
CC
Active Read Current
30
mA
V
CC
= 5.5V, CE = V
IL
,
I
OUT
= 0mA, f = 8 MHz
I
CC2
(1)
V
CC
Programming Current
20
mA
V
CC
= 5.5V,
Programming in Progress
I
CC3
(1)
V
CC
Erase Current
20
mA
V
CC
= 5.5V,
Erase in Progress
I
PPS
V
PP
Standby Current
10
A
V
PP
<
V
CC
200
A
V
PP
>
V
CC
I
PP1
V
PP
Read Current
200
A
V
PP
= V
PPH
I
PP2
(1)
V
PP
Programming Current
30
mA
V
PP
= V
PPH
,
Programming in Progress
I
PP3
(1)
V
PP
Erase Current
30
mA
V
PP
= V
PPH
,
Erase in Progress
V
IL
Input Low Level
0.5
0.8
V
V
OL
Output Low Level
0.45
V
I
OL
= 5.8mA, V
CC
= 4.5V
V
IH
Input High Level
2.0
V
CC
+0.5
V
V
OH
Output High Level
2.4
V
I
OH
= 2.5mA, V
CC
= 4.5V
V
ID
A
9
Signature Voltage
11.5
13.0
V
A
9
= V
ID
I
ID
A
9
Signature Current
500
A
A
9
= V
ID
I
CCD
V
CC
Deep Powerdown Current
1.0
A
RP = GND
0.2V
I
CCES
V
CC
Erase Suspend Current
10
mA
Erase Suspended CE = V
IH
I
PPES
V
PP
Erase Suspend Current
300
A
Erase Suspended V
PP
=V
PPH
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
CAT28F001
5
Doc. No. 25071-00 2/98 F-1
SUPPLY CHARACTERISTICS
Limits
Symbol
Parameter
Min
Max.
Unit
V
LKO
V
CC
Erase/Write Lock Voltage
2.5
V
V
CC
V
CC
Supply Voltage
4.5
5.5
V
V
PPL
V
PP
During Read Operations
0
6.5
V
V
PPH
V
PP
During Erase/Program
11.4
12.6
V
V
HH
RP, OE Unlock Voltage
11.4
12.6
V
A.C. CHARACTERISTICS, Read Operation
V
CC
= +5V
10%, unless otherwise specified
JEDEC
Standard
28F001-90
(7)
28F001-12
(7)
28F001-15
(7)
Symbol
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
AVAV
t
RC
Read Cycle Time
90
120
150
ns
t
ELQV
t
CE
CE Access Time
90
120
150
ns
t
AVQV
t
ACC
Address Access Time
90
120
150
ns
t
GLQV
t
OE
OE Access Time
35
50
55
ns
-
t
OH
Output Hold from Address OE/CE Change
0
0
0
ns
t
GLQX
t
OLZ
(1)(6)
OE to Output in Low-Z
0
0
0
ns
t
ELQX
t
LZ
(1)(6)
CE to Output in Low-Z
0
0
0
ns
t
GHQZ
t
DF
(1)(2)
OE High to Output High-Z
30
30
30
ns
t
EHQZ
t
HZ
(1)(2)
CE High to Output High-Z
35
55
55
ns
t
PHQV
t
PWH
RP High to Output Delay
600
600
600
ns
28F001-70
(8)
Min.
Max.
0
0
0
70
70
70
27
30
55
600
5108 FHD F05
Note:
(1)
This parameter is tested initially and after a design or process change that affects the parameter.
(2)
Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3)
Input Rise and Fall Times (10% to 90%) < 10 ns.
(4)
Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(5)
Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(6)
Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For load and reference points, see Fig. 1
(8)
For load and reference points, see Fig. 2
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
CL = 100 pF
OUT
CL INCLUDES JIG CAPACITANCE
INPUT PULSE LEVELS
REFERENCE POINTS
2.0 V
0.8 V
2.4 V
0.45 V
5108 FHD F03A
Figure 1. A.C. Testing Input/Output Waveform
(3)(4)(5)
Testing Load Circuit (example)
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
CL = 30 pF
OUT
CL INCLUDES JIG CAPACITANCE
5108 FHD F04
INPUT PULSE LEVELS
REFERENCE POINTS
3.0 V
0.0 V
1.5 V
5108 FHD F03
Figure 2. Highspeed A.C. Testing Input/Output
Waveform(3)(4)(5)
Testing Load Circuit (example)
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