1
2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CMOS and TTL compatible I/O
Automatic page write operation:
1 to 32 bytes in 5ms
Page load timer
End of write detection:
Toggle bit
DATA
DATA
DATA
DATA
DATA polling
Hardware and software write protection
100,000 program/erase cycles
100 year data retention
CAT28LV64
64K-Bit CMOS PARALLEL EEPROM
DESCRIPTION
The CAT28LV64 is a low voltage, low power, CMOS
parallel EEPROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and V
CC
power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bit signal the start and end of the self-
timed write cycle. Additionally, the CAT28LV64 features
hardware and software write protection.
The CAT28LV64 is manufactured using Catalyst's
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-
pin PLCC packages.
BLOCK DIAGRAM
FEATURES
3.0V to 3.6 V Supply
Read access times:
150/200/250ns
Low power CMOS dissipation:
Active: 8 mA max.
Standby: 100
A max.
Simple write operation:
On-chip address and data latches
Self-timed write cycle with auto-clear
Fast write cycle time:
5ms max.
Commercial, industrial and automotive
temperature ranges
Doc. No. 1010, Rev. D
ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ROW
DECODER
COLUMN
DECODER
HIGH VOLTAGE
GENERATOR
A5A12
CE
OE
WE
A0A4
I/O0I/O7
I/O BUFFERS
8,192 x 8
E
2
PROM
ARRAY
32 BYTE PAGE
REGISTER
VCC
DATA POLLING
AND
TOGGLE BIT
HA
LOGEN FREE
TM
LEAD FREE
CAT28LV64
2
Doc. No. 1010, Rev. D
PIN FUNCTIONS
Pin Name
Function
Pin Name
Function
A
0
A
12
Address Inputs
WE
Write Enable
I/O
0
I/O
7
Data Inputs/Outputs
V
CC
3.0 to 3.6 V Supply
CE
Chip Enable
V
SS
Ground
OE
Output Enable
NC
No Connect
PIN CONFIGURATION
SOIC Package (J, W) (K, X)
DIP Package (P, L)
PLCC Package (N, G)
TSOP Top View (8mm x 13.4mm) (T13, H13)
I/O2
VSS
I/O6
I/O5
13
14
20
19
18
17
9
10
11
12
24
23
22
21
A1
A0
I/O0
I/O1
OE
A10
CE
I/O7
A5
A4
A3
A2
5
6
7
8
1
2
3
4
NC
A12
A7
A6
A9
A11
28
27
26
25
VCC
WE
NC
A8
I/O4
I/O3
16
15
I/O2
VSS
I/O6
I/O5
13
14
20
19
18
17
9
10
11
12
24
23
22
21
A1
A0
I/O0
I/O1
OE
A10
CE
I/O7
A5
A4
A3
A2
5
6
7
8
1
2
3
4
NC
A12
A7
A6
A9
A11
28
27
26
25
VCC
WE
NC
A8
I/O4
I/O3
16
15
A6
A5
A4
A3
5
6
7
8
A2
A1
A0
NC
9
10
11
12
I/O0
13
A8
A9
A11
NC
29
28
27
26
OE
A10
CE
25
24
23
22
I/O7
21
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
14 15 16 17 18 19 20
4 3 2 1 32 31 30
A
7
A
12
NC
NC
V
CC
WE
NC
I/O6
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
I/O6
I/O5
I/O4
GND
I/O2
A1
A2
VCC
WE
A8
A9
A11
OE
A7
A6
A5
A4
A3
A10
I/O7
A12
16
15
CE
I/O3
I/O1
I/O0
A0
NC
NC
CAT28LV64
3
Doc. No. 1010, Rev. D
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55
C to +125C
Storage Temperature ....................... 65
C to +150C
Voltage on Any Pin with
Respect to Ground
(2)
........... 2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25
C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(3)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Test Method
N
END
(1)
Endurance
10
5
Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR
(1)
Data Retention
100
Years
MIL-STD-883, Test Method 1008
V
ZAP
(1)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
I
LTH
(1)(4)
Latch-Up
100
mA
JEDEC Standard 17
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to V
CC
+1V.
MODE SELECTION
Mode
CE
CE
CE
CE
CE
WE
WE
WE
WE
WE
OE
OE
OE
OE
OE
I/O
Power
Read
L
H
L
D
OUT
ACTIVE
Byte Write (WE Controlled)
L
H
D
IN
ACTIVE
Byte Write (CE Controlled)
L
H
D
IN
ACTIVE
Standby, and Write Inhibit
H
X
X
High-Z
STANDBY
Read and Write Inhibit
X
H
H
High-Z
ACTIVE
CAPACITANCE T
A
= 25
C, f = 1.0 MHz
Symbol
Test
Max.
Units
Conditions
C
I/O
(1)
Input/Output Capacitance
10
pF
V
I/O
= 0V
C
IN
(1)
Input Capacitance
6
pF
V
IN
= 0V
CAT28LV64
4
Doc. No. 1010, Rev. D
28LV64-15
28LV64-20
28LV64-25
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
t
RC
Read Cycle Time
150
200
250
ns
t
CE
CE Access Time
150
200
250
ns
t
AA
Address Access Time
150
200
250
ns
t
OE
OEAccess Time
70
80
100
ns
t
LZ
(1)
CE Low to Active Output
0
0
0
ns
t
OLZ
(1)
OE Low to Active Output
0
0
0
ns
t
HZ
(1)(2)
CE High to High-Z Output
50
50
55
ns
t
OHZ
(1)(2)
OE High to High-Z Output
50
50
55
ns
Output Hold from
t
OH
(1)
Address Change
0
0
0
ns
D.C. OPERATING CHARACTERISTICS
V
cc
= 3.0V to 3.6V, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
CC
V
CC
Current (Operating, TTL)
8
mA
CE = OE = V
IL
,
f = 1/t
RC
min, All I/O's Open
I
SBC
(3)
V
CC
Current (Standby, CMOS)
100
A
CE = V
IHC
,
All I/O's Open
I
LI
Input Leakage Current
1
1
A
V
IN
= GND to V
CC
I
LO
Output Leakage Current
5
5
A
V
OUT
= GND to V
CC
,
CE = V
IH
V
IH
(3)
High Level Input Voltage
2
V
CC
+0.3
V
V
IL
Low Level Input Voltage
0.3
0.6
V
V
OH
High Level Output Voltage
2
V
I
OH
= 100
A
V
OL
Low Level Output Voltage
0.3
V
I
OL
= 1.0mA
V
WI
Write Inhibit Voltage
2
V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) V
IHC
= V
CC
0.3V to V
CC
+0.3V.
A.C. CHARACTERISTICS, Read Cycle
V
cc
= 3.0V to 3.6V, unless otherwise specified.
CAT28LV64
5
Doc. No. 1010, Rev. D
28LV64-15
28LV64-20
28LV64-25
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
t
WC
Write Cycle Time
5
5
5
ms
t
AS
Address Setup Time0
0
0
0
ns
t
AH
Address Hold Time
100
100
100
ns
t
CS
CE Setup Time
0
0
0
ns
t
CH
CE Hold Time
0
0
0
ns
t
CW
(2)
CE Pulse Time
110
150
150
ns
t
OES
OE Setup Time
0
10
10
ns
t
OEH
OE Hold Time
0
10
10
ns
t
WP
(2)
WE Pulse Width
110
150
150
ns
t
DS
Data Setup Time
60
100
100
ns
t
DH
Data Hold Time
0
0
0
ns
t
INIT
(1)
Write Inhibit Period
After Power-up
5
10
5
10
5
10
ms
t
BLC
(1)(3)
Byte Load Cycle Time
0.05
100
0.1
100
0.1
100
s
DEVICE
UNDER
TEST
Vcc
1.8 K
OUTPUT
CL INCLUDES JIG CAPACITANCE
CL
= 100 pF
1. 3K
INPUT PULSE LEVELS
REFERENCE POINTS
2.0 V
0.6 V
V - 0.3 V
0.0 V
CC
Figure 1. A.C. Testing Input/Output Waveform
(4)
Figure 2. A.C. Testing Load Circuit (example)
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration t
BLC
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within t
BLC
max. stops the timer.
(4) Input rise and fall times (10% and 90%) < 10 ns.
A.C. CHARACTERISTICS, Write Cycle
V
cc
= 3.0V to 3.6V, unless otherwise specified.
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