CAT34RC02

2-kb I

C Serial EEPROM, Serial Presence Detect

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I

C Bus Protocol.

PIN CONFIGURATION

FUNCTIONAL SYMBOL

DIP Package (P, L)

TSSOP Package (U, Y)

SOIC Package (J, W)

FEATURES

400 kHz I

C bus compatible*

1.7 to 5.5 volt operation

16-byte page write buffer

Hardware write protection for entire memory

Permanent and reversible software write
protection for lower 128 bytes

Schmitt trigger on SCL and SDA inputs

Low power CMOS technology

1,000,000 program/erase cycles

100 year data retention

8-pin DIP, SOIC, TSSOP and TDFN packages

Industrial and extended temperature ranges

DESCRIPTION

The CAT34RC02 is a 2-kb Serial CMOS EEPROM
internally organized as 256 words of 8 bits each. Catalyst's
advanced CMOS technology substantially reduces
device power requirements. The CAT34RC02 features

a 16-byte page write buffer. The device operates via the
I

C bus serial interface and is available in 8-pin DIP,

SOIC, TSSOP and TDFN packages.

Doc No. 1052, Rev. K

A0
A1

VSS

VCC
WP

SCL

SDA

A1
A2

VSS

VCC
WP

SCL

SDA

VCC
WP

SCL

SDA

A0
A1

VSS

LOGEN FREE

LEAD FREE

TDFN Package (SP2, VP2)

PIN FUNCTIONS

Pin Name

Function

, A

Device Address Inputs

SDA

Serial Data/Address

SCL

Serial Clock

Write Protect

1.7 V to 5.5 V Power Supply

Ground

VSS

VCC

SCL

SDA

VCC

VSS

SDA

SCL

CAT34RC02

A2, A1, A0

CAT34RC02

Doc. No. 1052, Rev. K

CAPACITANCE T

= 25

°C, f = 400 kHz, V

= 5 V

Symbol

Test

Conditions

Min

Typ

Max

Units

I/O

(2)

Input/Output Capacitance (SDA)

I/O

= 0 V

(2)

Input Capacitance (other pins)

= 0 V

WPL

WP Input Impedance

< 0.5 V

WPH

WP Input Impedance

IN >

x 0.7

500

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Reference Test Method

Min

Units

END

(2)(*)

Endurance

MIL-STD-883, Test Method 1033

1,000,000

Program/ Erase Cycles

(2)(*)

Data Retention

MIL-STD-883, Test Method 1008

100

Years

ZAP

(2)(*)

ESD Susceptibility

MIL-STD-883, Test Method 3015

4000

Volts

LTH

(2)(3)

Latch-up

JEDEC Standard 17

100

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias .................. -55

°C to +125°C

Storage Temperature ........................ -65

°C to +150°C

Voltage on Any Pin with

Respect to Ground

(1)

............ -2.0 V to V

+ 2.0 V

Voltage on A

0 ..................................................

-2.0 V to +12.0 V

with Respect to V

SS ..............................

-2.0 V to +7.0 V

Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than V

+ 0.5 V. During transitions, the voltage on any pin

may undershoot to no less than -2.0 V or overshoot to no more than VCC + 2.0 V, for periods of less than 20 ns. The maximum DC
voltage on address pin A

is +12.0 V.

(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1.0 V to V

+ 1.0 V.

(4) Standby Current, I

= 10

µA max at extended temperature range.

*COMMENT

Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.

(*) Page Mode, VCC = 5 V, 25

°C

D.C. OPERATING CHARACTERISTICS

= 1.7 V to 5.5 V, unless otherwise specified.

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Power Supply Current (Read)

SCL

= 100 kHz

Power Supply Current (Write)

SCL

= 100 kHz

(4)

Standby Current (V

= 5.0 V)

= GND or V

µA

Input Leakage Current

= GND to V

µA

Output Leakage Current

OUT

= GND to V

µA

Input Low Voltage

x 0.3

Input High Voltage

x 0.7

+ 1.0

OL1

Output Low Voltage (V

= 3.0 V)

= 3 mA

0.4

OL2

Output Low Voltage (V

= 1.7 V)

= 1.5 mA

0.5

RSWP Set/Clear Overdrive

- V

> 4.8 V

High Voltage

CAT34RC02

Doc No. 1052, Rev. K

Write Cycle Limits

Symbol

Parameter

Min

Typ

Max

Units

Write Cycle Time

A.C. CHARACTERISTICS

= 1.7 V to 5.5 V, unless otherwise specified.

Read & Write Cycle Limits

Symbol

Parameter

1.7 V - 5.5 V

2.5 V - 5.5 V

Min

Max

Min

Max

Units

SCL

Clock Frequency

100

400

kHz

(1)

Noise Suppression Time

100

Constant at SCL, SDA Inputs

SCL Low to SDA Data Out

3.5

0.9

µs

and ACK Out

BUF

(1)

Time the Bus Must be Free Before

4.7

1.3

µs

a New Transmission Can Start

HD:STA

Start Condition Hold Time

0.6

µs

LOW

Clock Low Period

4.7

1.3

µs

HIGH

Clock High Period

0.6

µs

SU:STA

Start Condition Setup Time

4.7

0.6

µs

(for a Repeated Start Condition)

HD:DAT

Data In Hold Time

SU:DAT

Data In Setup Time

250

100

(1)

SDA and SCL Rise Time

0.3

µs

(1)

SDA and SCL Fall Time

300

SU:STO

Stop Condition Setup Time

0.6

µs

Data Out Hold Time

100

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t

PUR

and t

PUW

are the delays required from the time V

is stable until the specified operation can be initiated.

Power-Up Timing

(1)(2)

Symbol

Parameter

Min

Typ

Max

Units

PUR

Power-up to Read Operation

PUW

Power-up to Write Operation

The write cycle time is the time elapsed between the
STOP command (following the write instruction) and the
completion of the internal write cycle. During the internal

write cycle, SDA is released by the Slave and the device
does not acknowledge external commands.

CAT34RC02

Doc. No. 1052, Rev. K

FUNCTIONAL DESCRIPTION

The CAT34RC02 supports the I

C (2-wire) Bus data

transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT34RC02
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master alone assigns those roles. A maximum of 8
devices may be connected to the bus as determined by
the device address inputs A

, A

, and A

PIN DESCRIPTIONS

SCL: Serial Clock
The serial clock input pin is used to clock all data
transfers into or out of the device.

SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer data into and out of the device. This pin is an
open drain output in transmit mode.

, A

: Device Address Inputs

These inputs set the device address. When left floating,
the address pins are internally pulled to ground.

WP: Write Protect

This input, when grounded or left floating, allows write
operations to the entire memory. When this pin is tied to
V

, the entire memory is write protected.

START BIT

SDA

STOP BIT

SCL

Figure 3. Start/Stop Timing

Figure 2. Write Cycle Timing

Figure 1. Bus Timing

tWR

STOP
CONDITION

START
CONDITION

ADDRESS

ACK

8th Bit

Byte n

SCL

SDA

tHIGH

SCL

SDA IN

SDA OUT

tLOW

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA

tDH

CAT34RC02

Doc No. 1052, Rev. K

C BUS PROTOCOL

The I

C bus consists of two `wires', SCL and SDA. The

two `wires' are connected to the supply (V

) via pull-up

resistors. Master and Slave devices connect to the bus
via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to `transmit' a `0' and
releases it to `transmit' a `1'.

(1) Data transfer may be initiated only when the bus is

not busy (see A.C. Characteristics).

(2) During a data transfer, the data line must remain

stable whenever the SCL line is high. An SDA
transition while SCL is high will be interpreted as a
START or STOP condition.

START Condition

The START Condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START condition acts as a `wake-up' call for the
Slave devices. A Slave will not respond to commands
unless the MASTER generates a START condition.

STOP Condition

The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP condition starts the internal write cycle, when
following a WRITE command and sends the Slave into
standby mode, when following a READ command.

Device Addressing

The Master initiates a data transfer by creating a START
condition on the bus. The Master then broadcasts an 8-
bit serial Slave address. The four most significant bits of
the Slave address (the `preamble') are fixed to 1010
(Ah), for normal read/write operations and 0110 (6h) for
Software Write Protect (SWP) operations (Fig. 5). The
next three bits, A

, A

and A

, select one of eight possible

Slave devices. The last bit, R/

W, specifies whether a

Read (1) or Write (0) operation is to be performed.

Acknowledge

After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9

clock cycle. The Slave will aslo

acknowledge the 8-bit byte address and every data byte
presented in WRITE mode. In READ mode the Slave
shifts out eight bits of data, and then `releases' the SDA
line durng the 9

clock cycle. If the Master acknowledges

in the 9

clock cycle (by pulling down the SDA line), then

the Slave continues transmitting. When data transfer is
complete, the Master responds with a NoACK (it does
not acknowledge the last data byte) and the Slave stops
transmitting and waits for a STOP condition.

Figure 4. Acknowledge Timing

Figure 5. Slave Address Bits

ACKNOWLEDGE

START

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

DEVICE ADDRESS

R/W

Normal Read and Write

Programming the Write
Protect Register

CAT34RC02

Doc. No. 1052, Rev. K

WRITE OPERATIONS

Byte Write

In Byte Write mode the Master creates a START condition,
and then broadcasts the Slave address, byte address
and data to be written. The Slave acknowledges the
three bytes by pulling down the SDA line during the 9

clock cycle following each byte. The Master creates a
STOP condition after the last ACK from the Slave, which
then starts the internal write operation (Fig. 6). During
internal write, the Slave will ignore any read/write request
from the Master.

Page Write

The CAT34RC02 contains 256 bytes of data, arranged
in 16 pages of 16 bytes each. The page is selected by the
four most significant bits of the address byte presented
to the device after the Slave address, while the four least
significant bits point to the byte within the page. By
`loading' more than one data byte into the device, up to
an entire page can be written in one write cycle (Fig. 7).
The internal byte address counter will increment after
each data byte. If the Master transmits more than 16
data bytes, then earlier bytes will be overwritten by later
bytes in a `wrap-around' fashion within the selected
page. The internal write cycle is started following the
STOP condition created by the Master.

Acknowledge Polling

Acknowledge polling can be used to determine if the
CAT34RC02 is busy writing or is ready to accept
commands. Polling is implemented by sending a
`Selective Read' command (described under READ
OPERATIONS) to the device. The CAT34RC02 will not

acknowledge the Slave address, as long as internal
write is in progress.

WRITE PROTECTION

Hardware Write Protection

With the WP pin held HIGH, the entire memory, as well
as the SWP flags are protected against WRITE operations
(Fig. 9). If the WP pin is left floating or is grounded. then
it has no impact on the operation of the CAT34RC02.

Software Write Protection

The lower half of memory (first 128 bytes) can be
protected against WRITE operations by setting one of
two Software Write Protection (SWP) flags/switches.
The PSWP (Permanent Software Write Protection) flag
can be set but not cleared by the user. The RSWP
(Reversible Software Write Protection) flag can be set
and cleared by the user. Whereas the PSWP flag can be
set `in-system', the RSWP flag is meant to be used
during testing. RSWP commands require the presence
of a very high voltage (higher than VCC) on address pin
A

and fixed logic levels for the other two address pins.

The CAT34RC02 is shipped `unprotected'. The state of
the SWP flags can be read by issuing an `Immediate
Address Read' command, with the Slave address
`preamble' set to 0110 (6h) instead of the `normal' 1010
(Ah). A SWP READ will return the complemented versions
of the two flags in the last two slots of the resulting data
byte; the other six more significant bits in the data byte
have no meaning to the user (Fig. 11).

Figure 7. Page Write Timing

BYTE

ADDRESS

SLAVE

ADDRESS

A
C
K

DATA

A
C
K

S
T

BUS ACTIVITY:

MASTER

SDA LINE

S
T
A
R
T

BUS ACTIVITY:

MASTER

SDA LINE

DATA n+P

BYTE

ADDRESS (n)

A
C
K

DATA n

A
C
K

S
T

A
C
K

DATA n+1

A
C
K

S
T
A
R
T

SLAVE

ADDRESS

NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0

Figure 6. Byte Write Timing

CAT34RC02

Doc No. 1052, Rev. K

The PSWP flag can be set (forever) by issuing a `Byte
Write' command, with the Slave address preamble set to
`6h', followed by a `don't care' address, followed by `don't
care' data and a STOP condition. The CAT34RC02 will
acknowledge the Slave address, dummy byte address
and dummy data (Fig. 10). The PSWP flag will be
permanently set (after the internal write cycle is
completed).

The SWP commands are shown in Table 1.

Table 1. SWP Commands

The CAT34RC02 will not acknowledge RSWP or PSWP
commands, once the PSWP flag is set. If the PSWP flag
is not set, but the WP pin is HIGH, then the CAT34RC02
will react to RSWP or PSWP commands as follows: if the
command attempts to `flip' one of the two SWP switches,
then the CAT34RC02 will respond the same way the
regular memory would, i.e. the command and address
(in this case dummy) are acknowledged, but the data (in
this case dummy) will not be acknowledged; if the

command attempts to `reaffirm' one of the two switches,
then the CAT34RC02 will not acknowledge the command
itself. In addition, the CAT34RC02 will not acknowledge
a `reaffirming' SWP command, even if the WP pin is
LOW.

Power-On Reset (POR)

The CAT34RC02 incorporates Power-On Reset (POR)
circuitry which protects the device against malfunctioning
while V

is lower than the recommended operating

voltage.

The device will power up into a read-only state and will
power-down into a reset state when V

crosses the

POR level of ~1.3V.

READ OPERATIONS

Immediate Address Read

In standby mode, the CAT34RC02 internal address
counter points to the data byte immediately following the
last byte accessed by a previous operation. If the
`previous' byte was the last byte in memory, then the
address counter will point to the first memory byte, etc.
If the CAT34RC02 decodes a Slave address with a `1' in
the R/

W bit position (Fig. 8), it will issue an ACK in the 9

clock cycle, and will then transmit the data byte being
pointed at by the address counter. The Master can then
stop further transmission by issuing a NoACK, followed
by a STOP condition.

Selective Read

The READ operation can also be started at an address
different from the one stored in the address counter. The

Figure 8. Immediate Address Read Timing

SCL

SDA

8th Bit

STOP

NO ACK

DATA OUT

SLAVE

ADDRESS

A
C
K

DATA

N
O

A
C
K

S
T

BUS ACTIVITY:

MASTER

SDA LINE

S
T
A
R
T

CAT34RC02

Doc. No. 1052, Rev. K

Figure 10. Software Write Protect (Write)

Figure 9. Memory Array

* For PSWP A

is at normal CMOS levels and for RSWP, A

is at V

which must be held high beyond the end

of the STOP condition (approximately 1

µs of "overlap" is sufficient).

address counter can be `initialized' by performing a
`dummy' WRITE operation (Fig. 12). The START
condition is followed by the Slave address (with the R/

bit set to `0') and the desired byte address. Instead of
following up with data, the Master then issues a 2

START, followed by the `Immediate Address Read'
sequence, as described earlier.

Software Write Protectable
(by setting the write
protect flags)

FFH

00H

7FH

Hardware Write Protectable
(by connecting WP pin to
Vcc)

BYTE

ADDRESS

SLAVE

ADDRESS

A
C
K

DATA

A
C
K

S
T

BUS ACTIVITY:

MASTER

SDA LINE

S
T
A
R
T

X X X X X X X

X = Don't Care

Sequential Read

If the Master acknowledges the 1

data byte transmitted

by the CAT34RC02, then the device will continue
transmitting as long as each data byte is acknowledged
by the Master (Fig. 13). If the end of memory is reached
during sequential READ, the address counter will `wrap-
around' to the beginning of memory, etc. Sequential
READ works with either `Immediate Address Read' or
`Selective Read', the only difference being the starting
byte address.

CAT34RC02

Doc No. 1052, Rev. K

REVISION HISTORY

)

(

)

(

)

(

Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com

Publication #:

1052

Revison:

Issue date:

10/18/04

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Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

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Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.

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other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.

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