1
Preliminary
CAT35C704
4K-Bit Secure Access Serial E
2
PROM
FEATURES
s
Single 5V Supply
s
Password READ/WRITE Protection: 1 to 8 Bytes
s
Memory Pointer WRITE Protection
s
Sequential READ Operation
s
256 x16 or 512 x 8 Selectable Serial Memory
s
High Speed Synchronous Protocol
s
Commercial, Industrial and Automotive
Temperature Ranges
s
Operating Frequency: DC3MHz
s
Low Power Consumption:
Active: 3 mA
Standby: 250
A
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
PIN FUNCTIONS
Pin Name
Function
CS
Chip Select
DO
(1)
Serial Data Output
CLK
Clock Input
DI
(1)
Serial Data Input
PE
Parity Enable
ERR
Error Indication Pin
V
CC
+5V Power Supply
GND
Ground
Note:
(1) DI, DO may be tied together to form a common I/O.
DESCRIPTION
The CAT35C704 is a 4K-bit Serial E
2
PROM that safe-
guards stored data from unauthorized access by use of
a user selectable (1 to 8 byte) access code and a
movable memory pointer. Two operating modes provide
unprotected and password-protected operation allow-
ing the user to configure the device as anything from a
ROM to a fully protected no-access memory. The
CAT35C704 uses a unique serial-byte synchronous
communication protocol and has a Sequential Read
feature where data can be sequentially clocked out of
the memory array. The device is available in 8-pin DIP
or 16-pin SOIC packages.
35C704 F02
BLOCK DIAGRAM
5074 FHD F01
PIN CONFIGURATION
SOIC Package (J)
DIP Package (P)
CS
CLK
DI
DO
VCC
PE
ERR
GND
DI
DO
NC
NC
ERR
GND
NC
NC
NC
NC
CS
CLK
NC
NC
VCC
PE
1
2
3
4
8
7
6
5
1
2
3
4
16
15
14
13
5
12
6
11
7
10
8
9
1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
SERIAL
COMMUNI-
CATION
BLOCK
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
STATUS
REGISTER
64-BIT ACCESS CODE
&
CONTROL BLOCK
4K-BIT EEPROM
ARRAY
R/W
BUFFER
ADDRESS
DECODER
ADDRESS
REGISTER
MEMORY
POINTER
DO
CLK
PE
CS
DI
ERR
VCC
GND
Doc. No. 25045-00 2/98
2
Preliminary
CAT35C704
Doc. No. 25045-00 2/98
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55
C to +125
C
Storage Temperature ....................... 65
C to +150
C
Voltage on Any Pin with
Respect to Ground
(1)
........... 2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (T
a
= 25
C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(2)
........................ 100mA
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Reference Test Method
N
END
(3)
Endurance
100,000
Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR
(3)
Data Retention
100
Years
MIL-STD-883, Test Method 1008
V
ZAP
(3)
ESD Susceptability
2000
Volts
MIL-STD-883, Test Method 3015
I
LTH
(3)(4)
Latch-up
100
mA
JEDEC Standard 17
D.C. CHARACTERISTICS
V
CC
= +5V
10%,unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
CC
Power Supply Current
3
mA
V
CC
= 5.5V, CS = V
CC
(Operating)
DO is Unloaded.
I
SB
Power Supply Current
250
A
V
CC
= 5.5V, CS = 0V
(Standby)
DI = 0V, CLK = 0V
V
IL
Input Low Voltage
0.1
0.8
V
V
IH
Input High Voltage
2
V
V
OL
Output Low Voltage
0.4
V
I
OL
= 2.1mA
V
OH
Output High Voltage
2.4
V
I
OH
= 400
A
I
LI
(5)
Input Leakage Current
2
A
V
IN
= 5.5V
I
LO
Output Leakage Current
10
A
V
OUT
= 5.5V, CS = 0V
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V
CC
+1V.
(5) PE pin test conditions: V
IH
< V
IN
< V
IL
Preliminary
CAT35C704
3
Doc. No. 25045-00 2/98
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
HZ
is measured from the falling edge of the clock to the time when the output is no longer driven.
A.C. CHARACTERISTICS
V
CC
= +5V
10%,unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
t
CSS
CS Setup Time
150
ns
t
CSH
CS Hold Time
0
ns
C
L
= 100pF
t
DIS
DI Setup Time
50
ns
V
IN
= V
IH
or V
IL
t
DIH
DI Hold Time
0
ns
V
OUT
= V
OH
or V
OL
t
PD
CLK to DO Delay
150
ns
t
HZ
(1) (2)
CLK to DO High-Z Delay
50
ns
t
EW
Program/Erase Pulse Width
12
ms
t
CSL
CS Low Pulse Width
200
ns
t
CKH
CLK High Pulse Width
165
ns
t
CKL
CLK Low Pulse Width
100
ns
t
SV
ERR Output Delay
150
ns
C
L
= 100pF
t
VCCS
(1)
V
CC
to CS Setup Time
5
s
C
L
= 100pF
t
CSZ
(1)
CS to DO High-Z Delay
50
ns
t
CSD
CS to DO Busy Delay
150
ns
f
CLK
Clock Frequency
DC
3
MHz
4
Preliminary
CAT35C704
Doc. No. 25045-00 2/98
PASSWORD PROTECTION
The CAT35C704 is a 4K-bit E
2
PROM that features a
password protection scheme to prevent unauthorized
access to the information stored in the device. It contains
an access code register which stores one to eight bytes
of access code along with the length of that access code.
Additionally, a memory pointer register stores the ad-
dress that partitions the memory into protected and
unprotected areas. As shipped from the factory, the
device is unprogrammed and unprotected. The length of
the access code is equal to zero and the memory pointer
register points to location zero. Every byte of the device
is fully accessible without an access code. Setting a
password and moving the memory pointer register to
cover all or part of the memory secures the device. Once
secured, the memory is divided into a read/write area
and a read-only area with the entry of a valid access
code. If no access code is entered, the memory is
divided into a read-only area and a non-access area.
Figure 2 illlustrates this partitioning of the memory array.
WRITE PROTECTION
Another feature of the CAT35C704 is WRITE-protection
without the use of an access code. If the memory pointer
register is set to cover all or part of the memory, without
setting the access code register, the device may be
divided into an area which allows full access, and an
area which allows READ-only access. To write into the
READ-only area, the user can override the memory
pointer register for every WRITE instruction or he can
simply move the address in the memory pointer register
to uncover this area, and then write into the memory.
This mechanism prevents inadvertent overwriting of
important data in the memory without the use of an
access code. Figure 3 illustrates this partitioning of the
memory array.
5074 FHD F03
Figure 2. Secure Mode
5074 FHD F04
ACCESS REGISTER:
ACCESS CODE LENGTH:
MEMORY POINTER:
POINTER
REGISTER
ADDRESS
IN MEMORY
READ-ONLY
ACCESS
PASSWORD-ONLY
ACCESS
255 (x16)
511 (x8)
0
ACCESS CODE (18 BYTES)
1 TO 8
a...a
a...a
Figure 1. A.C. Timing
VCC
CS
CLK
DI
tVCCS
DO
tCSS
tCKH
tCKL
tCSH
tHZ
tDIH
tDIS
tPD
tPD
HIGH-Z
HIGH-Z
Preliminary
CAT35C704
5
Doc. No. 25045-00 2/98
READ SEQUENTIAL
To allow for convenient reading of blocks of contiguous
data, the device has a READ SEQUENTIAL instruction
which accepts a starting address of the block and
continuously outputs data of subsequent addresses
until the end of memory, or until Chip Select goes LOW.
The CAT35C704 communicates with external devices
via a synchronous serial communication protocol (SECS)
that has a maximum transmission rate of 3 MHz. The
data transmission may be a continuous stream of data
or it can be packed by pulsing Chip Select LOW in
between each packet of information. (Except for the
SEQUENTIAL READ instruction where Chip Select
must be held high).
PIN DESCRIPTIONS
CS
Chip Select is a TTL compatible input which, when set
HIGH, allows normal operation of the device. Any time
Chip Select is set LOW, it resets the device, terminating
all I/O communication, and puts the output in a high
impedance state. CS is used to reset the device if an
error condition exists or to put the device in a power-
down mode to minimize power consumption. It may also
be used to frame data transmission in applications
where the clock and data input have to be ignored from
time to time. Although CS resets the device, it does not
change the program/erase or the access-enable status,
nor does it terminate a programming cycle once it has
started. The program/erase and access-enable opera-
tions, once enabled, will remain enabled until specific
disabling instructions are sent or until power is removed.
Figure 3. Unprotected Mode
(1)
ACCESS REGISTER:
ACCESS CODE LENGTH:
MEMORY POINTER:
POINTER
REGISTER
ADDRESS
IN MEMORY
READ/WRITE/ERASE
ACCESS
READ-ONLY
ACCESS
255 (x16)
511 (x8)
0
x...x
0
a...a
a...a
5074 FHD F05
Figure 4. ERR Pin Timing
5074 FHD F06
Note:
(1) x = DON'T CARE; a = ADDRESS BIT.
CS
CLK
ERR
tSV
tSV
HIGH-Z
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