SERIAL

DATA

OUTPUT

REGISTER

REF

V 1

OUT

V 3

V 4

OUT

V 2

OUT

PROG

RDY/

BSY

PROGRAM

CONTROL

H.V.

CHARGE

PUMP

DATA
CONTROLLER

CLK

REF

NVRAM

28k

(ea)

WIPER

CONTROL

REGISTERS

AND

GND

CLK

VDD

PROG

RDY/BSY

VREF H1

VREF H2

VREF H4

VREF H3

VREF L1

VREF L2

VREF

VREF L3

VOUT1

VOUT2

VOUT3

VOUT4

GND

CLK

VDD

PROG

RDY/BSY

VREF H1

VREF H2

VREF H4

VREF H3

VREF L1

VREF L2

VREF

VREF L3

VOUT1

VOUT2

VOUT3

VOUT4

CAT525

Configured Digitally Programmable Potentiometer (DPPTM): Programmable Voltage Applications

FEATURES

Four 8-bit DPPs configured as programmable

voltage sources in DAC-like applications

Independent reference inputs

Buffered wiper outputs

Non-volatile NVRAM memory wiper storage

Output voltage range includes both supply rails

4 independently addressable buffered
output wipers

1 LSB accuracy, high resolution

Serial Microwire-like interface

Single supply operation: 2.7V - 5.5V

Setting read-back without effecting outputs

APPLICATIONS

Automated product calibration

Remote control adjustment of equipment

Offset, gain and zero adjustments in
self-calibrating and adaptive control systems

Tamper-proof calibrations

DAC (with memory) substitute

DESCRIPTION

The CAT525 is a quad 8-bit digitally programmable
potentiometer (DPPTM) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax machines
and cellular telephones on automated high volume
production lines and systems capable of self calibration,
it is also well suited for applications were equipment
requiring periodic adjustment is either difficult to access
or located in a hazardous environment.

The CAT525 offers four independently programmable
DPPs each having its own reference inputs and each
capable of rail to rail output swing. The wipers are
buffered by rail to rail op amps. Wiper settings, stored in
non-volatile NVRAM memory, are not lost when the
device is powered down and are automatically reinstated
when power is returned. Each wiper can be dithered to

PIN CONFIGURATION

test new output values without effecting the stored
settings and stored settings can be read back without
disturbing the DPP's output.

Control of the CAT525 is accomplished with a simple 3-
wire, Microwire-like serial interface. A Chip Select pin
allows several CAT525's to share a common serial
interface and communications back to the host controller
is via a single serial data line thanks to the CAT525's Tri-
Stated Data Output pin. A RDY/

BSY

output working in

concert with an internal low voltage detector signals
proper operation of non-volatile NVRAM Memory Erase/
Write cycle.

The CAT525 is available in the 0

C to 70

C commercial

and -40

C to 85

C industrial operating temperature

ranges and offered in 20-pin plastic DIP and surface
mount packages.

DIP Package (P)

SOIC Package (J)

CAT525

Doc. No. 2001, Rev. B

FUNCTIONAL DIAGRAM

CAT525

CAT525

Doc. No. 2001, Rev. B

ABSOLUTE MAXIMUM RATINGS

Supply Voltage*

to GND ...................................... -0.5V to +7V

Inputs

CLK to GND ............................ -0.5V to V

+0.5V

CS to GND .............................. -0.5V to V

+0.5V

DI to GND ............................... -0.5V to V

+0.5V

RDY/BSY to GND ................... -0.5V to V

+0.5V

PROG to GND ........................ -0.5V to V

+0.5V

REF

H to GND ........................ -0.5V to V

+0.5V

REF

L to GND ......................... -0.5V to V

+0.5V

Outputs

to GND ............................... -0.5V to V

+0.5V

OUT

1 4 to GND ................... -0.5V to V

+0.5V

Operating Ambient Temperature

Commercial (`C' or Blank suffix) ...... 0

C to +70

Industrial (`I' suffix) ........................ -40

C to +85

Junction Temperature ..................................... +150

Storage Temperature ........................ -65

C to +150

Lead Soldering (10 sec max) .......................... +300

* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Min

Max

Units

Test Method

ZAP

(1)

ESD Susceptibility

2000

Volts

MIL-STD-883, Test Method 3015

LTH

(1)(2)

Latch-Up

100

JEDEC Standard 17

NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.

2. Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to V

+ 1V.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

DD1

Supply Current (Read)

Normal Operating

400

600

DD2

Supply Current (Write)

Programming, V

= 5V

1600

2500

= 3V

1000

1600

Operating Voltage Range

2.7

5.5

Symbol

Parameter

Conditions

Min

Typ

Max

Units

High Level Output Voltage

= -40

-0.3

Low Level Output Voltage

= 1 mA, V

= +5V

0.4

= 0.4 mA, V

= +3V

0.4

LOGIC INPUTS

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Input Leakage Current

= V

Input Leakage Current

= 0V

-10

High Level Input Voltage

Low Level Input Voltage

0.8

POWER SUPPLY

LOGIC OUTPUTS

CAT525

Doc. No. 2001, Rev. B

Symbol

Parameter

Conditions

Min

Typ

Max

Units

CSMIN

Minimum CS Low Time

150

CSS

CS Setup Time

100

CSH

CS Hold Time

DIS

DI Setup Time

DIH

DI Hold Time

DO1

Output Delay to 1

150

DO0

Output Delay to 0

150

Output Delay to High-Z

400

Output Delay to Low-Z

400

BUSY

Erase/Write Cycle Time

PROG Setup Time

150

PROG

Minimum Pulse Width

700

CLK

Minimum CLK High Time

500

CLK

Minimum CLK Low Time

300

Clock Frequency

MHz

DPP Settling Time to 1 LSB

LOAD

= 10 pF, V

= +5V

LOAD

= 10 pF, V

= +3V

NOTES: 1. All timing measurements are defined at the point of signal crossing V

/ 2.

2. These parameters are periodically sampled and are not 100% tested.

AC ELECTRICAL CHARACTERISTICS:
V

= +2.7V to +5.5V, V

REF

H = V

, V

REF

L = 0V

, unless otherwise specified

=100pF,

see note 1

Digital

Analog

POTENTIOMETER CHARACTERISTICS
V

= +2.7V to +5.5V, V

REF

H = V

, V

REF

L = 0V

, unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Units

POT

Potentiometer Resistance

POT

to R

POT

Match

+0.5

Pot

Resistance Tolerance

+15

Voltage on V

REFH

2.7

Voltage on V

REFL

- 2.7

Resolution

0.4

INL

Integral Linearity Error

0.5

LSB

DNL

Differential Linearity Error

0.25

0.5

LSB

OUT

Buffer Output Resistance

OUT

Buffer Output Current

RPOT

TC of Pot Resistance

300

ppm/°C

RATIO

Ratiometric TC

ppm/°C

ISO

Isolation Resistance

Noise

nV/

Potentiometer Capacitances

8/8

Frequency Response

Passive Attenuator

MHz

CAT525

Doc. No. 2001, Rev. B

A. C. TIMING DIAGRAM

1 2 3 4 5

CLK

t H CLK

Rising CLK edge to f

lling CLK edge

t L CLK

lling CLK edge to CLK r

i
sing edge

t CSH

lling CLK edge f

r last data bit (DI)

to f

lling CS edge

t CSS

Rising CS edge to ne

xt r

i
sing CLK edge

t CSMIN

lling CS edge to r

i
sing CS edge

t DIS

Data v

lid to first r

i
sing CLK

edge after CS = high

t DIH

Rising CLK edge to end of data v

lid

t DO0

Rising CLK edge to D0 = lo

t LZ

Rising CS edge to D0 becoming high

w impedance (activ

e output)

t DO1

Rising CLK edge to D0 = high

t HZ

lling CS edge to D0 becoming high

impedance (T

r
i-State)

Rising PR

OG edge to ne

xt r

i
sing

CLK edge

lling CLK edge after PR

OG=H to

r
i
sing RD

BSY

edge

t H CLK

t L CLK

t CSH

t CSS

t CSMIN

t DIS

t DIH

t DO0

t LZ

t DO1

t HZ

TIMING

MIN/MAX

Min

Max

(Max)

Max

(Max)

Min

ARAM

NAME

Y/BSY

t B

USY

Rising PR

OG edge to f

lling

OG edge

t PS

t PR

Max

t PS

1 2 3 4 5

t B

USY

CAT525

Doc. No. 2001, Rev. B

PIN DESCRIPTION

Pin

Name

Function

REFH2

Maximum DPP 2 output voltage

REFH1

Maximum DPP 1 output voltage

Power supply positive

CLK

Clock input pin

RDY/

BSY

Ready/Busy output

Chip select

Serial data input pin

Serial data output pin

PROG

Non-volatile Memory Programming
Enable Input

GND

Power supply ground

REFL1

Minimum DPP 1 output voltage

REFL2

Minimum DPP 2 output voltage

REFL3

Minimum DPP 3 output voltage

REFL4

Minimum DPP 4 output voltage

OUT4

DPP 4 output

OUT3

DPP 3 output

OUT2

DPP 2 output

OUT1

DPP 1 output

REFH4

Maximum DPP 4 output voltage

REFH3

Maximum DPP 3 output voltage

DEVICE OPERATION

The CAT525 is a quad 8-bit configured digitally
programmable potentiometer (DPP/CDPP) whose
outputs can be programmed to any one of 256 individual
voltage steps. Once programmed, these output settings
are retained in non-volatile memory and will not be lost
when power is removed from the chip. Upon power up
the DPPs return to the settings stored in non-volatile
memory. Each confitured DPP can be written to and
read from independently without effecting the output
voltage during the read or write cycle. Each output can
also be adjusted without altering the stored output
setting, which is useful for testing new output settings
before storing them in memory.

DIGITAL INTERFACE

The CAT525 employs a 3 wire serial, Microwire-like
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic "1" as a start bit. The
DPP address and data are clocked into the DI pin on the
clock's rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.

Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high

impedance when not in use.

CHIP SELECT

Chip Select (CS) enables and disables the CAT525's
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP wiper control registers
will remain in effect until CS goes low. Bringing CS to a
logic low returns all DPP outputs to the settings stored in
non-volatile memory and switches DO to its high
impedance Tri-State mode.

Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.

CLOCK

The CAT525's clock controls both data flow in and out of
the IC and non-volatile memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock's rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to non-volatile memory, even
though the data being saved may already be resident in
the DPP wiper control register.

No clock is necessary upon system power-up. The
CAT525's internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using the
external clock.

CDPP/DPP addressing is as follows:

DPP OUTPUT

OUT1

OUT2

OUT3

OUT4

CAT525

Doc. No. 2001, Rev. B

As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
into the control registers. Standard CMOS and TTL logic
families work well in this regard and it is recommended
that any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.

REF

REF

, the voltage applied between pins V

REFH

REFL

sets the configured DPP's Zero to Full Scale output
range where V

REFL

= Zero and V

REFH

= Full Scale. V

REF

can span the full power supply range or just a fraction of
it. In typical applications V

REFH

REFL

are connected

across the power supply rails. When using less than the
full supply voltage be mindfull of the limits placed on
V

REFH

and V

REFL

as specified in the References section

of DC Electrical Characteristics.

READY/

BUSY

When saving data to non-volatile memory, the Ready/
Busy ouput (RDY/

BSY

) signals the start and duration of

the erase/write cycle. Upon receiving a command to
store data (PROG goes high) RDY/

BSY

goes low and

remains low until the programming cycle is complete.
During this time the CAT525 will ignore any data
appearing at DI and no data will be output on DO.

RDY/

BSY

is internally ANDed with a low voltage detector

circuit monitoring V

DD.

If V

is below the minimum value

required for EEPROM programming, RDY/

BSY

will

remain high following the program command indicating
a failure to record the desired data in non-volatile memory.

DATA OUTPUT

Data is output serially by the CAT525, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 525s to share a

single serial data line and simplifies interfacing multiple
525s to a microprocessor.

WRITING TO MEMORY

Programming the CAT525's non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DPP address and eight data bits are
clocked into the DPP wiper control register via the DI pin.
Data enters on the clock's rising edge. The DPP output
changes to its new setting on the clock cycle following
D7, the last data bit.

Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DPP control
register will be ready to receive the next set of address
and data bits. The clock must be kept running throughout
the programming cycle. Internal control circuitry takes
care of generating and ramping up the programming
voltage for data transfer to the non-volatile memory
cells. The CAT525's non-volatile memory cells will
endure over 100,000 write cycles and will retain data for
a minimum of 20 years without being refreshed.

READING DATA

Each time data is transferred into a DPP wiper control
register currently held data is shifted out via the D0 pin,
thus in every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DPP's output. This feature allows

Ps to

poll DPPs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in non-volatile memory so that it can be
restored at the end of the read cycle. In Figure 2 CS
returns low before the 13

clock cycle completes. In

doing so the non-volatile memory setting is reloaded into
the DPP wiper control register. Since this value is the

Figure 1. Writing to Memory

Figure 2. Reading from Memory

PROG

DPP

OUTPUT

t 1 2 3 4 5 6 7 8 9 10 11 12

CURRENT

DPP VALUE

NON-VOLATILE

CURRENT DPP DATA

RDY/BSY

NEW DPP DATA

CURRENT DPP DATA

CURRENT

DPP VALUE

NON-VOLATILE

DPP

OUTPUT

PROG

NEW

DPP VALUE

VOLATILE

NEW

DPP VALUE

NON-VOLATILE

t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2

RDY/BSY

CAT525

Doc. No. 2001, Rev. B

Figure 3. Temporary Change in Output

same as that which had been there previously no change
in the DPP's output is noticed. Had the value held in the
control register been different from that stored in non-
volatile memory then

a change would occur at the read

cycle's conclusion.

TEMPORARILY CHANGE OUTPUT

The CAT525 allows temporary changes in DPP's output
to be made without disturbing the settings retained in
non-volatile memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.

Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP settings may be
changed as many times as required and can be made to
any of the four DPPs in any order or sequence. The
temporary setting(s) remain in effect long as CS remains
high. When CS returns low all four DPPs will return to the
output values stored in non-volatile memory.

When it is desired to save a new setting acquired using
this feature, the new value must be reloaded into the
DPP control register prior to programming. This is
because the CAT525's internal control circuitry discards
from the programming register the new data two clock
cycles after receiving it if no PROG signal is received.

Amplified DPP Output

APPLICATION CIRCUITS

Bipolar DPP Output

CAT525

GND

VDD

REFH

REFL

CONTROL
& DATA

OP 07

V = ( ) -V

OUT

R +

-15V

+15V

+5V

VDPP

For R =

V = 2V -V

OUT

DPP

OUT

VDPP

lifi d DAC O

CAT525

GND

VDD

REFH

REFL

CONTROL
& DATA

OP 07

OUT

-15V

+15V

+5V

V = (1 + ) V

OUT DPP

RF
RI

MSB LSB

1111 1111 ---- (.98 V ) + .01 V = .990 V V = +4.90V

1000 0000 ---- (.98 V ) + .01 V = .502 V V = +0.02V

0111 1111 ---- (.98 V ) + .01 V = .498 V V = -0.02V

0000 0001 ---- (.98 V ) + .01 V = .014 V V = -4.86V

0000 0000 ---- (.98 V ) + .01 V = .010 V V = -4.90V

REF

V = 5V

REF

255

OUT

DPP INPUT DPP OUTPUT ANALOG

R = R

OUTPUT

REF

OUT

128
255
127
255

REF

OUT

1
255

REF

OUT

REF

OUT

0
255

V = 0.99 V

V = 0.01 V

ZERO

REF

V = ------ (V - V ) + V

DPP

CODE

255

ZERO ZERO

REF

NEW DPP DATA

CURRENT DPP DATA

PROG

DPP

OUTPUT

t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2

CURRENT

DPP VALUE

NON-VOLATILE

NEW

DPP VALUE

VOLATILE

CURRENT

DPP VALUE

NON-VOLATILE

RDY/BSY

CAT525

Doc. No. 2001, Rev. B

APPLICATION CIRCUITS (Cont.)

Coarse-Fine Offset Control by Averaging DPP Outputs

for Single Power Supply Systems

Coarse-Fine Offset Control by Averaging DPP Outputs

for Dual Power Supply Systems

CAT525

LT 1029

I > 2 mA

V+

GND

VDD

V = 5.000V

REF

REFH

REFL

CONTROL
& DATA

CAT525

GND

VDD

REFH

REFL

CONTROL
& DATA

15K

5.1V

10K

4.02 K

1.00K

35V

LM 324

1N5231B

MPT3055EL

28 - 32V

OUTPUT

0 - 25V
@ 1A

Digitally Trimmed Voltage Reference

Digitally Controlled Voltage Reference

CAT525

FINE ADJUST

DPP

COARSE ADJUST

DPP

GND

REFL

REFH

VDD

127RC

+5V

VREF

R = ----------

256 1

VREF

Fine adjust gives

1 LSB change in V

when V = ------

OFFSET

VREF

OFFSET

VOFFSET

FINE ADJUST

DPP

COARSE ADJUST

DPP

GND

REFL

REFH

VDD

127RC

+5V

REF

-V

REF

R = ----------------------

OFFSET

VOFFSET

REF

(+V ) - (V )

R = ----------------------

OFFSET

REF

(-V ) + (V )

CAT525

Doc. No. 2001, Rev. B

APPLICATION CIRCUITS (Cont.)

Staircase Window Comparator

Overlapping Window Comparator

CAT525

10K

+5V

WINDOW 2

10K

+5V

WINDOW 3

10K

+5V

WINDOW 4

10K

+5V

WINDOW 5

10K

+5V

WINDOW 1

GND

REFL

PROG

CLK

VPP

VDD

REFH

REF

+5V

1.0

LM 339

DPP 1

DPP 2

DPP 3

DPP 4

WINDOW 1

WINDOW 2

WINDOW 3

WINDOW 4

WINDOW 5

REF

V 1

OUT

V 2

OUT

V 3

OUT

V 4

OUT

GND

WINDOW STRUCTURE

CAT525

10K

+5V

WINDOW 2

10K

+5V

WINDOW 3

10K

+5V

WINDOW 1

GND

REFL

PROG

CLK

VPP

VDD

REFH

REF

+5V

1.0

LM 339

DPP 1

DPP 2

DPP 3

DPP 4

WINDOW 1

WINDOW 2

V 1

OUT

V 2

OUT

V 3

OUT

V 4

OUT

GND

WINDOW STRUCTURE

WINDOW 3

V H

REF

Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com

Publication #:

2001

Revison:

Issue Date:

3/22/02

Type:

Final

Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP TM

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CAT515J-TE13

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CAT515J-TE13