Doc. No. 2003, Rev. C

VDD

CLK

RDY/BSY

PROG

VREFH

VOUT

VREFL

GND

VDD

CLK

RDY/BSY

PROG

VREFH

VOUT

VREFL

GND

CAT521

Configured Digitally Programmable Potentiometer (DPPTM): Programmable Voltage Applications

FEATURES

8-bit DPP configured as a programmable

voltage source in DAC-like applications

Buffered wiper output

Non-volatile NVRAM memory wiper storage

Output voltage range includes both supply rails

1 LSB accuracy, high resolution

Serial Microwire-like interface

Single supply operation: 2.7V - 5.5V

Setting read-back without effecting outputs

APPLICATIONS

Automated product calibration

Remote control adjustment of equipment

Offset, gain and zero adjustments in
self-calibrating and adaptive control systems

Tamper-proof calibrations

DAC (with memory) substitute

DESCRIPTION

The CAT521 is a 8-bit digitally-programmable
potentiometer (DPPTM) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for
self-calibrating systems and for applications where
equipment which requires periodic adjustment is either
difficult to access or in a hazardous environment.

The programmable DPP has an output voltage range
which includes both supply rails. The wiper is buffered
by a rail to rail op amp. The wiper setting, stored in
non-volatile NVRAM memory, is not lost when the
device is powered down and is automatically reinstated
when power is returned. The wiper can be dithered to
test new output values without effecting the stored

FUNCTIONAL DIAGRAM

PIN CONFIGURATION

settings and stored settings can be read back without
disturbing the DPP's output.

The CAT521 is controlled with a simple 3-wire, Microwire-
like serial interface. A Chip Select pin allows several
devices to share a common serial interface.
Communication back to the host controller is via a single
serial data line thanks to the CAT521 Tri-Stated Data
Output pin. A RDY/

BSY

output working in concert with

an internal low voltage detector signals proper operation
of the non-volatile NVRAM memory Erase/Write cycle.

The CAT521 is available in 0

C to 70

C commercial and

-40

C to 85

C industrial operating temperature ranges.

Both 14-pin plastic DIP and surface mount packages
are available.

DIP Package (P)

SOIC Package (J)

CAT521

RDY/BSY

PROG

PROGRAM

CONTROL

CLK

SERIAL

DATA

OUTPUT

REGISTER

GND

OUT

28k

SERIAL

CONTROL

NVRAM

WIPER

CONTROL

REGISTER

AND

REFH

VREFL

CAT521

Doc. No. 2003, Rev. C

Symbol

Parameter

Conditions

Min

Typ

Max

Units

DD1

Supply Current (Read)

Normal Operating

400

600

DD2

Supply Current (Write)

Programming, V

= 5V

1600

2500

= 3V

1000

1600

Operating Voltage Range

2.7

5.5

ABSOLUTE MAXIMUM RATINGS

Supply Voltage*

to GND ...................................... -0.5V to +7V

Inputs

CLK to GND ............................ -0.5V to V

+0.5V

CS to GND .............................. -0.5V to V

+0.5V

DI to GND ............................... -0.5V to V

+0.5V

RDY/BSY to GND ................... -0.5V to V

+0.5V

PROG to GND ........................ -0.5V to V

+0.5V

REF

H to GND ........................ -0.5V to V

+0.5V

REF

L to GND ......................... -0.5V to V

+0.5V

Outputs

to GND ............................... -0.5V to V

+0.5V

OUT

1 4 to GND ................... -0.5V to V

+0.5V

Operating Ambient Temperature

Commercial (`C' or Blank suffix) ...... 0

C to +70

Industrial (`I' suffix) ........................ -40

C to +85

Junction Temperature ..................................... +150

Storage Temperature ........................ -65

C to +150

Lead Soldering (10 sec max) .......................... +300

* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Min

Max

Units

Test Method

ZAP

(1)

ESD Susceptibility

2000

Volts

MIL-STD-883, Test Method 3015

LTH

(1)(2)

Latch-Up

100

JEDEC Standard 17

NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.

2. Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to V

+ 1V.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

High Level Output Voltage

= -40

-0.3

Low Level Output Voltage

= 1 mA, V

= +5V

0.4

= 0.4 mA, V

= +3V

0.4

LOGIC INPUTS

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Input Leakage Current

= V

Input Leakage Current

= 0V

-10

High Level Input Voltage

Low Level Input Voltage

0.8

POWER SUPPLY

LOGIC OUTPUTS

CAT521

Doc. No. 2003, Rev. C

Symbol

Parameter

Conditions

Min

Typ

Max

Units

CSMIN

Minimum CS Low Time

150

CSS

CS Setup Time

100

CSH

CS Hold Time

DIS

DI Setup Time

DIH

DI Hold Time

DO1

Output Delay to 1

150

DO0

Output Delay to 0

150

Output Delay to High-Z

400

Output Delay to Low-Z

400

BUSY

Erase/Write Cycle Time

PROG Setup Time

150

PROG

Minimum Pulse Width

700

CLK

Minimum CLK High Time

500

CLK

Minimum CLK Low Time

300

Clock Frequency

MHz

DPP Settling Time to 1 LSB

LOAD

= 10 pF, V

= +5V

LOAD

= 10 pF, V

= +3V

NOTES: 1. All timing measurements are defined at the point of signal crossing V

/ 2.

2. These parameters are periodically sampled and are not 100% tested.

AC ELECTRICAL CHARACTERISTICS:
V

= +2.7V to +5.5V, V

REF

H = V

, V

REF

L = 0V

, unless otherwise specified

=100pF,

see note 1

Digital

Analog

POTENTIOMETER CHARACTERISTICS
V

= +2.7V to +5.5V, V

REF

H = V

, V

REF

L = 0V

, unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Units

POT

Potentiometer Resistance

POT

to R

POT

Match

+0.5

Pot

Resistance Tolerance

+15

Voltage on V

REFH

2.7

Voltage on V

REFL

- 2.7

Resolution

0.4

INL

Integral Linearity Error

0.5

LSB

DNL

Differential Linearity Error

0.25

0.5

LSB

OUT

Buffer Output Resistance

OUT

Buffer Output Current

RPOT

TC of Pot Resistance

300

ppm/°C

RATIO

Ratiometric TC

ppm/°C

ISO

Isolation Resistance

Noise

nV/

Potentiometer Capacitances

8/8

Frequency Response

Passive Attenuator

MHz

CAT521

Doc. No. 2003, Rev. C

PIN DESCRIPTION

Pin

Name

Function

Power supply positive

CLK

Clock input pin

RDY/

BSY

Ready/Busy output

Chip select

Serial data input pin

Serial data output pin

PROG

EEPROM Programming Enable
Input

GND

Power supply ground

REFL

Minimum DAC output voltage

No Connect

OUT

DPP output

No Connect

REFH

Maximum DPP 1 output voltage

DEVICE OPERATION

The CAT521 is a single 8-bit configured digitally
programmable potentiometer (DPPTM) whose output
can be programmed to any one of 256 individual voltage
steps. Once programmed, the output setting is retained
in non-volatile memory and will not be lost when power
is removed from the chip. Upon power up the DPP
returns to the setting stored in non-volatile memory. The
DPP can be written to and read from without effecting the
output voltage during the read or write cycle. The output
can also be adjusted without altering the stored output
setting, which is useful for testing new output settings
before storing them in memory.

DIGITAL INTERFACE

The CAT521 employs a 3 wire, Microwire-like serial
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic "1" as a start bit. The
DPP address and data are clocked into the DI pin on the
clock's rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.

Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.

CHIP SELECT

Chip Select (CS) enables and disables the CAT521's
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP control register will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DPP outputs to the settings stored in non-
volatile memory and switches DO to its high impedance
Tri-State mode.

Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.

CLOCK

The CAT521 clock controls both data flow in and out of
the device and non-volatile memory cell programming.
Serial data is shifted into the DI pin and out of the DO pin
on the clock's rising edge. While it is not necessary for
the clock to be running between data transfers, the clock
must be operating in order to write to non-volatile memory,
even though the data being saved may already be
resident in the DPP wiper control register.

No clock is necessary upon system power-up. The
CAT521 internal power-on reset circuitry loads data
from non-volatile memory to the DPP without using the
external clock.

DPP addressing is as follows:

DPP OUTPUT

OUT

CAT521

Doc. No. 2003, Rev. C

As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
into the control register. Standard CMOS and TTL logic
families work well in this regard and it is recommended
that any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.

REF

REF

, the voltage applied between pins V

REFH

REFL

sets the DPP's Zero to Full Scale output range where
V

REFL

= Zero and V

REFH

= Full Scale. V

REF

can span the

full power supply range or just a fraction of it. In typical
applications V

REFH

REFL

are connected across the

power supply rails. When using less than the full supply
voltage be mindfull of the limits placed on V

REFH

and

REFL

as specified in the References section of DC

Electrical Characteristics.

READY/

BUSY

When saving data to non-volatile memory, the Ready/
Busy ouput (RDY/

BSY

) signals the start and duration of

the non-volatile erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/

BSY

goes low and remains low until the programming cycle
is complete. During this time the CAT521 will ignore any
data appearing at DI and no data will be output on DO.

RDY/

BSY

is internally ANDed with a low voltage detector

circuit monitoring V

DD.

If V

is below the minimum value

required for non-volatile programming, RDY/

BSY

will

remain high following the program command indicating
a failure to record the desired data in non-volatile memory.

DATA OUTPUT

Data is output serially by the CAT521, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 521s to share a

single serial data line and simplifies interfacing multiple
521s to a microprocessor.

WRITING TO MEMORY

Programming the CAT521's non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DPP address and eight data bits are
clocked into the DPP wiper control register via the DI pin.
Data enters on the clock's rising edge. The DPP output
changes to its new setting on the clock cycle following
D7, the last data bit.

Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DPP wiper
control register will be ready to receive the next set of
address and data bits. The clock must be kept running
throughout the programming cycle. Internal control
circuitry takes care of generating and ramping up the
programming voltage for data transfer to the non-volatile
memory cells. The CAT521 non-volatile memory cells
will endure over 1,000,000 write cycles and will retain
data for a minimum of 100 years without being refreshed.

READING DATA

Each time data is transferred into the DPP wiper control
register currently held data is shifted out via the D0 pin,
thus in every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DPP's output. This feature allows

Ps to

poll DPPs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in non-volatile memory so that it can be
restored at the end of the read cycle. In Figure 2 CS
returns low before the 13

clock cycle completes. In

doing so the non-volatile memory's setting is reloaded
into the DPP wiper control register. Since this value is

Figure 1. Writing to Memory

Figure 2. Reading from Memory

NEW DPP DATA

CURRENT DPP DATA

CURRENT

DPP VALUE

NON-VOLATILE

DPP

OUTPUT

PROG

NEW

DPP VALUE

VOLATILE

NEW

DPP VALUE

NON-VOLATILE

t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2

RDY/BSY

PROG

DPP

OUTPUT

t 1 2 3 4 5 6 7 8 9 10 11 12

CURRENT

DPP VALUE

NON-VOLATILE

CURRENT DPP DATA

RDY/BSY

CAT521

Doc. No. 2003, Rev. C

Figure 3. Temporary Change in Output

the same as that which had been there previously no
change in the DPP's output is noticed. Had the value
held in the control register been different from that stored
in non-volatile memory then

a change would occur at the

read cycle's conclusion.

TEMPORARILY CHANGE OUTPUT

The CAT521 allows temporary changes in the DPP's
output to be made without disturbing the settings retained
in non-volatile memory. This feature is particularly
useful when testing for a new output setting and allows
for user adjustment of preset or default values without
losing the original factory settings.

Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP settings may be
changed as many times as required. The temporary
setting remains in effect long as CS remains high. When
CS returns low the DPP will return to the output value
stored in non-volatile memory.

When it is desired to save a new setting acquired using
this feature, the new value must be reloaded into the
DPP wiper control register prior to programming. This is
because the CAT521's internal control circuitry discards
from the programming register the new data two clock
cycles after receiving it if no PROG signal is received.

Amplified DPP Output

APPLICATION CIRCUITS

Bipolar DPP Output

NEW DPP DATA

CURRENT DPP DATA

PROG

DPP

OUTPUT

t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2

CURRENT

DPP VALUE

NON-VOLATILE

NEW

DPP VALUE

VOLATILE

CURRENT

DPP VALUE

NON-VOLATILE

RDY/BSY

MSB LSB

1111 1111 ---- (.98 VREF) + .01 VREF= .990 V V = +4.90V

1000 0000 ---- (.98 VREF) + .01 VREF= .502 V V = +0.02V

0111 1111 ---- (.98 VREF) + .01 VREF= .498 V V = -0.02V

0000 0001 ---- (.98 VREF + .01 VREF = .014 V V = -4.86V

0000 0000 ---- (.98 VREF) + .01 VREF = .010 V V = -4.90V

REF

V = 5V

REF

255

OUT

DPP INPUT DPP OUTPUT ANALOG

R = R

OUTPUT

REF

OUT

128
255
127
255

REF

OUT

1
255

REF

OUT

REF

OUT

0
255

VFS = 0.99 V

V = 0.01 V

ZERO

V = ------ (V - V ) + V

DPP

CODE

255

ZERO ZERO

GND

VDD

CONTROL
& DATA

OP 07

-15V

+15V

+5V

For R =

V = 2V -V

OUT

DPP

VOUT

VOUT =

VDPP (RI+RF)-VIRF

VREFH

VREFL

CAT521

GND

VDD

REFH

REFL

CONTROL
& DATA

OP 07

OUT

-15V

+15V

+5V

V = (1 + ) V

OUT DPP

RF
RI

Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com

Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP TM

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.

Publication #:

2003

Revison:

Issue date:

3/22/02

Type:

Final

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