Advance Information

FEATURES

Two 8-bit DPPS Configured as Programmable

Voltages in DAC-like Applications

Buffered Wiper Outputs

Nonvolatile Wiper Storage

Output voltage range includes both supply rails

2 independently addressable output wipers

1 LSB Accuracy, High Resolution

Serial

P interface

Single supply operation: 2.7V-5.5V

Setting read-back without effecting outputs

APPLICATIONS

Automated product calibration.

Remote control adjustment of equipment

Offset, gain and zero adjustments in Self-
Calibrating and Adaptive Control systems.

Tamper-proof calibrations.

DAC (with memory) substitute

DESCRIPTION

The CAT523 is a dual, 8-bit digitally-programmable
potentiometer configured for programmable voltage and
DAC-like applications. Intended for final calibration of
products such as camcorders, fax machines and cellular
telephones on automated high volume production lines,
it is also well suited for systems capable of self
calibration, and applications where equipment which is
either difficult to access or in a hazardous environment,
requires periodic adjustment.

The 2 independently programmable DPPs have a
common output voltage range which includes both
supply rails. The wipers are buffered by rail to rail OP
AMPS. Wiper settings, stored in non-volatile memory,
are not lost when the device is powered down and are
automatically reinstated when power is returned. Each
wiper can be dithered to test new output values without

effecting the stored settings and stored settings can be
read back without disturbing the DAC's output.

Control of the CAT523 is accomplished with a simple 3
wire serial interface. A Chip Select pin allows several
CAT523's to share a common serial interface and
communication back to the host controller is via a single
serial data line thanks to the CAT523's Tri-Stated Data
Output pin. A RDY/

BSY

output working in concert with

an internal low voltage detector signals proper operation
of non-volatile Erase/Write cycle.

The CAT523 is available in the 0 to 70

C Commercial

and 40

C to + 85

C Industrial operating temperature

ranges and offered in 14-pin plastic DIP and SOIC
mount packages.

FUNCTIONAL DIAGRAM

PIN CONFIGURATION

CAT523

Configured Digitally Programmable Potentiometer (DPP): Programmable Voltage Applications

DIP Package (P)

SOIC Package (J)

CAT523

Doc. No. 25076-00 2/98 M-1

RDY/

BSY

CLK

PROG

VDD

GND

VREFH
VOUT1
VOUT2

VREFL

CLK

PROG

VDD

GND

VREFH
VOUT1
VOUT2

VREFL

CAT

523

CAT

523

RDY/

BSY

RDY/BSY

PROG

PROGRAM

CONTROL

CLK

SERIAL

CONTROL

SERIAL

DATA

OUTPUT

REGISTER

GND

V 1

OUT

V 2

DATA

REGISTER

AND

NONVOLATILE

MEMORY

REFH

V L

REF

CAT523

Advance Information

Logic Inputs

Input Leakage Current

= V

Input Leakage Current

= 0V

High Level Input Voltage

Low Level Input Voltage

0.8

References

REF

H Input Voltage Range

2.7

REF

L Input Voltage Range

GND

-2.7

REF

L Resistance

Logic Outputs

High Level Output Voltage

= 40

0.3

Low Level Output Voltage

= 1 mA, V

= +5V

0.4

= 0.4 mA, V

= +3V

0.4

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage

to GND ...................................... 0.5V to +7V

Inputs

CLK to GND ............................ 0.5V to V

+0.5V

CS to GND .............................. 0.5V to V

+0.5V

DI to GND ............................... 0.5V to V

+0.5V

PROG to GND ........................ 0.5V to V

+0.5V

REF

H to GND ........................ 0.5V to V

+0.5V

REF

L to GND ......................... 0.5V to V

+0.5V

Outputs

to GND ............................... 0.5V to V

+0.5V

OUT

1 4 to GND ................... 0.5V to V

+0.5V

Operating Ambient Temperature

Commercial (`C' suffix) .................... 0

C to +70

Industrial (`I' suffix) ...................... 40

C to +85

Junction Temperature ..................................... +150

Storage Temperature ....................... 65

C to +150

Lead Soldering (10 sec max) .......................... +300

* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.

DC ELECTRICAL CHARACTERISTICS:
V

= +2.7 to +5.5V, V

REF

H = V

, V

REF

L = 0V, unless otherwise specified

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Min

Max

Units

Test Method

ZAP

(1)

ESD Susceptibility

2000

Volts

MIL-STD-883, Test Method 3015

LTH

(1)(2)

Latch-Up

100

JEDEC Standard 17

NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.

2. Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to V

+ 1V.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Resolution

Bits

Accuracy

INL

Integral Linearity Error

LOAD

= 10

A, T

= C

LSB

= I

LSB

LOAD

= 40

A, T

= C

LSB

= I

LSB

DNL

Differential Linearity Error

LOAD

= 10

A, T

= C

0.5

LSB

= I

0.5

LSB

LOAD

= 40

A, T

= C

1.5

LSB

= I

1.5

LSB

CAT523

Advance Information

AC ELECTRICAL CHARACTERISTICS:
V

= +2.7V to +5.5V, V

REF

H = +V

, V

REF

L = 0V, unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Digital

CSMIN

Minimum CS Low Time

150

CSS

CS Setup Time

100

CSH

CS Hold Time

DIS

DI Setup Time

DIH

DI Hold Time

DO1

Output Delay to 1

150

DO0

Output Delay to 0

150

Output Delay to High-Z

400

Busy

Erase/Write Cycle Time

Output Delay to Low-Z

400

PROG

Erase/Write Pulse Width

700

PROG Setup Time

150

CLK

Minimum CLK High Time

500

CLK

Minimum CLK Low Time

300

Clock Frequency

MHz

Analog

DAC Settling Time to 1/2 LSB

LOAD

= 10 pF, V

= +5V

LOAD

= 10 pF, V

= +3V

Pin Capacitance

Input Capacitance

= 0V, f = 1 MHz

(2)

OUT

Output Capacitance

OUT

= 0V, f = 1 MHz

(2)

NOTES: 1. All timing measurements are defined at the point of signal crossing V

/ 2.

2. These parameters are periodically sampled and are not 100% tested.

Analog Output

Temperature

Power Supply

DC ELECTRICAL CHARACTERISTICS (Cont.):
V

= +2.7V to +5.5V , V

REF

H = +V

, V

REF

L = 0V, unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Units

FSO

Full-Scale Output Voltage

= V

REF

0.99 V

0.995 V

ZSO

Zero-Scale Output Voltage

= V

REF

0.005 V

0.01 V

DAC Output Load Current

OUT

DAC Output Impedance

= +5V

100k

= +3V

150k

PSSR

Power Supply Rejection

LOAD

= 250 nA

LSB / V

OUT

Temperature Coefficient

REF

H = +5V, V

REF

L = 0V

200

= +5V, I

LOAD

= 250nA

REF

Temperature Coefficient of

REF

H to V

REF

700

ppm /

REF

Resistance

DD1

Supply Current (Read)

Normal Operating

400

600

DD2

Supply Current (Write)

=5V

1600

2500

=3V

1000

1600

Operating Voltage Range

2.7

5.5

= 100 pF,

see note 1

CAT523

Advance Information

DAC addressing is as follows:

DAC OUTPUT

OUT

PIN DESCRIPTION

Pin

Name

Function

Power supply positive.

CLK

Clock input pin.Clock input pin.

RDY/

BSY

Ready/Busy Output

Chip Select

Serial data input pin.

Serial data output pin.

PROG

EEPROM Programming Enable
Input

GND

Power supply ground.

REF

Minimum DAC output voltage.

No Connect.

OUT

DAC output channel 2.

OUT

DAC output channel 1.

REF

Maximum DAC output voltage.

DEVICE OPERATION

The CAT523 is a quad 8-bit Digital to Analog Converter
(DAC) whose outputs can be programmed to any one of
256 individual voltage steps. Once programmed, these
output settings are retained in non-volatile EEPROM
memory and will not be lost when power is removed from
the chip. Upon power up the DACs return to the settings
stored in EEPROM memory. Each DAC can be written
to and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be temporarily adjusted without chang-
ing the stored output setting, which is useful for testing
new output settings before storing them in memory.

DIGITAL INTERFACE

The CAT523 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic "1" as a start bit. The DAC
address and data are clocked into the DI pin on the
clock's rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.

Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.

CHIP SELECT

Chip Select (CS) enables and disables the CAT523's
read and write operations. When CS is high data may be

read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high imped-
ance Tri-State mode.

Because CS functions like a reset the CS pin has been
equipped with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.

CLOCK

The CAT523's clock controls both data flow in and out of
the IC and EEPROM memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock's rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to EEPROM memory, even
though the data being saved may already be resident in
the DAC control register.

No clock is necessary upon system power-up. The
CAT523's internal power-on reset circuitry loads data
from EEPROM to the DACs without using the external
clock.

As data transfers are edge triggered clean clock transi-
tions are necessary to avoid falsely clocking data into the
control registers. Standard CMOS and TTL logic fami-
lies work well in this regard and it is recommended that
any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.

CAT523

Advance Information

complished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DAC address and eight data bits are
clocked into the DAC control register via the DI pin. Data
enters on the clock's rising edge. The DAC output
changes to its new setting on the clock cycle following
D7, the last data bit.

Programming is achieved by bringing PROG high for a
minimum of 3 ms. PROG must be brought high some-
time after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DAC control
register will be ready to receive the next set of address
and data bits. The clock must be kept running through-
out the programming cycle. Internal control circuitry
takes care of ramping the programming voltage for data
transfer to the EEPROM cells. The CAT523's EEPROM
memory cells will endure over 100,000 write cycles and
will retain data for a minimum of 100 years without being
refreshed.

READING DATA

Each time data is transferred into a DAC control register
currently held data is shifted out via the D0 pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DAC's output. This feature allows

Ps to

poll DACs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in EEPROM so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low before
the 13

clock cycle completes. In doing so the EEPROM's

setting is reloaded into the DAC control register. Since

REF

REF

, the voltage applied between pins V

REF

andV

REF

sets the DAC's Zero to Full Scale output range where
V

REF

L = Zero and V

REF

= Full Scale. V

REF

can span the

full power supply range or just a fraction of it. In typical
applications V

REF

andV

REF

L are connected across the

power supply rails. When using less than the full supply
voltage V

REF

H is restricted to voltages between V

and

/2 and V

REF

L to voltages between GND and V

/2.

READY

/BUSY

When saving data to non-volatile EEPROM memory, the
Ready/Busy ouput (RDY/

BSY

) signals the start and

duration of the EEPROM erase/write cycle. Upon receiv-
ing a command to store data (PROG goes high) RDY/

BSY

goes low and remains low until the programming

cycle is complete. During this time the CAT523 will
ignore any data appearing at DI and no data will be
output on DO.

RDY/

BSY

is internally ANDed with a low voltage detec-

tor circuit monitoring V

DD.

If V

is below the minimum

value required for EEPROM programming, RDY/

BSY

will remain high following the program command indicat-
ing a failure to record the desired data in non-volatile
memory.

DATA OUTPUT

Data is output serially by the CAT523, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 523s to share a
single serial data line and simplifies interfacing multiple
523s to a microprocessor.

WRITING TO MEMORY

Programming the CAT523's EEPROM memory is ac-

Figure 2. Reading from Memory

Figure 1. Writing to Memory

PROG

DAC

OUTPUT

t 1 2 3 4 5 6 7 8 9 10 11 12

CURRENT

DAC VALUE

NON-VOLATILE

CURRENT DAC DATA

NEW DAC DATA

CURRENT DAC DATA

CURRENT

DAC VALUE

NON-VOLATILE

DAC

OUTPUT

PROG

NEW

DAC VALUE

VOLATILE

NEW

DAC VALUE

NON-VOLATILE

t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2

RDY/BSY

CAT523

Advance Information

OPT 504

GND

VDD

V H

REF

V L

REF

CONTROL
& DATA

OP 07

V = ( ) -V

OUT

R +

-15V

+15V

+5V

V DAC

For R =

V = 2V -V

OUT

DAC

VOUT

APPLICATION CIRCUITS

this value is the same as that which had been there
previously no change in the DAC's output is noticed.
Had the value held in the control register been different
from that stored in EEPROM then

a change would occur

at the read cycle's conclusion.

TEMPORARILY CHANGE OUTPUT

The CAT523 allows temporary changes in DAC's output
to be made without disturbing the settings retained in
EEPROM memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.

Figure 3 shows the control and data signals needed to
effect a temporary output change. DAC settings may be
changed as many times as required and can be made to
any of the four DACs in any order or sequence. The
temporary setting(s) remain in effect long as CS remains
high. When CS returns low all four DACs will return to the
output values stored in EEPROM memory.

When it is desired to save a new setting acquired using

Figure 3. Temporary Change in Output

this feature, the new value must be reloaded into the
DAC control register prior to programming. This is be-
cause the CAT523's internal control circuitry discards
the new data from the programming register two clock
cycles after receiving it (after reception is complete) if no
PROG signal is received.

NEW DAC DATA

CURRENT DAC DATA

PROG

DAC

OUTPUT

t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2

CURRENT

DAC VALUE

NON-VOLATILE

NEW

DAC VALUE

VOLATILE

CURRENT

DAC VALUE

NON-VOLATILE

Bipolar DAC Output

MSB LSB

1111 1111 ---- (.98 V ) + .01 V = .990 V V = +4.90V

1000 0000 ---- (.98 V ) + .01 V = .502 V V = +0.02V

0111 1111 ---- (.98 V ) + .01 V = .498 V V = -0.02V

0000 0001 ---- (.98 V ) + .01 V = .014 V V = -4.86V

0000 0000 ---- (.98 V ) + .01 V = .010 V V = -4.90V

REF

V = 5V

REF

255

OUT

DAC INPUT DAC OUTPUT ANALOG

R = R

OUTPUT

REF

OUT

128
255
127
255

REF

OUT

1
255

REF

OUT

REF

OUT

0
255

V = 0.99 V

REF

V = 0.01 V

ZERO

REF

V = ------ (V - V ) + V

DAC

CODE

255

ZERO

Amplified DAC Output

OPT 504

GND

VDD

V H

REF

V L

REF

CONTROL
& DATA

OP 07

OUT

-15V

+15V

+5V

V = (1 + ) V

OUT DAC

RF
R I

CAT523

CAT523

Advance Information

APPLICATION CIRCUITS (Cont.)

Coarse-Fine Offset Control by Averaging DAC Outputs

for Single Power Supply Systems

Coarse-Fine Offset Control by Averaging DAC Outputs

for Dual Power Supply Systems

FINE ADJUST

DAC

COARSE ADJUST

DAC

GND

V L

REF

V H

REF

VDD

127RC

+5V

VREF

R = ----------

256 1 µA

VREF

Fine adjust gives ± 1 LSB change in V

when V = ------

OFFSET

VREF

OFFSET

V OFFSET

FINE ADJUST

DAC

COARSE ADJUST

DAC

GND

V L

REF

V H

REF

VDD

127RC

+5V

REF

-V

REF

R = ----------------------

1 µA

OFFSET

VOFFSET

REF

(+V ) - (V )

R = ----------------------

1 µA

OFFSET

REF

(-V ) + (V )

Digitally Trimmed Voltage Reference

Digitally Controlled Voltage Reference

OPT 504

LT 1029

I > 2 mA

V+

GND

VDD

V = 5.000V

REF

V H

REF

V L

REF

CONTROL
& DATA

OPT 504

GND

VDD

V H

REF

V L

REF

CONTROL
& DATA

15K

10 µF

5.1V

10K

4.02 K

1.00K

10 µF
35V

LM 324

1N5231B

MPT3055EL

28 - 32V

OUTPUT

0 - 25V
@ 1A

CAT523

CAT523

Advance Information

APPLICATION CIRCUITS (Cont.)

Current Sink with 4 Decades of Resolution

Current Source with 4 Decades of Resolution

GND

V L

REF

VDD

REF

+5V

DAC

OPT 504

CONTROL
& DATA

DAC

10K

LM385-2.5

5 µA steps

I = 2 - 255 mA

SINK

2N7000

10K

TIP 30

5 meg

3.9K

-15V

2N7000

+5V

+15V

4.7 µA

1 mA steps

2.2K

GND

V L

REF

VDD

V H

REF

+5V

DAC

OPT 504

CONTROL
& DATA

DAC

5 meg

3.9K

LM385-2.5

-15V

5 µA steps

I = 2 - 255 mA

SOURCE

1 mA steps

10K

+15V

TIP 29

BS170P

51K

CAT523

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