DESCRIPTION

The CAT5419 is two Digitally Programmable
Potentiometers (DPPTM) integrated with control logic
and 16 bytes of NVRAM memory.

A separate 6-bit control register (WCR) independently
controls the wiper tap position for each DPP. Associated
with each wiper control register are four 6-bit non-
volatile memory data registers (DR) used for storing up
to four wiper settings. Writing to the wiper control register
or any of the non-volatile data registers is via a 2-wire
serial bus (I

C-like). On power-up, the contents of the

CAT5419

Dual Digitally Programmable Potentiometers (DPPTM) with
64 Taps and 2-wire Interface

FEATURES

Two linear-taper digital potentiometers

64 resistor taps per potentiometer

End-to-end resistance 2.5k

, 10k

, 50k

or 100k

Potentiometer control and memory access via
2-wire interface (I

C like)

Low wiper resistance, typically 80

Four non-volatile wiper settings for each
potentiometer

Recall of wiper settings at power up

2.5 to 6.0 volt operation

Standby current less than 1

1,000,000 nonvolatile WRITE cycles

100 year nonvolatile memory data retention

24-lead SOIC, 24-lead TSSOP and BGA

Write protection for data register

PIN CONFIGURATION

FUNCTIONAL DIAGRAM

Document No. 2115, Rev. F

first data register (DR0) for each of the two potentiometers
is automatically loaded into its respective wiper control
registers (WCR).

The Write Protection (

) pin protects against

inadvertent programming of the data register.

The CAT5419 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.

BGA

Top View - Bump Side Down

R R

WIPER

CONTROL

REGISTERS

NONVOLATILE

DATA

REGISTERS

2-WIRE BUS

INTERFACE

CONTROL

LOGIC

SCL

SDA

A0
A1
A2
A3

LOGEN FREE

LEAD FREE

1 2 3 4

RW0

RL1

RL0

SDA

RW1

VCC

RH0

RH1

VSS

SCL

CAT

5419

VCC

RL0

RH0

RW0

SDA

RL1

RH1

RW1

GND

SCL

CAT

5419

SDA

RL1

RH1

RW1

GND

SCL

RW0

RH0

RL0

VCC
NC

A0
NC

SOIC Package (J, W)

TSSOP Package (U, Y)

CAT5419

Document No. 2115, Rev. F

PIN DESCRIPTION

Pin

(TSSOP)

(SOIC)

(BGA) Name

Function

VCC

Supply Voltage

Low Reference Terminal

for Potentiometer 0

High Reference Terminal

for Potentiometer 0

Wiper Terminal for Potentiometer 0

Device Address

Write Protection

SDA

Serial Data Input/Output

Device Address

Low Reference Terminal

for Potentiometer 1

High Reference Terminal

for Potentiometer 1

Wiper Terminal for Potentiometer 1

GND

Ground

No Connect

SCL

Bus Serial Clock

Device Address

No Connect

Device Address, LSB

No Connect

PIN DESCRIPTIONS

SCL:

Serial Clock

The CAT5419 serial clock input pin is used to clock
all data transfers into or out of the device.

SDA:

Serial Data

The CAT5419 bidirectional serial data pin is used
to transfer data into and out of the device. The
SDA pin is an open drain output and can be wire-
OR'd with the other open drain or open collector
outputs.

A0, A1, A2, A3:

Device Address Inputs

These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus.
A match in the slave address must be made
with the address input in order to initiate
communication with the CAT5419.

, R

: Resistor End Points

The R

and R

pins are equivalent to the terminal

connections on a mechanical potentiometer.

Wiper

The R

pins are equivalent to the wiper terminal of

a mechanical potentiometer.

Write Protect Input

The

pin when tied low prevents non-volatile

writes to the data registers (change of wiper control
register is allowed) and when tied high or left
floating normal read/write operations are allowed.
See page 7, Write Protection for more details.

DEVICE OPERATION

The CAT5419 is two resistor arrays integrated with 2-
wire serial interface logic, four 6-bit wiper control registers
and sixteen 6-bit, non-volatile memory data registers.
Each resistor array contains 63 separate resistive
elements connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (R

and R

). R

and R

are

symmetrical and may be interchanged. The tap positions
between and at the ends of the series resistors are
connected to the output wiper terminals (R

) by a

CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a time
and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the 2-wire bus. Additional instructions allow data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.

CAT5419

Document No. 2115, Rev. F

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias .................. -55

C to +125

Storage Temperature ........................ -65

C to +150

Voltage on any Pin with

Respect to V

(1)(2)

................ -2.0V to +V

+2.0V

with Respect to Ground ................ -2.0V to +7.0V

Package Power Dissipation

Capability (T

= 25

C) ................................... 1.0W

Lead Soldering Temperature (10 secs) ............ 300

Wiper Current .................................................. +12mA

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2)

Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.

(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(4) LSB = R

TOT

/ 63 or (R

- R

) / 63, single pot

(5) n = 0, 1, 2, ..., 63

Note:

(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns.

Maximum DC voltage on output pins is V

+0.5V, which may overshoot to V

+2.0V for periods of less than 20 ns.

(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V

+1V.

*COMMENT
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions outside of those listed in the operational sections
of this specification is not implied. Exposure to any absolute
maximum rating for extended periods may affect device
performance and reliability.

Recommended Operating Conditions:

= +2.5V to +6.0V

Temperature

Min

Max

Industrial

-40

POTENTIOMETER CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

POT

Potentiometer Resistance (-00

)

100

POT

Potentiometer Resistance (-50

)

POT

Potentiometer Resistance (-10

)

POT

Potentiometer Resistance (-2.5

)

2.5

Potentiometer Resistance

+20

Tolerance

POT

Matching

Power Rating

C, each pot

Wiper Current

Wiper Resistance

= +3mA @ V

=3V

300

Wiper Resistance

= +3mA @ V

= 5V

150

TERM

Voltage on any R

or R

= 0V

GND

Noise

(1)

TBD

nV/ Hz

Resolution

1.6

Absolute Linearity

(2)

w(n)(actual)

-R

(n)(expected)

(5)

LSB

(4)

Relative Linearity

(3)

w(n+1)

-[R

w(n)+LSB

]

(5)

+0.2

LSB

(4)

Temperature Coefficient of

+300

ppm/

RPOT

POT

(1)

RATIO

Ratiometric Temp. Coefficient

(1)

ppm/

Potentiometer Capacitances

(1)

10/10/25

Frequency Response

POT

= 50k

(1)

0.4

MHz

CAT5419

Document No. 2115, Rev. F

Symbol

Parameter

Min

Typ

Max

Units

SCL

Clock Frequency

400

kHz

(1)

Noise Suppression Time Constant at SCL, SDA Inputs

SLC Low to SDA Data Out and ACK Out

0.9

BUF

(1)

Time the bus must be free before a new transmission can start

1.2

HD:STA

Start Condition Hold Time

0.6

LOW

Clock Low Period

1.2

HIGH

Clock High Period

0.6

SU:STA

Start Condition SetupTime (for a Repeated Start Condition)

0.6

HD:DAT

Data in Hold Time

SU:DAT

Data in Setup Time

100

(1)

SDA and SCL Rise Time

0.3

(1)

SDA and SCL Fall Time

300

SU:STO

Stop Condition Setup Time

0.6

Data Out Hold Time

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.

CAPACITANCE

= 25

C, f = 1.0 MHz, V

= 5V

Symbol

Test

Conditions

Min

Typ

Max

Units

I/O

(1)

Input/Output Capacitance (SDA)

I/O

= 0V

(1)

Input Capacitance (A0, A1, A2, A3, SCL,

)

= 0V

POWER UP TIMING

(1)

Over recommended operating conditions unless otherwise stated.

Symbol

Parameter

Min

Typ

Max

Units

PUR

Power-up to Read Operation

PUW

Power-up to Write Operation

D.C. OPERATING CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Power Supply Current

SCL

= 400kHz

Standby Current (V

= 5.0V)

= GND or V

CC;

SDA Open

Input Leakage Current

= GND to V

Output Leakage Current

OUT

= GND to V

Input Low Voltage

-1

x 0.3

Input High Voltage

x 0.7

+ 1.0

OL1

Output Low Voltage (V

= 3.0V)

= 3 mA

0.4

A.C. CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

CAT5419

Document No. 2115, Rev. F

WRITE CYCLE LIMITS

Over recommended operating conditions unless otherwise stated.

Symbol

Parameter

Min

Typ

Max

Units

Write Cycle Time

The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle,
the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

tHIGH

SCL

SDA IN

SDA OUT

tLOW

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA

tDH

Figure 1. Bus Timing

tWR

STOP
CONDITION

START
CONDITION

ADDRESS

ACK

8TH BIT

BYTE n

SCL

SDA

Figure 2. Write Cycle Timing

START BIT

SDA

STOP BIT

SCL

Figure 3. Start/Stop Timing

RELIABILITY CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol

Parameter

Reference Test Method

Min

Typ

Max

Units

END

(1)

Endurance

MIL-STD-883, Test Method 1033

1,000,000

Cycles/Byte

(1)

Data Retention

MIL-STD-883, Test Method 1008

100

Years

ZAP

(1)

ESD Susceptibility

MIL-STD-883, Test Method 3015

2000

Volts

LTH

(1)(2)

Latch-Up

JEDEC Standard 17

100

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t

PUR

and t

PUW

are the delays required from the time V

is stable until the specified operation can be initiated.

CAT5419

Document No. 2115, Rev. F

SERIAL BUS PROTOCOL

The following defines the features of the 2-wire bus
protocol:

(1) Data transfer may be initiated only when the bus

is not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any
changes in the data line while the clock is high will
be interpreted as a START or STOP condition.

The device controlling the transfer is a master,
typically a processor or controller, and the device
being controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
CAT5419 will be considered a slave device in all
applications.

START Condition

The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT5419 monitors the
SDA and SCL lines and will not respond until this
condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a
START condition. The Master then sends the address of

the particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
0101 for the CAT5419 (see Figure 5). The next four
significant bits (A3, A2, A1, A0) are the device address
bits and define which device the Master is accessing. Up
to sixteen devices may be individually addressed by the
system. Typically, +5V and ground are hard-wired to
these pins to establish the device's address.

After the Master sends a START condition and the slave
address byte, the CAT5419 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address.

Acknowledge

After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.

The CAT5419 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
8-bit byte.

When the CAT5419 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT5419 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.

ACKNOWLEDGE

START

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 4. Acknowledge Timing

CAT5419

Document No. 2115, Rev. F

WRITE OPERATIONS

In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the
requested operation of CAT5419. The instruction byte
consist of a four-bit opcode followed by two register
selection bits and two pot selection bits. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the selected register.
The CAT5419 acknowledges once more and the Master
generates the STOP condition, at which time if a non-
volatile data register is being selected, the device begins
an internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will not
respond to any request from the Master device.

Acknowledge Polling

The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is

issued to indicate the end of the host's write operation,
the CAT5419 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing
the start condition followed by the slave address. If the
CAT5419 is still busy with the write operation, no ACK
will be returned. If the CAT5419 has completed the write
operation, an ACK will be returned and the host can then
proceed with the next instruction operation.

WRITE PROTECTION

The Write Protection feature allows the user to protect
against inadvertent programming of the non-volatile
data registers. If the

pin is tied to LOW, the data

registers are protected and become read only. Similarly,

pin going LOW after Start will interrupt non-volatile

write to data registers, while

pin going LOW after

internal write cycle has started will have no effect on any
write operation.The CAT5419 will accept both slave
addresses and instructions, but the data registers are
protected from programming by the device's failure to
send an acknowledge after data is received.

Figure 6. Write Timing

Figure 5. Slave Address Bits

CAT5419

A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.

A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.

A
C
K

DR1 WCR DATA

S
T

BUS ACTIVITY:

MASTER

SDA LINE

S
T
A
R
T

A
C
K

SLAVE/DPP

ADDRESS

INSTRUCTION

BYTE

Fixed

Variable

op code

Data Register

Address

Pot/WCR

Address

CAT5419

Document No. 2115, Rev. F

INSTRUCTION AND REGISTER
DESCRIPTION

Instructions

SLAVE ADDRESS BYTE

The first byte sent to the CAT5419 from the master/
processor is called the Slave/DPP Address Byte. The
most significant four bits of the slave address are a
device type identifier. These bits for the CAT5419 are
fixed at 0101[B] (refer to Table 1).

The next four bits, A3 - A0, are the internal slave address
and must match the physical device address which is
defined by the state of the A3 - A0 input pins for the
CAT5419 to successfully continue the command
sequence. Only the device which slave address matches
the incoming device address sent by the master executes
the instruction. The A3 - A0 inputs can be actively driven
by CMOS input signals or tied to V

or V

INSTRUCTION BYTE

The next byte sent to the CAT5419 contains the instruction
and register pointer information. The four most significant
bits used provide the instruction opcode I [3:0]. The R1
and R0 bits point to one of the four data registers of each
associated potentiometer. The least two significant bits
point to one of two Wiper Control Registers. The format
is shown in Table 2.

Table 1. Identification Byte Format

ID3

ID2

ID1

ID0

(MSB)

(LSB)

Device Type

Identifier

Slave Address

Table 2. Instruction Byte Format

(MSB)

(LSB)

Instruction

Data Register

WCR/Pot Selection

Opcode

Selection

Data Register Selected

DR0

DR1

DR2

DR3

Data Register Selection

CAT5419

Document No. 2115, Rev. F

Table 3. Instruction Set

WIPER CONTROL AND DATA REGISTERS

Wiper Control Register (WCR)

The CAT5419 contains two 6-bit Wiper Control Registers,
one for each potentiometer. The Wiper Control Register
output is decoded to select one of 64 switches along its
resistor array. The contents of the WCR can be altered
in four ways: it may be written by the host via Write Wiper
Control Register instruction; it may be written by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction, it can be
modified one step at a time by the Increment/decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register
zero (DR0) upon power-up.

The Wiper Control Register is a volatile register that
loses its contents when the CAT5419 is powered-down.
Although the register is automatically loaded with the
value in DR0 upon power-up, this may be different from
the value present at power-down.

Data Registers (DR)

Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the

four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data Registers
is a non-volatile operation and will take a maximum of
5ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as standard memory locations for system
parameters or user preference data.

INSTRUCTIONS

Four of the nine instructions are three bytes in length.
These instructions are:

Read Wiper Control Register

- read the current

wiper position of the selected potentiometer in the WCR

-- Write Wiper Control Register - change current

wiper position in the WCR of the selected potentiometer

-- Read Data Register - read the contents of the

selected Data Register

-- Write Data Register - write a new value to the

selected Data Register

The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions

Note:

1/0 = data is one or zero

Instruction

Instruction Set

Operation

Read Wiper Control
Register

1/0

Read the contents of the Wiper Control
Register pointed to by P0

Write Wiper Control Register

1/0

Write new value to the Wiper Control
Register pointed to by P0

Read Data Register

1/0

Read the contents of the Data Register
pointed to by P0 and R1-R0

Write Data Register

1/0

Write new value to the Data Register
pointed to by P0 and R1-R0

XFR Data Register to Wiper
Control Register

1/0

Transfer the contents of the Data Register
pointed to by P0 and R1-R0 to its
associated Wiper Control Register

XFR Wiper Control Register
to Data Register

1/0

Transfer the contents of the Wiper Control
Register pointed to by P0 to the Data
Register pointed to by R1-R0

Gang XFR Data Registers
to Wiper Control Registers

1/0

Transfer the contents of the Data Registers
pointed to by R1-R0 of both pots to their
respective Wiper Control Register

Gang XFR Wiper Control
Registers to Data Register

1/0

Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1-R0 of both pots

Increment/Decrement Wiper
Control Register

1/0

Enable Increment/decrement of the Control
Latch pointed to by P0

WCR0/

CAT5419

Document No. 2115, Rev. F

exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be delayed
by t

WRL

. A transfer from the WCR (current wiper position),

to a Data Register is a write to non-volatile memory and
takes a maximum of t

to complete. The transfer can

occur between one of the potentiometers and one of its
associated registers; or the transfer can occur between
all potentiometers and one associated register.

Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
CAT5419; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:

XFR Data Register to Wiper Control Register

This transfers the contents of one specified Data
Register to the associated Wiper Control Register.

-- XFR Wiper Control Register to Data Register

This transfers the contents of the specified Wiper
Control Register to the specified associated
Data Register.

-- Global XFR Data Register to Wiper

Control Register
This transfers the contents of specified Data
Registers to the associated Wiper Control
Registers.

-- Global XFR Wiper Counter Register to

Data Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (Figure 5
and 9). The Increment/Decrement command is different
from the other commands. Once the command is issued
and the CAT5419 has responded with an acknowledge,
the master can clock the selected wiper up and/or down
in one segment steps; thereby providing a fine tuning
capability to the host. For each SCL clock pulse (t

HIGH

)

while SDA is HIGH, the selected wiper will move one
resistor segment towards the R

terminal. Similarly, for

each SCL clock pulse while SDA is LOW, the selected
wiper will move one resistor segment towards the R

terminal.

See Instructions format for more detail.

Figure 7. Two-Byte Instruction Sequence

Figure 8. Three-Byte Instruction Sequence

Figure 9. Increment/Decrement Instruction Sequence

R
T

R1 R0

SDA

S
T

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction
Opcode

Address

Pot/WCR

Address

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction
Opcode

Address

Data
Register
Address

Pot/WCR

Address

S
T

A
R
T

A2 A1 A0

A
C

R0 0

A
C

SDA

S
T

D
E

R1 R0

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction
Opcode

Address

Data
Register
Address

Pot/WCR

Address

WCR[7:0]

Data Register D[7:0]

R
T

P0 A

SDA

D6 D5 D4 D3 D2

D1 D0

CAT5419

Document No. 2115, Rev. F

Figure 10. Increment/Decrement Timing Limits

INSTRUCTION FORMAT

Read Wiper Control Register (WCR)

Write Wiper Control Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

SCL

SDA

INC/DEC

Command

Issued

Voltage Out

WRID

DEVICE ADDRESSES

INSTRUCTION

DATA

1 0 1 A3 A2 A1 A0

1 0 0 1 0 0 0 P0

7 6

2 1 0

0 0

S
T
A
R
T

A
C
K

S
T
O
P

DEVICE ADDRESSES

INSTRUCTION

DATA

1 0 1 A3 A2 A1 A0

1 0 1 0 0 0 0 P0

7 6

2 1 0

0 0

S
T
A
R
T

A
C
K

S
T
O
P

DEVICE ADDRESS

INSTRUCTION

DATA

1 0 1 A3 A2A1 A0

1 1 0 0 R1 R0 0 P0

2 1 0

S
T
A
R
T

A
C
K

S
T
O
P

DEVICE ADDRESS

INSTRUCTION

DATA

1 0 1 A3 A2A1 A0

1 0 1

1 R1 R0 0 P0

2 1 0

S
T
A
R
T

A
C
K

S
T
O
P

CAT5419

Document No. 2115, Rev. F

DEVICE ADDRESS

INSTRUCTION

0 1 0 1 A3 A2 A1 A0

1 1 0 1 R1 R0 0 P0

DEVICE ADDRESS

INSTRUCTION

0 1 0 1 A3 A2 A1 A0

1 1 1 0 R1 R0 0 P0

DEVICE ADDRESS

INSTRUCTION

0 1 0 1 A3 A2 A1 A0

1 0 0 0 R1 R0 0 0

Global Transfer Wiper Control Register (WCR) to Data Register (DR)

INSTRUCTION FORMAT

(continued)

Transfer Wiper Control Register (WCR) to Data Register (DR)

S
T
A
R
T

A
C
K

S
T
O
P

Transfer Data Register (DR) to Wiper Control Register (WCR)

S
T
A
R
T

A
C
K

S
T
O
P

Notes:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.

Global Transfer Data Register (DR) to Wiper Control Register (WCR)

A
C
K

S
T
O
P

S
T
A
R
T

DEVICE ADDRESS

INSTRUCTION

DATA

1 0 1 A3 A2 A1 A0

0 0 1 0 0 0 0 P0

I/D I/D

Increment (I)/Decrement (D) Wiper Control Register (WCR)

S
T
A
R
T

A
C
K

S
T
O
P

· · ·

DEVICE ADDRESS

INSTRUCTION

0 1 0 1 A3 A2 A1 A0

0 0 0 1 R1 R0 0 0

A
C
K

S
T
O
P

S
T
A
R
T

CAT5419

Document No. 2115, Rev. F

PACKAGING INFORMATION CON'T

24 Ball BGA

1 2 3 4

Top View (Bump Side Down)

4 3 2 1

Bottom View (Bump Side Up)

Note: Drawing not to scale
= Die orientation mark

Side View (Bump Side Down)

Millimeters

Inches

Symbol

Min

Nom

Max

Nom

Min

Max

Package Body Dimension X

TBD

Package Body Dimension Y

TBD

Package Height

0.635

0.505

0.765

0.02500

0.01988

0.03012

Package Body Thickness

0.433

0.395

0.471

0.01705

0.01555

0.01854

Ball Height

0.202

0.110

0.294

0.00795

0.00433

0.01157

Ball Diameter

0.284

0.180

0.388

0.01118

0.00709

0.01528

Total Ball Count

Ball Count X Axis

Ball Count Y Axis

Pins Pitch X Axis

0.5

Pins Pitch Y Axis

0.5

Edge to Ball Center (Corner)

Distance Along X

TBD

Edge to Ball Center (Corner)

Distance Along Y

TBD

Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com

Publication #:

2115

Revison:

Issue date:

04/02/04

Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP TM

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CAT5269J-00TE13

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CAT5269J-00TE13