DESCRIPTION

The CAT5411 is two Digitally Programmable
Potentiometers (DPPsTM) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of 63 resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 6-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the

CAT5411

Dual Digitally Programmable Potentiometers (DPPTM) with
64 Taps and SPI Interface

FEATURES

Two linear-taper digitally programmable

potentiometers

64 resistor taps per potentiometer

End to end resistance 2.5k

, 10k

, 50k

or 100k

Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)

Low wiper resistance, typically 80

Nonvolatile memory storage for up to four wiper
settings for each potentiometer

Automatic recall of saved wiper settings at
power up

2.5 to 6.0 volt operation

Standby current less than 1

1,000,000 nonvolatile WRITE cycles

100 year nonvolatile memory data retention

24-lead SOIC, 24-lead TSSOP, and BGA

Industrial temperature ranges

PIN CONFIGURATION

FUNCTIONAL DIAGRAM

Document No. 2114, Rev. G

wiper control register or any of the non-volatile data
registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the
two potentiometers is automatically loaded into its
respective wiper control register.

The CAT5411 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.

BGA

Top View - Bump Side Down

R R

WIPER

CONTROL

REGISTERS

NONVOLATILE

DATA

REGISTERS

SPI BUS

INTERFACE

CONTROL

LOGIC

SCK

A0
A1

LOGEN FREE

LEAD FREE

1 2 3 4

RW0

RL1

RL0

RW1

VCC

RH0

RH1

VSS

HOLD

SCK

CAT

5411

VCC

RL0

RH0

RW0

RL1

RH1

RW1

GND

HOLD

SCK

CAT

5411

RL1

RH1

RW1

GND

SCK

HOLD

RW0

RH0

RL0

VCC
NC

A0
SO

SOIC Package (J, W)TSSOP Package (U, Y)

CAT5411

Document No. 2114, Rev. F

takes the SO output pin to high impedance and forces the devices into a Standby mode (unless an internal write operation is
underway). The CAT5411 draws ZERO current in the Standby mode. A high to low transition on

is required prior to any

sequence being initiated. A low to high transition on

after a valid write sequence is what initiates an internal write cycle.

Write Protect

is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When

is tied low, all

non-volatile write operations to the Data registers are inhibited (change of wiper control register is allowed).

going low while

is still low will interrupt a write to the registers. If the internal write cycle has already been initiated,

going low will have no

effect on any write operation.

HOLD

Hold

The

HOLD

pin is used to pause transmission to the CAT5411 while in the middle of a serial sequence without having to re-

transmit entire sequence at a later time. To pause,

HOLD

must be brought low while SCK is low. The SO pin is in a high imped-

ance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication,

HOLD

brought high, while SCK is low. (

HOLD

should be held high any time this function is not being used.)

HOLD

may be tied high

directly to VCC or tied to VCC through a resistor.

PIN DESCRIPTIONS

SI:

Serial Input

SI is the serial data input pin. This pin is used to input
all opcodes, byte addresses and data to be written to
the CAT5411. Input data is latched on the rising edge
of the serial clock.

SO:

Serial Output

SO is the serial data output pin. This pin is used to
transfer data out of the CAT5411. During a read
cycle, data is shifted out on the falling edge of the
serial clock.

SCK:

Serial Clock

SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5411. Opcodes, byte
addresses or data present on the SI pin are latched
on the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.

A0, A1: Device Address Inputs

These inputs set the device address when address-
ing multiple devices. A total of four devices can be
addressed on a single bus. A match in the slave
address must be made with the address input in
order to initiate communication with the CAT5411.

, R

: Resistor End Points

The R

and R

pins are equivalent to the terminal

connections on a mechanical potentiometer.

Wiper

The R

pins are equivalent to the wiper terminal of a

mechanical potentiometer.

Chip Select

is the Chip select pin.

low enables the

CAT5411 and

high disables the CAT5411.

high

PIN DESCRIPTION

Pin

(SOIC)(TSSOP)(BGA)Name

Function

VCC

Supply Voltage

Low Reference Terminal

for Potentiometer 0

High Reference Terminal

for Potentiometer 0

Wiper Terminal for Potentiometer 0

Chip Select

Write Protection

Serial Input

Device Address

Low Reference Terminal

for Potentiometer 1

High Reference Terminal

for Potentiometer 1

Wiper Terminal for Potentiometer 1

GND

Ground

No Connect

SCK

Bus Serial Clock

HOLD

Hold

Serial Data Output

Device Address, LSB

No Connect

CAT5411

Document No. 2114, Rev. G

DEVICE OPERATION

The CAT5411 is two resistor arrays integrated with SPI
serial interface logic, four 6-bit wiper control registers
and eight 6-bit, non-volatile memory data registers.
Each resistor array contains 63 separate resistive
elements connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (R

and R

). R

and

are

symmetrical and may be interchanged. The tap positions
between and at the ends of the series resistors are
connected to the output wiper terminals (R

) by a

CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a time
and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the SPI bus. Additional instructions allows data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.

SERIAL BUS PROTOCOL

The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5411 to interface directly with many
of today's popular microcontrollers. The CAT5041
contains an 8-bit instruction register .The instruction set
and the operation codes are detailed in the instruction
set table

After the device is selected with

going low the first

byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK. The
first byte contains one of the six op-codes that define the
operation to be performed.

CAT5411

Document No. 2114, Rev. F

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2)

Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.

(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(4) LSB = R

TOT

/ 63 or (R

- R

) / 63, single pot

(5) n = 0, 1, 2, ..., 63

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias .................. -55

C to +125

Storage Temperature ........................ -65

C to +150

Voltage on any Pin with

Respect to V

(1)(2)

................ -2.0V to +V

+2.0V

with Respect to Ground ................ -2.0V to +7.0V

Package Power Dissipation

Capability (T

= 25

C) ................................... 1.0W

Lead Soldering Temperature (10 secs) ............ 300

Wiper Current .................................................. +12mA

Note:

(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns.

Maximum DC voltage on output pins is V

+0.5V, which may overshoot to V

+2.0V for periods of less than 20 ns.

(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V

+1V.

*COMMENT
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions outside of those listed in the operational sections
of this specification is not implied. Exposure to any absolute
maximum rating for extended periods may affect device perfor-
mance and reliability.

Recommended Operating Conditions:

= +2.5V to +6.0V

Temperature

Min

Max

Industrial

-40

POTENTIOMETER CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

POT

Potentiometer Resistance (-00

)

100

POT

Potentiometer Resistance (-50

)

POT

Potentiometer Resistance (-10

)

POT

Potentiometer Resistance (-2.5

)

2.5

Potentiometer Resistance

+20

Tolerance

POT

Matching

Power Rating

C, each pot

Wiper Current

Wiper Resistance

= +3mA @ V

=3V

300

Wiper Resistance

= +3mA @ V

= 5V

150

TERM

Voltage on any R

or R

= 0V

GND

Noise

(1)

nV/ Hz

Resolution

1.6

Absolute Linearity

(2)

w(n)(actual)

-R

(n)(expected)

(5)

LSB

(4)

Relative Linearity

(3)

w(n+1)

-[R

w(n)+LSB

]

(5)

+0.2

LSB

(4)

Temperature Coefficient of

+300

ppm/

RPOT

POT

(1)

RATIO

Ratiometric Temp. Coefficient

(1)

ppm/

Potentiometer Capacitances

(1)

10/10/25

Frequency Response

POT

= 50k

(1)

0.4

MHz

CAT5411

Document No. 2114, Rev. G

D.C. OPERATING CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Power Supply Current

SCK

= 2MHz, SO Open

Inputs = GND

Standby Current (V

= 5.0V)

= GND or V

CC;

SO Open

Input Leakage Current

= GND to V

Output Leakage Current

OUT

= GND to V

Input Low Voltage

-1

x 0.3

Input High Voltage

x 0.7

+ 1.0

OL1

Output Low Voltage (V

= 3.0V)

= 3 mA

0.4

PIN CAPACITANCE

(1)

Applicable over recommended operating range from T

=25°C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).

Symbol

Test Conditions

Min

Typ

Max

Units

Conditions

OUT

Output Capacitance (SO)

OUT

=0V

Input Capacitance (

, SCK, SI,

HOLD

)

=0V

CAT5411

Document No. 2114, Rev. F

Test

SYMBOL

PARAMETER

Min

Typ

Max

UNITS

Conditions

Data Setup Time

Data Hold Time

SCK High Time

125

SCK Low Time

125

SCK

Clock Frequency

MHz

HOLD

to Output Low Z

(1)

Input Rise Time

(1)

Input Fall Time

HOLD

Setup Time

100

HOLD

Hold Time

100

Write Cycle Time

Output Valid from Clock Low

250

Output Hold Time

DIS

Output Disable Time

250

HOLD

to Output High Z

100

High Time

250

CSS

Setup Time

250

CSH

Hold Time

250

NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.

POWER UP TIMING

(1)

Over recommended operating conditions unless otherwise stated.

Symbol

Parameter

Min

Typ

Max

Units

PUR

Power-up to Read Operation

PUW

Power-up to Write Operation

A.C. CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

= 50pF

CAT5411

Document No. 2114, Rev. G

WRITE CYCLE LIMITS

Over recommended operating conditions unless otherwise stated.

Symbol

Parameter

Min

Typ

Max

Units

Write Cycle Time

Figure 1. Sychronous Data Timing

Figure 2.

HOLD

Timing

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t

PUR

and t

PUW

are the delays required from the time V

is stable until the specified operation can be initiated.

RELIABILITY CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol

Parameter

Reference Test Method

Min

Typ

Max

Units

END

(1)

Endurance

MIL-STD-883, Test Method 1033

1,000,000

Cycles/Byte

(1)

Data Retention

MIL-STD-883, Test Method 1008

100

Years

ZAP

(1)

ESD Susceptibility

MIL-STD-883, Test Method 3015

2000

Volts

LTH

(1)(2)

Latch-Up

JEDEC Standard 17

100

Note: Dashed Line= mode (1, 1) -- -- -- --

VALID IN

CSS

VIL

HI-Z

CSH

DIS

HI-Z

SCK

tFI

SCK

HOLD

tCD

tHD

tCD

tLZ

tHZ

HIGH IMPEDANCE

CAT5411

Document No. 2114, Rev. F

INSTRUCTION AND REGISTER
DESCRIPTION

DEVICE TYPE / ADDRESS BYTE

The first byte sent to the CAT5411 from the master/
processor is called the Device Address Byte. The most
significant four bits of the Device Type address are a
device type identifier. These bits for the CAT5411 are
fixed at 0101[B] (refer to Table 1).

The two least significant bits in the slave address byte,
A1 - A0, are the internal slave address and must match
the physical device address which is defined by the state
of the A1 - A0 input pins for the CAT5411 to successfully
continue the command sequence. Only the device which
slave address matches the incoming device address
sent by the master executes the instruction. The A1 - A0
inputs can be actively driven by CMOS input signals or
tied to V

or V

. The remaining two bits in the device

address byte must be set to 0.

INSTRUCTION BYTE

The next byte sent to the CAT5411 contains the instruction
and register pointer information. The four most significant
bits used provide the instruction opcode I [3:0]. The R1
and R0 bits point to one of the four data registers of each
associated potentiometer. The least two significant bits
point to one of two Wiper Control Registers. The format
is shown in Table 2.

Table 1. Identification Byte Format

ID3

ID2

ID1

ID0

(MSB)

(LSB)

Device Type

Identifier

Slave Address

Table 2. Instruction Byte Format

Data Register Selected

DR0

DR1

DR2

DR3

Data Register Selection

(MSB)

(LSB)

Instruction

Data Register

WCR/Pot Selection

Opcode

Selection

CAT5411

Document No. 2114, Rev. G

Table 3. Instruction Set

WIPER CONTROL AND DATA REGISTERS

Wiper Control Register (WCR)

The CAT5411 contains two 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of 64
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written by
the host via Write Wiper Control Register instruction;
it may be written by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction, it can be modified one step at a
time by the Increment/decrement instruction (see
Instruction section for more details). Finally, it is
loaded with the content of its data register zero (DR0)
upon power-up.

The Wiper Control Register is a volatile register that
loses its contents when the CAT5411 is powered-down.
Although the register is automatically loaded with the
value in DR0 upon power-up, this may be different from
the value present at power-down.

Data Registers (DR)

Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the

four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data Registers
is a non-volatile operation and will take a maximum of
5ms.

Write in Process

The contents of the Data Registers are saved to
nonvolatile memory when the CS input goes HIGH after
a write sequence is received. The status of the internal
write cycle can be monitored by issuing a Read Status
command to read the Write in Process (WIP) bit.

INSTRUCTIONS

Five of the ten instructions are three bytes in length.
These instructions are:

Read Wiper Control Register

- read the current

wiper position of the selected potentiometer in the WCR

-- Write Wiper Control Register - change current

wiper position in the WCR of the selected potentiometer

-- Read Data Register - read the contents of the

selected Data Register

-- Write Data Register - write a new value to the

selected Data Register

-- Read Status - Read the status of the WIP bit which

Note:

1/0 = data is one or zero

Instruction

Instruction Set

Operation

Read Wiper Control
Register

1/0

Read the contents of the Wiper Control
Register pointed to by P0

Write Wiper Control Register

1/0

Write new value to the Wiper Control
Register pointed to by P0

Read Data Register

1/0

Read the contents of the Data Register
pointed to by P0 and R1-R0

Write Data Register

1/0

Write new value to the Data Register
pointed to by P0 and R1-R0

XFR Data Register to Wiper
Control Register

1/0

Transfer the contents of the Data Register
pointed to by P0 and R1-R0 to its
associated Wiper Control Register

XFR Wiper Control Register
to Data Register

1/0

Transfer the contents of the Wiper Control
Register pointed to by P0 to the Data
Register pointed to by R1-R0

Global XFR Data Registers
to Wiper Control Registers

1/0

Transfer the contents of the Data Registers
pointed to by R1-R0 of all four pots to their
respective Wiper Control Register

Global XFR Wiper Control
Registers to Data Register

1/0

Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1-R0 of all four pots

Increment/Decrement Wiper
Control Register

1/0

Enable Increment/decrement of the Control
Latch pointed to by P0

WCR0/

Read Status (WIP bit)

Read WIP bit to check internal
write cycle status

CAT5411

Document No. 2114, Rev. F

when set to "1" signifies a write cycle is in progress.

The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be delayed
by t

WRL

. A transfer from the WCR (current wiper position),

to a Data Register is a write to non-volatile memory and
takes a minimum of t

to complete. The transfer can

occur between one of the potentiometers and one of its
associated registers; or the transfer can occur between
both potentiometers and one associated register.

Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
CAT5411; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:

XFR Data Register to Wiper Control Register

This transfers the contents of one specified Data
Register to the associated Wiper Control Register.

-- XFR Wiper Control Register to Data Register

This transfers the contents of the specified Wiper
Control Register to the specified associated
Data Register.

-- Global XFR Data Register to Wiper

Control Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.

-- Global XFR Wiper Counter Register to

Data Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (Figure 5
and 9). The Increment/Decrement command is different
from the other commands. Once the command is issued
the master can clock the selected wiper up and/or down
in one segment steps; thereby providing a fine tuning
capability to the host. For each SCK clock pulse (t

HIGH

)

while SI is HIGH, the selected wiper will move one
resistor segment towards the R

terminal. Similarly, for

each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the R

terminal.

See Instructions format for more detail.

Figure 7. Two-Byte Instruction Sequence

Figure 8. Three-Byte Instruction Sequence

Figure 9. Increment/Decrement Instruction Sequence

R1 R0 0

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction

Opcode

Address

Pot/WCR

Address

R1 R0

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction
Opcode

Address

Data
Register
Address

Pot/WCR

Address

WCR[7:0]

Data Register D[7:0]

D6 D5 D4 D3 D2

D1 D0

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction
Opcode

Address

Data
Register
Address

Pot/WCR

Address

A2 A1 A0

R0 0

D
E

CAT5411

Document No. 2114, Rev. G

Figure 10. Increment/Decrement Timing Limits

INSTRUCTION FORMAT

Read Wiper Control Register (WCR)

Write Wiper Control Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

SCK

INC/DEC

Command

Issued

Voltage Out

WRID

Read (WIP) Status

DEVICE ADDRESSES INSTRUCTION

DATA

1 0 1 0 0 A1 A0 1 0 0 1 0 0 0 P0 7

6 5 4 3 2 1 0

DEVICE ADDRESSES INSTRUCTION

DATA

1 0 1 0 0 A1 A0 1 0 0 1 0 0 0 P0 7

6 5 4 3 2 1 0

DEVICE ADDRESSES INSTRUCTION

DATA

1 0 1 0 0 A1 A0 1 0 1 1 R1 R0 0 P0 7 6

4 3

2 1

DEVICE ADDRESSES INSTRUCTION

DATA

1 0 1 0 0 A1 A0 1 1 0 0 R1 R0 0 P0 7 6

4 3

2 1

High Voltage

Write Cycle

DEVICE ADDRESSES INSTRUCTION

DATA

1 0 1 0

0 A1 A0 0 1 0 1 0 0 0 1 7 6 5 4 3 2 1

0 0 0 0 0 0 0

CAT5411

Document No. 2114, Rev. F

Global Transfer Wiper Control Register (WCR) to Data Register (DR)

INSTRUCTION FORMAT

(continued)

Transfer Wiper Control Register (WCR) to Data Register (DR)

Transfer Data Register (DR) to Wiper Control Register (WCR)

Notes:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after

goes high.

Global Transfer Data Register (DR) to Wiper Control Register (WCR)

Increment (I)/Decrement (D) Wiper Control Register (WCR)

DEVICE ADDRESSES INSTRUCTION

1 0 1

0 0 A1 A0 0 0

0 1 R1 R0 0 0

DEVICE ADDRESSES INSTRUCTION

1 0 1

0 0 A1 A0 1 0

0 0 R1 R0 0 0

High Voltage

Write Cycle

DEVICE ADDRESSES INSTRUCTION

1 0 1

0 0 A1 A0 1 1

1 0 R1 R0 0 P0

High Voltage

Write Cycle

DEVICE ADDRESSES INSTRUCTION

1 0 1 0

0 A1 A0 1 1 0 1 R1 R0 0 P0

DEVICE ADDRESSES INSTRUCTION

DATA

1 0 1 0

0 A1 A0 0 0 1 0 0 0 0 P0 I/D I/D

I/D I/D

· · ·

CAT5411

Document No. 2114, Rev. G

Notes:
(1) The device used in the above example is a CAT5411JI-10-TE13 (SOIC, Industrial Temperature, 10kohm, Tape & Reel)

ORDERING INFORMATION

24-LEAD 300 MIL WIDE SOIC (J)

0.2914 (7.40)
0.2992 (7.60)

0.394 (10.00)
0.419 (10.65)

0.0926 (2.35)
0.1043 (2.65)

0.0040 (0.10)
0.0118 (0.30)

0.050 (1.27) BSC

0.013 (0.33)
0.020 (0.51)

0 --8

0.0091 (0.23)
0.0125 (0.32)

0.010 (0.25)
0.029 (0.75)

X 45

0.016 (0.40)
0.050 (1.27)

0.5985 (15.20)
0.6141 (15.60)

PACKAGING INFORMATION

Prefix

Device #

Suffix

5411

Product
Number

CAT

Optional
Company ID

Temperature Range
I = Industrial (-40 C to 85 C)

-TE13

Tape & Reel
TE13: 2000/Reel

-10

Resistance

-25: 2.5kohm
-10: 10kohm
-50: 50kohm
-00: 100kohm

Package

J: SOIC
B: BGA
U: TSSOP
W: SOIC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)

CAT5411

Document No. 2114, Rev. G

Millimeters

Inches

Symbol

Min

Nom

Max

Nom

Min

Max

Package Body Dimension X

TBD

Package Body Dimension Y

TBD

Package Height

0.635

0.505

0.765

0.02500

0.01988

0.03012

Package Body Thickness

0.433

0.395

0.471

0.01705

0.01555

0.01854

Ball Height

0.202

0.110

0.294

0.00795

0.00433

0.01157

Ball Diameter

0.284

0.180

0.388

0.01118

0.00709

0.01528

Total Ball Count

Ball Count X Axis

Ball Count Y Axis

Pins Pitch X Axis

0.5

Pins Pitch Y Axis

0.5

Edge to Ball Center (Corner)

Distance Along X

TBD

Edge to Ball Center (Corner)

Distance Along Y

TBD

PACKAGING INFORMATION CON'T

24 Ball BGA

1 2 3 4

Top View (Bump Side Down)

4 3 2 1

Bottom View (Bump Side Up)

Note: Drawing not to scale
= Die orientation mark

Side View (Bump Side Down)

Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com

Publication #:

2114

Revison:

Issue date:

4/01/04

Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP TM

DPPs TM

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.

REVISION HISTORY

Date

Rev.

Reason

04/01/04

Eliminate data sheet designation
Update Features

Update Description
Update Pin Description
Update Absolute Maximum Ratings
Update Recommended Operating Conditions
Update Potentiometer Characteristics
Update Reliability Characteristics
Update Ordering Information

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CAT5411YI-50-TE13

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CAT5411YI-50-TE13