CAT93C46/56/57/66/86
1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM
FEATURES
s
High speed operation:
93C46/56/57/66: 1MHz
93C86: 3MHz
s
Low power CMOS technology
s
1.8 to 6.0 volt operation
s
Selectable x8 or x16 memory organization
s
Self-timed write cycle with auto-clear
s
Hardware and software write protection
s
Power-up inadvertant write protection
s
1,000,000 Program/erase cycles
s
100 year data retention
s
Commercial, industrial and automotive
temperature ranges
s
Sequential read (except CAT93C46)
s
Program enable (PE) pin (CAT93C86 only)
s
"Green" package option available
93C46/56/57/66/86 F02
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J,W)
CMOS EEPROM floating gate technology. The devices
are designed to endure 1,000,000 program/erase cycles
and have a data retention of 100 years. The devices are
available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP
packages.
DESCRIPTION
The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit
Serial EEPROM memory devices which are configured
as either registers of 16 bits (ORG pin at V
CC
) or 8 bits
(ORG pin at GND). Each register can be written (or read)
serially by using the DI (or DO) pin. The CAT93C46/56/
57/66/86 are manufactured using Catalyst's advanced
SOIC Package (S,V)
93C46/56/57/66/86
F01
PIN FUNCTIONS
Pin Name
Function
CS
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
V
CC
+1.8 to 6.0V Power Supply
GND
Ground
ORG
Memory Organization
NC
No Connection
PE*
Program Enable
BLOCK DIAGRAM
Note: When the ORG pin is connected to VCC, the x16 organiza-
tion is selected. When it is connected to ground, the x8 pin
is selected. If the ORG pin is left unconnected, then an
internal pullup device will select the x16 organization.
SOIC Package (K,X)
2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
TSSOP Package (U,Y)**
*Only For 93C86 ** TSSOP (U/Y) package only available for 93C46/56/57/66
8
7
6
5
VCC
ORG
GND
DI
CS
SK
DO
1
2
3
4
NC (PE*)
VCC
ADDRESS
DECODER
MEMORY ARRAY
ORGANIZATION
DATA
REGISTER
MODE DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO
SK
CS
DI
ORG
GND
PE*
Doc. No. 1023, Rev. G
HA
LOGEN FREE
TM
LEAD FREE
CS
SK
DI
DO
VCC
NC (PE*)
ORG
GND
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
ORG
GND
1
2
3
4
8
7
6
5
VCC
CS
SK
ORG
GND
DO
DI
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
ORG
GND
1
2
3
4
8
7
6
5
NC (PE*)
NC (PE*)
NC (PE*)
2
93C46/56/57/66/86
Doc. No. 1023, Rev. G
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
I
CC1
Power Supply Current
f
SK
= 1MHz
3
mA
(Operating Write)
V
CC
= 5.0V
I
CC2
Power Supply Current
f
SK
= 1MHz
500
A
(Operating Read)
V
CC
= 5.0V
I
SB1
Power Supply Current
CS = 0V
10
A
(Standby) (x8 Mode)
ORG=GND
I
SB2
(5)
Power Supply Current
CS=0V
0
A
(Standby) (x16Mode)
ORG=Float or V
CC
I
LI
Input Leakage Current
V
IN
= 0V to V
CC
1
A
I
LO
Output Leakage Current
V
OUT
= 0V to V
CC
,
1
A
(Including ORG pin)
CS = 0V
V
IL1
Input Low Voltage
4.5V
V
CC
< 5.5V
-0.1
0.8
V
V
IH1
Input High Voltage
4.5V
V
CC
< 5.5V
2
V
CC
+ 1
V
V
IL2
Input Low Voltage
1.8V
V
CC
< 4.5V
0
V
CC
x 0.2
V
V
IH2
Input High Voltage
4.8V
V
CC
< 4.5V
V
CC
x 0.7
V
CC
+1
V
V
OL1
Output Low Voltage
4.5V
V
CC
< 5.5V
0.4
V
I
OL
= 2.1mA
V
OH1
Output High Voltage
4.5V
V
CC
< 5.5V
2.4
V
I
OH
= -400
A
V
OL2
Output Low Voltage
1.8V
V
CC
< 4.5V
0.2
V
I
OL
= 1mA
V
OH2
Output High Voltage
1.8V
V
CC
< 4.5V
V
CC
- 0.2
V
I
OH
= -100
A
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55
C to +125
C
Storage Temperature ........................ -65
C to +150
C
Voltage on any Pin with
Respect to Ground
(1)
............. -2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25
C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(2)
........................ 100 mA
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Typ
Max
Units
N
END
(3)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
T
DR
(3)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
V
ZAP
(3)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
I
LTH
(3)(4)
Latch-Up
JEDEC Standard 17
100
mA
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V
CC
+1V.
(5) Standby Current (ISB
2
)=0
A (<900nA) for 93C46/56/57/66, (ISB
2
)=2
A for 93C86.
3
93C46/56/57/66/86
Doc. No. 1023, Rev. G
PIN CAPACITANCE
Symbol
Test
Conditions
Min
Typ
Max
Units
C
OUT
(3)
Output Capacitance (DO)
V
OUT
=0V
5
pF
C
IN
(3)
Input Capacitance (CS, SK, DI, ORG)
V
IN
=0V
5
pF
Note:
(1)
Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE
and ERASE commands.
(2)
Applicable only to 93C86
(3)
This parameter is tested initially and after a design or process change that affects the parameter.
INSTRUCTION SET
Instruction Device
Start Opcode
Address Data
Comments
PE
(2)
Type
Bit
x8
x16
x8
x16
READ
93C46
1
10
A6-A0
A5-A0
Read Address ANA0
93C56
(1)
1
10
A8-A0
A7-A0
93C66
1
10
A8-A0
A7-A0
93C57
1
10
A7-A0
A6-A0
93C86
1
10
A10-A0
A9-A0
X
ERASE
93C46
1
11
A6-A0
A5-A0
Clear Address ANA0
93C56
(1)
1
11
A8-A0
A7-A0
93C66
1
11
A8-A0
A7-A0
93C57
1
11
A7-A0
A6-A0
93C86
1
11
A10-A0
A9-A0
I
WRITE
93C46
1
01
A6-A0
A5-A0
D7-D0 D15-D0
Write Address ANA0
93C56
(1)
1
01
A8-A0
A7-A0
D7-D0 D15-D0
93C66
1
01
A8-A0
A7-A0
D7-D0 D15-D0
93C57
1
01
A7-A0
A6-A0
D7-D0 D15-D0
93C86
1
01
A10-A0
A9-A0
D7-D0 D15-D0
I
EWEN
93C46
1
00
11XXXXX
11XXXX
Write Enable
93C56
1
00
11XXXXXXX
11XXXXXX
93C66
1
00
11XXXXXXX
11XXXXXX
93C57
1
00
11XXXXXX
11XXXXX
93C86
1
00
11XXXXXXXXX 11XXXXXXXX
X
EWDS
93C46
1
00
00XXXXX
00XXXX
Write Disable
93C56
1
00
00XXXXXXX
00XXXXXX
93C66
1
00
00XXXXXXX
00XXXXXX
93C57
1
00
00XXXXXX
00XXXXX
93C86
1
00
00XXXXXXXXX 00XXXXXXXX
X
ERAL
93C46
1
00
10XXXXX
10XXXX
Clear All Addresses
93C56
1
00
10XXXXXXX
10XXXXXX
93C66
1
00
10XXXXXXX
10XXXXXX
93C57
1
00
10XXXXXX
10XXXXX
93C86
1
00
10XXXXXXXXX 10XXXXXXXX
I
WRAL
93C46
1
00
01XXXXX
01XXXX
D7-D0 D15-D0
Write All Addresses
93C56
1
00
01XXXXXXX
01XXXXXX
D7-D0 D15-D0
93C66
1
00
01XXXXXXX
01XXXXXX
D7-D0 D15-D0
93C57
1
00
01XXXXXX
01XXXXX
D7-D0 D15-D0
93C86
1
00
01XXXXXXXXX 01XXXXXXXX
D7-D0 D15-D0
I
4
93C46/56/57/66/86
Doc. No. 1023, Rev. G
Limits
V
CC
=
V
CC
=
V
CC
=
Test
1.8V-6V
2.5V-6V
4.5V-5.5V
SYMBOL PARAMETER
Conditions
Min
Max
Min
Max
Min
Max
Units
t
CSS
CS Setup Time
200
100
50
ns
t
CSH
CS Hold Time
0
0
0
ns
t
DIS
DI Setup Time
200
100
50
ns
t
DIH
DI Hold Time
200
100
50
ns
t
PD1
Output Delay to 1
1
0.5
0.15
s
t
PD0
Output Delay to 0
1
0.5
0.15
s
t
HZ
(1)
Output Delay to High-Z
400
200
100
ns
t
EW
Program/Erase Pulse Width
5
5
5
ms
t
CSMIN
Minimum CS Low Time
1
0.5
0.15
s
t
SKHI
Minimum SK High Time
1
0.5
0.15
s
t
SKLOW
Minimum SK Low Time
1
0.5
0.15
s
t
SV
Output Delay to Status Valid
1
0.5
0.1
s
SK
MAX
Maximum Clock Frequency
DC
500
DC
1000
DC
3000
kHz
A.C. CHARACTERISTICS (93C46/56/57/66)
Limits
V
CC
=
V
CC
=
V
CC
=
1.8V-6V
2.5V-6V
4.5V-5.5V
Test
SYMBOL PARAMETER
Conditions
Min
Max
Min
Max
Min
Max
Units
t
CSS
CS Setup Time
200
100
50
ns
t
CSH
CS Hold Time
0
0
0
ns
t
DIS
DI Setup Time
400
200
100
ns
t
DIH
DI Hold Time
400
200
100
ns
t
PD1
Output Delay to 1
1
0.5
0.25
s
t
PD0
Output Delay to 0
1
0.5
0.25
s
t
HZ
(1)
Output Delay to High-Z
400
200
100
ns
t
EW
Program/Erase Pulse Width
10
10
10
ms
t
CSMIN
Minimum CS Low Time
1
0.5
0.25
s
t
SKHI
Minimum SK High Time
1
0.5
0.25
s
t
SKLOW
Minimum SK Low Time
1
0.5
0.25
s
t
SV
Output Delay to Status Valid
1
0.5
0.25
s
SK
MAX
Maximum Clock Frequency
DC
250
DC
500
DC
1000
kHz
A.C. CHARACTERISTICS (93C86)
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
C
L
= 100pF
(3)
C
L
= 100pF
(3)
5
93C46/56/57/66/86
Doc. No. 1023, Rev. G
A.C. TEST CONDITIONS
Input Rise and Fall Times
50ns
Input Pulse Voltages
0.4V to 2.4V
4.5V
V
CC
5.5V
Timing Reference Voltages
0.8V, 2.0V
4.5V
V
CC
5.5V
Input Pulse Voltages
0.2V
CC
to 0.7V
CC
1.8V
V
CC
4.5V
Timing Reference Voltages
0.5V
CC
1.8V
V
CC
4.5V
POWER-UP TIMING
(1)(2)
SYMBOL
PARAMETER
Max
Units
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
1
ms
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in "AC Test Conditions" table.
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