1
CAT93HC46
1K-Bit High Speed Microwire Serial EEPROM
FEATURES
s
High speed operation:
93HC46: 3MHz
s
Low power CMOS technology
s
1.8 to 6.0 volt operation
s
Selectable x8 or x16 memory organization
s
Self-timed write cycle with auto-clear
s
Sequential Read
s
Software write protection
s
Power-up inadvertent write protection
s
1,000,000 program/erase cycles
s
100 year data retention
s
Commercial, industrial and automotive
temperature ranges
93C46/56/57/66/86 F02
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
technology. The device is designed to endure 1,000,000
program/erase cycles and has a data retention of 100
years. The CAT93HC46 is available in 8-pin DIP, 8-pin
SOIC or 8-pin TSSOP packages.
DESCRIPTION
The CAT93HC46 is a 1K-bit Serial EEPROM memory
devices which is configured as either registers of 16 bits
(ORG pin at V
CC
) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the DI
(or DO) pin. The CAT93HC46 is manufactured using
Catalyst's advanced CMOS EEPROM floating gate
SOIC Package (S)
PIN FUNCTIONS
Pin Name
Function
CS
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
V
CC
+1.8 to 6.0V Power Supply
GND
Ground
ORG
Memory Organization
NC
No Connection
PE*
Program Enable
BLOCK DIAGRAM
Note: When the ORG pin is connected to VCC, the X16
organization is selected. When it is connected to ground,
the X8 pin is selected. If the ORG pin is left unconnected,
then an internal pullup device will select the X16
organization.
2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
TSSOP Package (U)
CS
SK
DI
DO
VCC
NC
ORG
GND
1
2
3
4
8
7
6
5
VCC
CS
SK
ORG
GND
DO
DI
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
ORG
GND
1
2
3
4
8
7
6
5
NC
NC
8
7
6
5
VCC
ORG
GND
DI
CS
SK
DO
1
2
3
4
NC
Doc. No. 1008,Rev. C
VCC
ADDRESS
DECODER
MEMORY ARRAY
ORGANIZATION
DATA
REGISTER
MODE DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO
SK
CS
DI
ORG
GND
2
CAT93HC46
Doc. No. 1008, Rev. C
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55
C to +125
C
Storage Temperature ....................... 65
C to +150
C
Voltage on any Pin with
Respect to Ground
(1)
............ 2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25
C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(2)
........................ 100 mA
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Reference Test Method
N
END
(3)
Endurance
1,000,000
Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR
(3)
Data Retention
100
Years
MIL-STD-883, Test Method 1008
V
ZAP
(3)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
I
LTH
(3)(4)
Latch-Up
100
mA
JEDEC Standard 17
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V
CC
+1V.
(5) Standby Current (ISB
2
)=0
A (<900nA).
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
CC1
Power Supply Current
3
mA
f
SK
= 3MHz
(Operating Write)
V
CC
= 5.0V
I
CC2
Power Supply Current
500
A
f
SK
= 3MHz
(Operating Read)
V
CC
= 5.0V
I
SB1
Power Supply Current
10
A
CS = 0V
(Standby) (x8 Mode)
ORG=GND
I
SB2
(5)
Power Supply Current
0
A
CS=0V
(Standby) (x16Mode)
ORG=Float or V
CC
I
LI
Input Leakage Current
1
A
V
IN
= 0V to V
CC
(Including ORG pin)
I
LO
Output Leakage Current
1
A
V
OUT
= 0V to V
CC
,
(Including ORG pin)
CS = 0V
V
IL1
Input Low Voltage
-0.1
0.8
4.5V
V
CC
< 5.5V
V
IH1
Input High Voltage
2
V
CC
+ 1
4.5V
V
CC
< 5.5V
V
IL2
Input Low Voltage
0
V
CC
x 0.2
1.8V
V
CC
< 4.5V
V
IH2
Input High Voltage
V
CC
x 0.7
V
CC
+ 1
1.8V
V
CC
< 4.5V
V
OL1
Output Low Voltage
0.4
4.5V
V
CC
< 5.5V,
I
OL
=2.1mA
V
OH1
Output High Voltage
2.4
V
4.5V
V
CC
< 5.5V,
I
OH
= -400mA
V
OL2
Output Low Voltage
0.2
1.8V
V
CC
< 4.5V, I
OL
=1mA
V
OH2
Output High Voltage
V
CC
-0.2
1.8V
V
CC
< 4.5V,
I
OH
= -100
A
V
V
V
V
V
V
3
CAT93HC46
Doc. No. 1008, Rev. C
PIN CAPACITANCE
Symbol
Test
Max.
Units
Conditions
C
OUT
(1)
OUTPUT CAPACITANCE (DO)
5
pF
V
OUT
=0V, T
A
=25C,
f
SK
=1MHz
C
IN
(1)
INPUT CAPACITANCE (CS, SK, DI, ORG)
5
pF
V
IN
=0V, T
A
=25C, f
SK
=1MHz
Note:
(1)
This parameter is tested initially and after a design or process change that affects the parameter.
INSTRUCTION SET
Start
Address Data
Instruction
Bit
Opcode
x8
x16
x8
x16 Comments
READ
1
10
A6-A0
A5-A0
Read Address ANA0
ERASE
1
11
A6-A0
A5-A0
Clear Address ANA0
WRITE
1
01
A6-A0
A5-A0
D7-D0
D15-D0 Write Address ANA0
EWEN
1
00
11XXXXX
11XXXX
Write Enable
EWDS
1
00
00XXXXX
00XXXX
Write Disable
ERAL
1
00
10XXXXX
10XXXX
Clear All Addresses
WRAL
1
00
01XXXXX
01XXXX
D7-D0
D15-D0 Write All Addresses
RECOMMENDED OPERATING CONDITIONS
Temperature
Minimum
Maximum
Commercial
0C
+70C
Industrial
-40C
+85C
Automotive
-40C
+105C
Extended
-40C
+125C
Device
Supply Voltage Range
CAT93HC46
2.5V to 6.0V
CAT93HC46-1.8
1.8V to 6.0V
4
CAT93HC46
Doc. No. 1008, Rev. C
Limits
V
CC
=
V
CC
=
V
CC
=
1.8V-6V
2.5V-6V
4.5V-5.5V
Test
SYMBOL
PARAMETER
Min.
Max.
Min.
Max.
Min.
Max.
UNITS
Conditions
t
CSS
CS Setup Time
200
100
50
ns
t
CSH
CS Hold Time
0
0
0
ns
V
IL
= 0.45V
t
DIS
DI Setup Time
400
200
50
ns
V
IH
= 2.4V
t
DIH
DI Hold Time
400
200
50
ns
C
L
= 100pF
t
PD1
Output Delay to 1
1
0.5
0.1
s
V
OL
= 0.8V
t
PD0
Output Delay to 0
1
0.5
0.1
s
V
OH
= 2.0v
t
HZ
(1)
Output Delay to High-Z
400
200
100
ns
t
EW
Program/Erase Pulse Width
5
5
5
ms
t
CSMIN
Minimum CS Low Time
1
0.5
0.1
s
t
SKHI
Minimum SK High Time
1
0.5
0.1
s
t
SKLOW
Minimum SK Low Time
1
0.5
0.1
s
t
SV
Output Delay to Status Valid
1
0.5
0.1
s
C
L
= 100pF
SK
MAX
Maximum Clock Frequency
DC
250
DC
1000
DC
3000
kHz
POWER-UP TIMING
(1)(2)
SYMBOL
PARAMETER
Max
Units
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
1
ms
A.C. CHARACTERISTICS
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in "AC Test Conditions" table.
A.C. TEST CONDITIONS
Input Rise and Fall Times
50ns
Input Pulse Voltages
0.4V to 2.4V
4.5V
V
CC
5.5V
Timing Reference Voltages
0.8V, 2.0V
4.5V
V
CC
5.5V
Input Pulse Voltages
0.2V
CC
to 0.7V
CC
1.8V
V
CC
4.5V
Timing Reference Voltages
0.5V
CC
1.8V
V
CC
4.5V
C
L
= 100pF
(3)
5
CAT93HC46
Doc. No. 1008, Rev. C
DEVICE OPERATION
The CAT93HC46 is a 1024-bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93HC46 can be organized as either registers of
16 bits or 8 bits. When organized as X16, seven 9-bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10-bit instructions control the reading, writing and erase
operations of the device. The CAT93HC46 operates on
a single power supply and will generate on chip, the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy "1" into the
DI pin. The DO pin will enter the high impedance state on
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applications
where the DI pin and the DO pin are to be tied together
to form a common DI/O pin.
Figure 1. Sychronous Data Timing
Figure 2a. Read Instruction Timing
SK
DI
CS
DO
tDIS
tPD0,tPD1
tCSMIN
tCSS
tDIS
tDIH
tSKHI
tCSH
VALID
VALID
DATA VALID
tSKLOW
SK
CS
DI
DO
tCS
STANDBY
tHZ
HIGH-Z
HIGH-Z
1
1
0
AN
AN--1
A0
0
DN DN--1
D1
D0
tPD0
MIN
6
CAT93HC46
Doc. No. 1008, Rev. C
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit byte/
word address (an additional bit when organized X8) and
for write operations a 16-bit data field (8-bit for X8
organizations).
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93HC46
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting out
the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable
after the specified time delay (t
PD0
or t
PD1
)
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle,
the CAT93HC46 will automatically increment to the next
address and shift out the next data word in a sequential
READ mode. As long as CS is continuously asserted
and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops
back to address 0. In the sequential READ mode, only
the initial data word is preceeded by a dummy zero bit.
All subsequent data words will follow without a dummy
zero bit.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of t
CSMIN
. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. (Note 1.) The ready/busy status of
the CAT93HC46 can be determined by selecting the
device and polling the DO pin. Since this device features
Auto-Clear before write, it is NOT necessary to erase a
memory location before it is written into.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of t
CSMIN
. The falling edge of CS will start the self clocking
Figure 3. Write Instruction Timing
93C46/56/57/66/86 F05
Figure 2b. Sequential Read Instruction Timing
SK
CS
DI
DO
tCS MIN
STANDBY
HIGH-Z
HIGH-Z
1
0
1
AN
AN-1
A0
DN
D0
BUSY
READY
STATUS
VERIFY
tSV
tHZ
tEW
SK
CS
DI
DO
HIGH-Z
1
1
0
AN AN1
A0
Dummy 0
D15 . . . D0
or
D7 . . . D0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address + 1
D15 . . . D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Don't Care
7
CAT93HC46
Doc. No. 1008, Rev. C
clear cycle of the selected memory location. The clocking
of the SK pin is not necessary after the device has
entered the self clocking mode. (Note 1.) The ready/
busy status of the CAT93HC46 can be determined by
selecting the device and polling the DO pin. Once
cleared, the content of a cleared location returns to a
logical "1" state.
Erase/Write Enable and Disable
The CAT93HC46 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93HC46 write
and clear instructions, and will prevent any accidental
writing or clearing of the device. Data can be read
normally from the device regardless of the write enable/
disable status.
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of t
CSMIN
. The
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. (Note 1.) The ready/busy status of
the CAT93HC46 can be determined by selecting the
device and polling the DO pin. Once cleared, the contents
of all memory bits return to a logical "1" state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
CSMIN
. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93HC46 can be determined by selecting
the device and polling the DO pin. It is not necessary for
all memory locations to be cleared before the WRAL
command is executed.
Note 1: After the last data bit has been sampled, Chip
Select (CS) must be brought Low before the next rising
edge of the clock (SK) in order to start the self-timed high
voltage cycle. This is important because if the CS is
brought low before or after this specific frame window,
the addressed location will not be programmed or erased.
Figure 4. Erase Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH-Z
HIGH-Z
1
AN
AN-1
BUSY
READY
STATUS VERIFY
tSV
tHZ
tEW
tCS MIN
1
1
A0
8
CAT93HC46
Doc. No. 1008, Rev. C
Figure 7. WRAL Instruction Timing
Figure 5. EWEN/EWDS Instruction Timing
Figure 6. ERAL Instruction Timing
SK
CS
DI
STANDBY
1
0
0
*
* ENABLE=11
DISABLE=00
SK
CS
DI
DO
STANDBY
tCS MIN
HIGH-Z
HIGH-Z
1
0
1
BUSY
READY
STATUS VERIFY
tSV
tHZ
tEW
0
0
STATUS VERIFY
SK
CS
DI
DO
STANDBY
HIGH-Z
1
0
1
BUSY
READY
tSV
tHZ
tEW
tCS MIN
DN
D0
0
0
9
CAT93HC46
Doc. No. 1008, Rev. C
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a 93HC46SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
Package
P = PDIP
S = SOIC (JEDEC)
J = SOIC (JEDEC)
U = TSSOP
Prefix
Device #
Suffix
93HC46
S
I
TE13
Product
Number
93HC46: 1K
Tape & Reel
TE13: 2000/Reel
Operating Voltage
Blank (V
cc
=2.5 to 6.0V)
1.8 (V
cc
=1.8 to 6.0V)
-1.8
CAT
Temperature Range
Blank = Commercial (0
C to +70
C)
I = Industrial (-40
C to +85
C)
A = Automotive (-40
C to
+105
C)
Optional
Company ID
E = Extended (-40C to +125C)
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP TM
AE
2
TM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Publication #:
1008
Revison:
C
Issue date:
3/29/02
Type:
Final
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