1
CAT93HC46
1-kb High Speed Microwire Serial EEPROM
FEATURES
s
High speed operation: 4 MHz @ 5.0 V
s
1.8 to 5.5 volt operation
s
Selectable x8 or x16 word organization
s
Sequential Read
s
Software write protection
s
Power-up inadvertent write protection
s
Low power CMOS technology
s
1,000,000 program/erase cycles
s
100 year data retention
s
Industrial and extended temperature ranges
s
8-Lead PDIP, SOIC, MSOP and TSSOP
packages
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W)
DESCRIPTION
The CAT93HC46 is a 1-kb Serial EEPROM memory
device which is configured as registers of either 16 bits
(ORG pin at V
CC
) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the DI
(or DO) pin. The CAT93HC46 is manufactured using
Catalyst's advanced CMOS EEPROM floating gate
SOIC Package (S, V)
FUNCTIONAL SYMBOL
Note: When the ORG pin is connected to VCC, the X16
organization is selected. When it is connected to ground,
the X8 pin is selected. If the ORG pin is left unconnected,
then an internal pullup device will select the X16
organization.
2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
TSSOP Package (U, Y)
8
7
6
5
VCC
ORG
GND
DI
CS
SK
DO
1
2
3
4
NC
Doc. No. 1008,Rev. G
MSOP Package (R, Z)
HA
LOGEN FREE
TM
LEAD FREE
technology. The device is designed to endure 1,000,000
program/erase cycles and has a data retention of 100
years. The CAT93HC46 is available in 8-pin DIP, SOIC,
MSOP or TSSOP packages.
CS
SK
DI
DO
VCC
NC
ORG
GND
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
ORG
GND
1
2
3
4
8
7
6
5
VCC
CS
SK
ORG
GND
DO
DI
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
ORG
GND
1
2
3
4
8
7
6
5
NC
NC NC
VCC
DO
ORG
DI
SK
CS
VSS
CAT93HC46
PIN FUNCTIONS
Pin Name
Function
CS
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
V
CC
1.8 to 5.5 V Power Supply
GND
Ground
ORG
Memory Organization
NC
No Connection
2
CAT93HC46
Doc. No. 1008, Rev. G
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55
C to +125
C
Storage Temperature ........................ -65
C to +150
C
Pin with Respect to Ground
(1)
.... -2.0 V to V
CC
+ 2.0 V
V
CC
with Respect to Ground ................ -2.0 V to 7.0 V
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(2)
........................ 100 mA
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
RELIABILITY CHARACTERISTICS
Note:
(1) The minimum DC input voltage is -0.5 V. During transitions, inputs may undershoot to -2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
(2) Output shorted for no more than one second.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1 V to V
CC
+ 1 V.
(5) Standby Current (ISB
2
) = 0
A (<900 nA).
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8
8
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T
S
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0
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1
d
o
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t
e
M
t
s
e
T
,
3
8
8
-
D
T
S
-
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I
M
0
0
1
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r
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e
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V
P
A
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3
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3
d
o
h
t
e
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t
s
e
T
,
3
8
8
-
D
T
S
-
L
I
M
0
0
0
2
s
t
l
o
V
I
H
T
L
)
4
(
)
3
(
p
U
-
h
c
t
a
L
7
1
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r
a
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n
a
t
S
C
E
D
E
J
0
0
1
A
m
D.C. OPERATING CHARACTERISTICS
Industrial Temperature Range (-40
C to 85
C)
Limits
Symbol
Parameter
Min
Typ
Max
Units
Test Conditions
I
CC1
Power Supply Current (Write)
2
mA
f
SK
= 4 MHz, V
CC
= 5.0 V
I
CC2
Power Supply Current (Read)
200
A
f
SK
= 4 MHz, V
CC
= 5.0 V
I
SB1
Standby Supply Current (x8)
10
A
CS = GND, ORG=GND
I
SB2
(5)
Standby Supply Current (x16)
0
10
A
CS = GND, ORG = Float or V
CC
I
LI
Input Leakage Current
1
A
V
IN
= 0 V to V
CC
, CS = GND
I
LO
Output Leakage Current
1
A
V
OUT
= 0 V to V
CC
, CS = GND
V
IL1
Input Low Voltage
-0.1
0.8
4.5 V
V
CC
< 5.5 V
V
IH1
Input High Voltage
2
V
CC
+ 1
4.5 V
V
CC
< 5.5 V
V
IL2
Input Low Voltage
0
V
CC
x 0.2
1.8 V
V
CC
< 4.5 V
V
IH2
Input High Voltage
V
CC
x 0.7
V
CC
+ 1
1.8V
V
CC
< 4.5 V
V
OL1
Output Low Voltage
0.4
4.5 V
V
CC
< 5.5 V, I
OL
= 2.1 mA
V
OH1
Output High Voltage
2.4
V
4.5 V
V
CC
< 5.5 V, I
OH
= -400
A
V
OL2
Output Low Voltage
0.2
1.8 V
V
CC
< 4.5 V, I
OL
= 1 mA
V
OH2
Output High Voltage
V
CC
- 0.2
1.8 V
V
CC
< 4.5 V, I
OH
= -100
A
3
CAT93HC46
Doc. No. 1008, Rev. G
1.8 V - 5.5 V
2.5 V - 5.5 V
4.5 V - 5.5 V
Test
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
Conditions
SK
MAX
Maximum Clock Frequency
DC
1
DC
2
DC
4
MHz
t
CSS
CS Setup Time
240
120
60
ns
t
CSH
CS Hold Time
0
0
0
ns
t
DIS
DI Setup Time
240
120
60
ns
t
DIH
DI Hold Time
240
120
60
ns
t
PD1
Output Delay to 1
480
240
120
ns
t
PD0
Output Delay to 0
480
240
120
ns
t
HZ
(1)
Output Delay to High-Z
240
120
60
ns
t
CSMIN
Minimum CS Low Time
240
120
60
ns
t
SKHI
Minimum SK High Time
480
240
120
ns
t
SKLOW
Minimum SK Low Time
240
120
60
ns
t
SV
Output Delay to Status Valid
480
240
120
ns
t
EW
Program/Erase Pulse Width
5
5
5
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
10 ns
Input Pulse Voltages
0.4 V to 2.4 V
4.5 V
V
CC
5.5 V
Timing Reference Voltages
0.8 V, 2.0 V
4.5 V
V
CC
5.5 V
Input Pulse Voltages
V
CC
x 0.2 to V
CC
x
0.8
1.8 V
V
CC
4.5 V
Timing Reference Voltages
V
CC
x
0.5
1.8 V
V
CC
4.5 V
POWER-UP TIMING
(1)(2)
Symbol
Parameter
Min
Typ
Max
Units
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
1
ms
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in the "AC Test Conditions" table.
A.C. CHARACTERISTICS
Industrial Temperature Range (-40
C to 85
C)
CL = 100 pF
(3)
4
CAT93HC46
Doc. No. 1008, Rev. G
DEVICE OPERATION
The CAT93HC46 is a 1024-bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93HC46 can be organized as registers of either
16 bits or 8 bits. When organized as X16, seven 9-bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10-bit instructions control the operation of the device.
The CAT93HC46 operates on a single power supply and
will generate on chip the high voltage required during
write operation.
Instructions, addresses, and data are clocked into the DI
pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state, except when reading
data from the device, or when checking the ready/busy
status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state by shifting a dummy "1" into the DI pin. The DO pin
will enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin
and the DO pin are to be tied together to form a common
DI/O pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit byte/
word address (an additional bit when organized X8) and
for write operations a 16-bit data field (8-bit for X8
organization).
Figure 1. Sychronous Data Timing
SK
DI
CS
DO
tDIS
tPD0,tPD1
tCSMIN
tCSS
tDIS
tDIH
tSKHI
tCSH
VALID
VALID
DATA VALID
tSKLOW
INSTRUCTION SET
Start
Address Data
Instruction
Bit
Opcode
x8
x16
x8
x16 Comments
READ
1
10
A6-A0
A5-A0
Read Address ANA0
ERASE
1
11
A6-A0
A5-A0
Clear Address ANA0
WRITE
1
01
A6-A0
A5-A0
D7-D0
D15-D0 Write Address ANA0
EWEN
1
00
11XXXXX
11XXXX
Write Enable
EWDS
1
00
00XXXXX
00XXXX
Write Disable
ERAL
1
00
10XXXXX
10XXXX
Clear All Addresses
WRAL
1
00
01XXXXX
01XXXX
D7-D0
D15-D0 Write All Addresses
5
CAT93HC46
Doc. No. 1008, Rev. G
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93HC46
will come out of the high impedance state; after an initial
dummy zero bit, data will be shifted out, MSB first. The
output will toggle on the rising edge of the SK clock and
will be stable after the specified time delay (t
PD0
or t
PD1
)
After the 1st data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle,
the CAT93HC46 will automatically increment to the next
address and shift out the next data word. As long as CS
is continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches the end of the address
space, then loops back to address 0. In the sequential
READ mode, only the initial data word is preceeded by
a dummy zero bit; all subsequent data words will follow
without a dummy zero bit.
Write
After receiving a WRITE command, address and data,
the CS (Chip Select) pin must be deselected for a
minimum of t
CSMIN
. The falling edge of CS will start the
self-timed clear and data store cycle into the specified
memory location. The clocking of the SK pin is not
necessary after the device has entered the self-timed
mode. (Note 1.) The ready/busy status of the CAT93HC46
can be determined by selecting the device and polling
the DO pin. Since this device features Auto-Clear before
write, it is NOT necessary to erase a memory location
before it is written into.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of t
CSMIN
. The falling edge of CS will start the self-timed
clear cycle of the selected memory location. The clocking
of the SK pin is not necessary after the device has
entered the self-timed mode. (Note 1.) The ready/busy
status of the CAT93HC46 can be determined by selecting
the device and polling the DO pin. Once cleared, the
content of a cleared location returns to a logical "1" state.
Figure 2a. Read Instruction Timing
SK
CS
DI
DO
tCS
STANDBY
tHZ
HIGH-Z
HIGH-Z
1
1
0
AN
AN--1
A0
0
DN DN--1
D1
D0
tPD0
MIN
Figure 2b. Sequential Read Instruction Timing
SK
CS
DI
DO
HIGH-Z
1
1
0
AN AN1
A0
Dummy 0
D15 . . . D0
or
D7 . . . D0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address + 1
D15 . . . D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Don't Care
6
CAT93HC46
Doc. No. 1008, Rev. G
Erase/Write Enable and Disable
The CAT93HC46 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once write is enabled, it will
remain enabled until power to the device is removed, or
the EWDS instruction is sent. The EWDS instruction can
be used to disable all CAT93HC46 write and clear
instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from
the device regardless of the write enable/disable status.
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of t
CSMIN
. The
falling edge of CS will start the self-timed clear cycle of
all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self-timed mode. (Note 1.) The ready/busy status of the
CAT93HC46 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory locations will return to a logical "1" state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
CSMIN
. The falling edge of CS will start the self-timed
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self-timed mode. The ready/busy status
of the CAT93HC46 can be determined by selecting the
device and polling the DO pin. It is not necessary for all
memory locations to be cleared before the WRAL
command is executed. Once written, the contents of all
memory locations will return to a logical "0" state.
Note 1: After the last data bit has been sampled, Chip
Select (CS) must be brought Low before the next rising
edge of the clock (SK) in order to start the self-timed high
voltage cycle. This is important because if the CS is
brought low before or after this specific frame window,
the addressed location will not be programmed or erased.
Figure 4. Erase Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH-Z
HIGH-Z
1
AN
AN-1
BUSY
READY
STATUS VERIFY
tSV
tHZ
tEW
tCS MIN
1
1
A0
Figure 3. Write Instruction Timing
SK
CS
DI
DO
tCS MIN
STANDBY
HIGH-Z
HIGH-Z
1
0
1
AN
AN-1
A0
DN
D0
BUSY
READY
STATUS
VERIFY
tSV
tHZ
tEW
7
CAT93HC46
Doc. No. 1008, Rev. G
Figure 7. WRAL Instruction Timing
Figure 5. EWEN/EWDS Instruction Timing
Figure 6. ERAL Instruction Timing
SK
CS
DI
STANDBY
1
0
0
*
* ENABLE=11
DISABLE=00
SK
CS
DI
DO
STANDBY
tCS MIN
HIGH-Z
HIGH-Z
1
0
1
BUSY
READY
STATUS VERIFY
tSV
tHZ
tEW
0
0
STATUS VERIFY
SK
CS
DI
DO
STANDBY
HIGH-Z
1
0
1
BUSY
READY
tSV
tHZ
tEW
tCS MIN
DN
D0
0
0
8
CAT93HC46
Doc. No. 1008, Rev. G
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a 93HC46SI-TE13 (SOIC, Industrial Temperature,Tape & Reel).
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWH.) For additional
information, please contact your Catalyst sales office.
* available upon request
Package
P = PDIP
S = SOIC (JEDEC)
J = SOIC (JEDEC)
U = TSSOP
Prefix
Device #
Suffix
93HC46
S
I
TE13
Product
Number
93HC46: 1K
Tape & Reel
TE13: 2000/Reel
Operating Voltage
Blank (V
cc
=2.5 to 6.0V)
1.8 (V
cc
=1.8 to 6.0V)
-1.8
CAT
Temperature Range
Blank = Commercial (0C to +70C)
I = Industrial (-40C to +85C)
A = Automotive (-40C to
+105C)
Optional
Company ID
E = Extended (-40C to +125C)
Rev H
(2)
Die Revision
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP TM
AE
2
TM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Publication #:
1008
Revison:
G
Issue date:
7/27/04
Type:
Final
Date
Rev.
Reason
11/11/2003
E
Updated Features
Eliminated Commercial temperature range
Updated DC Operating Characteristics
Updated AC Characteristics
Updated Ordering Information
11/14/2003
F
Updated DC Operating Characteristics
7/27/2004
G
Add die revision to Ordering Information
REVISION HISTORY
PDF 
ZIP