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500
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
500V , 4.7A , R
DS(ON)
=0.85
@V
GS
=10V.
Super high dense cell design for extremely low R
DS(ON)
.
High power and current handling capability.
TO-220F full-pak for through hole
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Symbol
Limit
Unit
Drain-Source Voltage
V
DS
V
Gate-Source Voltage
V
GS
30
V
-Pulsed
I
D
4.7
A
I
DM
A
Drain-Source Diode Forward Current
I
S
4.7
A
Maximum Power Dissipation
P
D
W
Operating and Storage Temperautre Range
T
J
, T
STG
-55 to 150
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
R
JC
R
JA
2.6
65
/W
C
/W
C
@Tc=25 C
Derate above 25 C
48
0.38
W/ C
Drain Current-Continuous
S
G
D
6-142
PRELIMINARY
15
CEF08N5
TO-220F
S
D
G
6
ELECTRICAL CHARACTERISTICS (T
C
=25 C unless otherwise noted)
Parameter
Symbol
Condition
Min Typ Max Unit
DRAIN-SOURCE AVALANCHE RATING
a
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
BV
DSS
V
GS
= 0V,I
D
= 250
A
500
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 500V, V
GS
= 0V
25
A
Gate-Body Leakage
I
GSS
V
GS
= 30V, V
DS
= 0V
100 nA
ON CHARACTERISTICS
a
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= 250
A
2
4
V
Drain-Source On-State Resistance
R
DS(ON)
V
GS
=10V, I
D
= 4.8A
0.85
On-State Drain Current
I
D(ON)
V
GS
= 10V, V
DS
= 10V
4
A
S
Forward Transconductance
FS
g
V
DS
= 50V, I
D
= 6A
SWITCHING CHARACTERISTICS
b
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
t
D(ON)
t
r
t
D(OFF)
t
f
V
DD
=250V,
I
D
= 8A,
V
GS
= 10V
R
GEN
=9.1
18
ns
ns
ns
ns
25
105
38
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Q
g
Q
gs
Q
gd
V
DS
=400V, I
D
= 8A,
V
GS
=10V
56
65
nC
nC
nC
Fall Time
6-143
Single Pulse Drain-Source
Avalanche Energy
Maximum Drain-Source
Avalanche Current
E
AS
I
AS
V
DD
=50V, L=24mH
A
mJ
CEF08N5
R
G
=25
8
500
30
0.76
8
6
6
Parameter
Symbol
Condition
Min Typ Max Unit
ELECTRICAL CHARACTERISTICS (T
C
=25 C unless otherwise noted)
DRAIN-SOURCE DIODE CHARACTERISTICS
Diode Forward Voltage
V
SD
V
GS
= 0V, Is =8A
1.5
V
a
Notes
b.Guaranteed by design, not subject to production testing.
a.Pulse Test:Pulse Width 300 s, Duty Cycle 2%.
6-144
Figure 1. Output Characteristics
I
D
,
D
r
ain
Current(A)
I
D
,
D
r
ain
Current
(A)
b
DYNAMIC CHARACTERISTICS
Input Capacitance
C
ISS
C
RSS
C
OSS
Output Capacitance
Reverse Transfer Capacitance
V
DS
=25V, V
GS
= 0V
f =1.0MH
Z
800
P
F
110
P
F
P
F
70
CEF08N5
Figure 2. Transfer Characteristics
V
GS
, Gate-to-Source Voltage (V)
0.1
1
2
4
6
10
8
25 C
150 C
-55 C
1.V
DS
=40V
2.Pulse Test
10
6
12
10
8
6
4
2
0
0
2
4
6
8
10
12
V
GS
=10,9,8,7V
V
GS
=5V
V
GS
=6V
6-145
with Temperature
Figure 6. Breakdown Voltage Variation
with Temperature
Vth,
Normalized
Gate-Source
Threshold
Voltage
g
FS
,
Transconductance
(S)
BV
DSS
,
Normalized
Drain-Source
Breakdown
Voltage
Is,
Source-drain
current
(A)
with Drain Current
I
DS
, Drain-Source Current (A)
Figure 8. Body Diode Forward Voltage
Variation with Source Current
V
SD
, Body Diode Forward Voltage (V)
Tj, Junction Temperature ( C)
Tj, Junction Temperature ( C)
Figure 5. Gate Threshold Variation
Figure 7. Transconductance Variation
Figure 3. Capacitance
V
DS
, Drain-to Source Voltage (V)
C
,
Capacitance
(pF)
1.30
1.20
1.10
1.0
0.90
0.80
0.70
0.60
-50 -25
0
25
50
75
100 125 150
V
DS
=V
GS
I
D
=250 A
-50
-25
0
25
50
75 100 125 150
1.15
1.10
1.05
1.00
0.95
0.90
0.85
I
D
=250 A
Figure 4. On-Resistance Variation with
Temperature
T
J
, Junction Temperature( C)
On-Resistance(Ohms)
R
DS(ON)
,
R
DS(ON)
,
Nor
maliz
ed
-100
-50
0
50
100
200
2.2
1.9
1.6
1.3
1.0
0.7
0.4
V
GS
=10V
I
D
=4.8A
150
20
10
0.1
1
0.4
0.6
0.8
1.2
1.0
V
GS
=0V
3
4
0
1
2
0
1
2
3
4
V
DS
=50V
CEF08N5
6
Ciss
Coss
Crss
1200
1000
800
600
400
200
0
0
5
10
15
20
25
6-146
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
t
V
V
t
t
d(on)
OUT
IN
on
r
10%
t
d(off)
90%
10%
10%
50%
50%
90%
t
off
t
f
90%
PULSE WIDTH
INVERTED
Transient
Thermal
Impedance
Square Wave Pulse Duration (sec)
Figure 13. Normalized Thermal Transient Impedance Curve
r(t),Normalized
Effective
V
DD
R
D
V
V
R
S
V
G
GS
IN
GEN
OUT
L
V
GS
,
G
ate
t
o
Source
V
oltage
(V)
Figure 9. Gate Charge
Qg, Total Gate Charge (nC)
Figure 10. Maximum Safe
Operating Area
V
DS
, Drain-Source Voltage (V)
I
D
,
D
rain
Current
(A)
15
12
9
6
3
0
0
20
40
60
80
V
DS
=400V
I
D
=8A
P
DM
t
1
t
2
1. R
JC
(t)=r (t) * R
JC
2. R
JC
=See Datasheet
3. T
JM-
T
C
= P* R
JC
(t)
4. Duty Cycle, D=t1/t2
D=0.5
0.1
0.05
0.02
0.01
Single Pulse
10
10
10
1
0
-1
10
-2
10
-3
10
-4
10
-5
10
-2
10
-1
10
0
0.2
10
10
10
10
0
10
10
3
2
1
10
1
T
C
=25 C
Single Pulse
Tj=150 C
D
C
-1
0
10m
s
1ms
10
0
s
RDS(
ON
) L
im
it
100
ms
CEF08N5
6
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