1
Features
CS5101
SSPR
PGnd
IS COMP
V
CC
V
C
Q1
R4
C2
R6
R2
R3
C
R4
C6
R14
C5
Gnd
V
OUT
R13
IS+
IS-
L1
R10
LGnd
V
FB
COMP
V
G
RAMP
C
R5
V
SY
C3
R8
R9
+
+
V
SYNC
R12
R11
R7
C
R2
R5
V
D
C4
C1
+
C
R1
R1
C
R3
5
V
REF
C
R
2
3
6
4
1
TR
s
1.5A Peak Output
(Grounded Totem Pole)
s
8V to 75V Gate Drive Voltage
s
8V to 45V Supply Voltage
s
300ns Propagation Delay
s
1% Error Amplifier
Reference Voltage
s
Lossless Turn On and
Turn Off
s
Sleep Mode: < 100A
s
Overcurrent Protection with
Dedicated Differential Amp
s
Synchronization to External
Clock
s
External Power Switch
Drain Voltage Monitor
Package Options
16L SO Wide
14L PDIP
CS5101
Secondary Side Post Regulator for AC/DC
and DC/DC Multiple Output Converters
1
SYNC
V
CC
V
REF
DGnd
V
FB
COMP
RAMP
V
C
PGnd
IS-
IS+
IS COMP
V
D
V
G
PGnd
AGnd
1
SYNC
V
CC
V
REF
LGnd
V
FB
COMP
RAMP
V
C
PGnd
IS-
IS+
IS COMP
V
D
V
G
CS5101
Description
The CS5101 is a bipolar monolithic
secondary side post regulator
(SSPR) which provides tight regula-
tion of multiple output voltages in
AC-DC or DC-DC converters.
Leading edge pulse width modula-
tion is used with the CS5101.
The CS5101 is designed to operate
over an 8V to 45V supply voltage
(V
CC
) range and up to a 75V drive
voltage (V
C
).
The CS5101 features include a totem
pole output with 1.5A peak output
current capability, externally pro-
grammable overcurrent protection,
an on chip 2% precision 5V refer-
ence, internally compensated error
amplifier, externally synchronized
switching frequency, and a power
switch drain voltage monitor. It is
available in a 14 lead plastic DIP or
a 16 lead wide body SO package.
Application Diagram
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
A Company
Rev. 3/31/97
2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CS5101
Absolute Maximum Ratings
Power Supply Voltage, V
CC
.....................................................................................................................................-0.3V to 45V
V
SYNC
and Output Supply Voltages, V
C
, V
G
, V
SYNC
, V
D
.....................................................................................-0.3V to 75V
V
IS
+, V
IS
- (V
CC
4V, up to 24V)..................................................................................................................................-0.3 to 24V
V
REF
, V
FB
, V
COMP
, V
RAMP
, V
ISCOMP
............................................................................................................................-0.3 to 10V
Operating Junction Temperature, T
J
.......................................................................................................................-40 to 150C
Operating Temperature Range ..................................................................................................................................-40 to 85C
Storage Temperature Range ....................................................................................................................................-65 to 150C
Output Energy (capacitive load per cycle).............................................................................................................................5J
ESD Human Body ....................................................................................................................................................................2kV
ESD Machine Model...............................................................................................................................................................200V
Lead Temperature Soldering
Wave Solder (through hole styles only)....................................................................................10 sec. max, 260C peak
Reflow (SMD styles only).....................................................................................60 sec. max above 183C, 230C peak
Electrical Characteristics:
-40C T
A
85C; -40C T
J
150C; 10V < V
CC
< 45V; 8V < V
C
<75V unless otherwise specified.
s Error Amplifier
Input Voltage Initial Accuracy
V
FB
= V
COMP
; V
CC
= 15V;
1.98
2.00
2.02
V
T = 25C (Note 1)
Input Voltage
V
FB
= V
COMP
, includes line and temp
1.94
2.00
2.06
V
Input Bias Current
V
FB
= 0V; IV
FB
flows out of pin
500
nA
Open Loop Gain
1.5V < V
COMP
< 3.0V
60
70
dB
Unity Gain Bandwidth
1.5V < V
COMP
< 3.0V; (Note 1)
0.7
1.0
MHz
Output Sink Current
V
COMP
= 2.0V; V
FB
= 2.2V
2
8
mA
Output Source Current
V
COMP
= 2.0V; V
FB
= 1.8V
2
6
mA
V
COMP
High
V
FB
= 1.8V
3.3
3.5
3.7
V
V
COMP
Low
V
FB
= 2.2V
0.85
1.0
1.15
V
PSRR
10V < V
CC
< 45V;
60
70
dB
V
FB
= V
COMP
(Note 1)
s Voltage Reference
Output Voltage Initial Accuracy
V
CC
= 15V; T = 25C (Note 1)
4.9
5.0
5.1
V
Output Voltage
0A < I
REF
< 8mA
4.8
5.0
5.2
V
Line Regulation
10V < V
CC
< 45V; I
REF
= 0A
10
60
mV
Load Regulation
0A < I
REF
< 8mA
20
60
mV
Current Limit
V
REF
= 4.8V
10
50
mA
V
REF
_OK FAULT V
V
SYNC
= 5V; V
REF
= V
LOAD
4.10
4.40
4.60
V
V
REF
_OK V
V
SYNC
= 5V; V
REF
= V
LOAD
4.30
4.50
4.80
V
V
REF
_OK Hysteresis
40
100
250
mV
s Current Sense Amplifier
IS COMP High V
IS
+
= 5V; IS
= IS COMP
4.7
5.0
5.3
V
IS COMP Low V
IS
+
= 0V; IS
= IS COMP
0.5
1.0
1.3
V
Source Current
IS
+
= 5V; IS
= 0V
2.0
10
mA
Sink Current
IS
-
= 5V; IS
+
= 0V
10
20
mA
Open Loop Gain
1.5V V
COMP
4.5V; R
L
= 4k
60
80
dB
CMRR
(Note 1)
60
80
dB
PSRR
10V < V
CC
< 45V, (Note 1)
60
80
dB
Unity Gain Bandwidth
1.5V V
COMP
4.5V; R
L
= 4k (Note 1)
0.5
0.8
MHz
4
CS5101
PACKAGE PIN #
PIN SYMBOL
FUNCTION
Package Pin Description
14L PDIP
16L SO Wide
1
1
SYNC
Synchronization input.
2
2
V
CC
Logic supply (10V to 45V).
3
3
V
REF
5.0V voltage reference.
4
LGnd
Logic level ground (Analog and digital ground tied).
5
6
V
FB
Error amplifier inverting input.
6
7
COMP
Error amplifier output and compensation.
7
8
RAMP
RAMP programmable with the external capacitor.
8
9
IS+
Current sense amplifier non-inverting input.
9
10
IS-
Current sense amplifier inverting input.
10
11
IS COMP
Current sense amplifier compensation and output.
11
12, 13
PGnd
Power ground.
12
14
V
G
External power switch gate drive.
13
15
V
C
Output power stage supply voltage (8V to 75V).
14
16
V
D
External FET DRAIN Voltage Monitor.
5
AGnd
Analog Ground.
4
DGnd
Digital Ground.
Circuit Description
COMP
RAMP
LGnd
SYNC
LATCH
Q
V
REF
PGnd
IS COMP
V
D
5V
V
C
V
G
IS
Q
1
Q
2
REF_OK
G
1
G
2
I = 200
mA
V
FB
2.5V
2V
Q
3
+
SYNC
V
CC
_OK
+
V
CC
S
R
PWM
+
4.5V/4.4V
1.65V
+
RAMP
+
+
+
EA
+
BUF
+
IS+
IS-
1.5V
0.7V
Q
4
+
SLEEP
V
CC
+
REF
UVL
OK
0.7V
8V/7V
2.4V
24.6k
5V
5V
5V
5V
5V
5V
V
CC
10k
10k
5V
5V
+
+
+
+
+
+
+
+
+
V
CC
+
V
C
Q
Block Diagram
5
CS5101
Circuit Description: continued
The CS5101 is designed to regulate voltages in multiple
output power supplies. Functionally, it is similar to a
magnetic amplifier, operating as a switch with a delayed
turn-on. It can be used with both single ended and dual
ended topologies.
The V
FB
voltage is monitored by the error amplifier EA. It
is compared to an internal reference voltage and the
amplified differential signal is fed through an inverting
amplifier into the buffer, BUF. The buffered signal is com-
pared at the PWM comparator with the ramp voltage
generated by capacitor C
R
. When the ramp voltage V
R
,
exceeds the control voltage V
C
, the output of the PWM
comparator goes high, latching its state through the
LATCH, the output stage transistor Q
1
turns on, and the
external power switch, usually an N-FET, turns on.
The SYNC circuit is activated at time t
1
(Figure 1) when
the voltage at the SYNC pin exceeds the threshold level
(2.5V) of the SYNC comparator. The external ramp capac-
itor C
R
is allowed to charge through the internal current
source I (200A). At time t
2
, the ramp voltage intersects
with the control voltage V
C
and the output of the PWM
comparator goes high, turning on the output stage and
the external power switch. At the same time, the PWM
comparator is latched by the RS latch, LATCH.
Figure 1. Waveforms for CS5101. The number to the left of each curve
refers to a node on the Application Diagram.
The logic state of the LATCH can be changed only when
both the voltage level of the trailing edge of the power
pulse at the SYNC pin is less than the threshold voltage of
the SYNC comparator (2.5V) and the RAMP voltage is
less than the threshold voltage of the RAMP comparator
(1.65V). On the negative going transition of the secondary
side pulse V
SY
, gate G
2
output goes high, resetting the
latch at time t
3
. Capacitor C
R
is discharged through tran-
sistor Q
4
. C
R
s output goes low disabling the output stage,
and the external power switch (an N-FET) is turned off.
The value of the ramp capacitor C
R
is based on the
switching frequency of the regulator and the maximum
duty cycle of the secondary pulse V
SY
.
If the RAMP pin is pulled externally to 0.3V or below, the
SSPR is disabled. Current drawn by the IC is reduced to
less than 100A, and the IC is in SLEEP mode.
The voltage at the V
CC
pin is monitored by the undervolt-
age lockout comparator with hysteresis. When V
CC
falls
below the UVL threshold, the 5V reference and all the cir-
cuitry running off of it is disabled. Under this condition
the supply current is reduced to less than 500A.
The V
CC
supply voltage is further monitored by the
V
CC
_OK comparator. When V
CC
is reduced below
V
REF
- 0.7V, a fault signal is sent to gate G
1
. This fault sig-
nal, which determines if V
CC
is absent, works in conjunc-
tion with the ramp signal to disable the output, but only
after the current cycle has finished and the RS latch is reset.
Therefore this fault will not cause the output to turn off
during the middle of an on pulse, but rather will utilize
lossless turn-off. This feature protects the FET from over-
voltage stress. This is accomplished through gate G
1
by
driving transistor Q
4
on.
An additional fault signal is derived from the REF_OK
comparator. V
REF
is monitored so to disable the output
through gate G
1
when the V
REF
voltage falls below the
OK threshold. As in the V
CC
_OK fault, the REF_OK fault
disables the output after the current cycle has been com-
pleted. The fault logic will operate normally only when
V
REF
voltage is within the specification limits of REF_OK.
The drain pin, V
D
monitors the voltage on the drain of the
power switch and derives energy from it to keep the out-
put stage in an off state when V
C
or V
CC
is below the min-
imum specified voltage.
DRAIN Function
FAULT Function
RAMP Function
0V
V
SY
V
SY
+ V
D
V
SY
0V
0V
V
SY
V
OUT
0V
0V
V
SY
+ V
C
t
1
t
2
t
3
t
4
t
1
V
D
V
OUT
+ V
D
V
D
V
G
V
L1
V
S
V
DS
V
C
V
RAMP
V
SY
1
2
3
4
5
6
Ground Level
(Gate doesn't go
below Gnd)
SYNC Function
Theory of Operation
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