ChipFind - документация

Электронный компонент: CS51022

Скачать:  PDF   ZIP
The CS51021/22/23/24 Fixed
Frequency PWM Current Mode
Controller family provides all neces-
sary features required for AC-DC or
DC-DC primary side control.
Several features are included elimi-
nating the additional components
needed to implement them external-
ly. In addition to low start-up cur-
rent (75A) and high frequency
operation capability, the CS51021/
22/23/24 family includes overvolt-
age and undervoltage monitoring,
externally programmable dual
threshold overcurrent protection,
current sense leading edge blank-
ing, current slope compensation,
accurate duty cycle control and an
externally available 5V reference.
The CS51021 and CS51023 feature
bidirectional synchronization capa-
bility, while the CS51022 and
CS51024 offer a sleep mode with
100A maximum IC current con-
sumption. The CS51021/22/23/24
family is available in a 16 lead nar-
row body SO package.
1
Features
V
IN
(36V to 72V)
51k
0.01
F
470pF
6.98k,
1%
10
6.98k,
1%
PGND
200K,1%
0.1
F
100p
62
IRF6345
100
1
F
10
680pF
10K
1K
180
MOC81025
2K,1%
100
F 100
F
SGND
V
OUT
(5V/5A)
22K
5.1K
0.1
F
1000pF
SYNC/SLEEP
2.49K,1%
51K
10K
0.01
F
2K, 1%
1K
330pF
MBRB2060CT
100pF
10
BA521
10K
BAS21
18V
22
F
11V
FZT688
10
4700pF
24.3K
1%
100
TL431
4:1
100:1
2:5
UV
U1
OV
V
REF
R
T
C
T
I
SET
LGnd
C
SS
V
FB
COMP
SYNC/
SLEEP
PGnd
SLOPE
V
C
V
CC
GATE
I
SENSE
CS51021/51022
s
75A Max. Startup Current
s
Fixed Frequency Current
Mode Control
s
1MHz Switching Frequency
s
Undervoltage Protection
Monitor
s
Overvoltage Protection
Monitor with
Programmable Hysteresis
s
Programmable Dual
Threshold Overcurrent
Protection with Delayed
Restart
s
Programmable Soft Start
s
Accurate Maximum Duty
Cycle Limit
s
Programmable Slope
Compensation
s
Leading Edge Current
Sense Blanking
s
1A Sink/Source Gate Drive
s
Bidirectional Synchronization
(CS51021/23)
s
50ns PWM Propagation
Delay
s
100A Max Sleep Current
(CS51022/24)
Package Options
CS51021/22/23/24
Enhanced Current Mode
PWM Controller
CS51021/CS51023
CS51022/CS51024
Description
Typical Application Diagram
1
SS
V
REF
OV
SLEEP
or SYNC
V
FB
R
T
C
T
V
CC
SLOPE
I
SET
PGnd
I
SENSE
COMP
LGnd
UV
V
C
GATE
16 Lead SO Narrow
Device
Sleep/Synch
V
CC
Start/Stop
CS51021
Synch
8.25V/7.7V
CS51022
Sleep
8.25V/7.7V
CS51023
Synch
13V/7.7V
CS51024
Sleep
13V/7.7V
A Company
36-72V to 5V, 5A DC-DC Convertor
Rev. 2/22/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
Consult factory for other package options.
Power Supply Voltage, V
CC
............................................................................................................................................-0.3V, 20V
Driver Supply Voltage, V
C
..............................................................................................................................................-0.3V, 20V
SYNC, SLEEP, R
T
C
T
, SOFT START, V
FB
, SLOPE, I
SENSE
, UV, OV, I
SET
(Logic Pins).......................................-0.25V to V
REF
Peak GATE Output Current.........................................................................................................................................................1A
Steady State Output Current.................................................................................................................................................. 0.2A
Operating Junction Temperature, T
J
..................................................................................................................................... 150C
Storage Temperature Range, T
S
...................................................................................................................................-65 to 150C
ESD (Human Body Model).........................................................................................................................................................2kV
Lead Temperature Soldering: Reflow (SMD styles only).............................................60 sec. max above 183C, 230C peak
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2
CS51021/22/23/24
Absolute Maximum Ratings
s
Under Voltage Lockout
START Threshold (CS51021/22)
7.95
8.25
8.8
V
START Threshold (CS51023/24)
12.4
13
13.4
V
STOP Threshold
7.4
7.7
8.2
V
Hysteresis (CS51021/22)
0.50
0.75
1.00
V
Hysteresis (CS51023/24)
4
5
6
V
I
CC
@ Startup (CS51021/22)
V
CC
< UV
START
Threshold
40
75
A
I
CC
@ Startup (CS51023/24)
V
CC
< UV
START
Threshold
45
75
A
I
CC
Operating (CS51021/23)
7
9
mA
I
CC
Operating (CS51022/24)
6
8
mA
I
C
Operating
Includes 1nF Load
7
12
mA
s
Voltage Reference
Initial Accuracy
T
A
= 25C, I
REF
= 2mA, V
CC
= 14V (Note1) 4.95
5
5.05
V
Total Accuracy
1mA<I
REF
<10mA
4.9
5
5.15
V
Line Regulation
8.2V < V
CC
< 18V, I
REF
= 2mA
6
20
mV
Load Regulation
1mA < I
REF
< 10mA
6
15
mV
NOISE Voltage
(Note 1)
50
uV
OP Life Shift
T=1000 Hours (Note 1)
4
20
mV
FAULT Voltage
Force V
REF
.92 V
REF
.95 V
REF
.97 V
REF
V
OK Voltage
Force V
REF
.94 V
REF
.96 V
REF
.98 V
REF
V
OK Hysteresis
Force V
REF
50
105
160
mV
Current Limit
Force V
REF
-20
mA
s
Error Amplifier
Initial Accuracy
T
A
=25C, I
REF
= 2mA, V
CC
= 14V,
2.465
2.515
2.565
V
V
FB
= COMP (Note 1)
Reference Voltage
V
FB
= COMP
2.440
2.515
2.590
V
V
FB
Leakage Current
V
FB
= 0V
-0.2
-2
A
Open Loop Gain
1.4V < COMP < 4V (Note 1)
60
90
dB
Unity Gain Bandwidth
(Note 1)
1.5
2.5
MHz
COMP Sink Current
COMP = 1.5V, V
FB
= 2.7V
2
6
mA
COMP Source Current
COMP = 1.5V, V
FB
= 2.3V
-0.2
-0.5
mA
Electrical Characteristics: Unless otherwise stated, specifications apply for -40C < T
A
< 85C, -40C < T
J
< 150C,
3V < V
C
< 20V, 8.2V < V
CC
< 20V, R
T
= 12k, C
T
= 390pF.
3
CS51021/22/23/24
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Electrical Characteristics: -40C < T
A
< 85C, -40C < T
J
< 150C, 3V < V
C
< 20V, 8.2V < V
CC
< 20V,
R
T
= 12k, C
T
= 390pF, unless otherwise stated
s
Error Amplifier continued
COMP High Voltage
V
FB
= 2.3V
4.35
4.8
5
V
COMP Low Voltage
V
FB
= 2.7V
0.4
0.8
1.2
V
PS Ripple Rejection
FREQ = 120Hz (Note 1)
60
85
dB
SS Clamp, V
COMP
V
SS
=2.5V, V
FB
= 0V, I
SET
= 2V
2.4
2.5
2.6
V
I
LIM(SET)
Clamp
(Note 1)
0.95
1
1.15
V
s
Oscillator
Accuracy
R
T
= 12k, C
T
= 390pF
230
255
280
kHz
Voltage Stability
Delta Frequency 8.2V < V
CC
< 20V
2
3
%
Temperature Stability
T
MIN
< T
A
< T
MAX
(Note1)
8
%
Min Charge & Discharge Time
(Note1)
0.333
s
Duty Cycle Accuracy
R
T
= 12k, C
T
= 390pF
70
77
83
%
Peak Voltage
(Note 1)
3
V
Valley Voltage
(Note 1)
1.5
V
Valley Clamp Voltage
10k Resistor to ground on R
T
C
T
1.2
1.4
1.6
V
Discharge Current
0.8
1
1.2
mA
Discharge Current
T
A
=25C (Note 1)
0.925
1
1.075
mA
s
Synchronization (CS51021/23)
Input Threshold
1.0
1.5
2.7
V
Output Pulsewidth
160
260
360
ns
Output High Voltage
I
SYNC
= 100A
3.5
4.3
4.8
V
Input Resistance
(Note 1)
35
70
140
k
Drive Delay
SYNC to GATE RESET
80
120
150
ns
Output Drive Current
1k Load
1.25
2
3.5
mA
s
SLEEP (CS51022/24)
SLEEP Input Threshold
Active High
1.0
1.5
2.7
V
SLEEP Input Current
V
SLEEP
= 4V
11
25
46
A
I
CC
@ SLEEP
V
CC
15V
50
100
A
s
GATE Driver
HIGH Voltage
Measure V
C
-GATE, V
C
= 10V, 150mA Load
1.5
2.2
V
LOW Voltage
Measure GATE-PGnd, 150mA SINK
1.2
1.5
V
HIGH Voltage Clamp
V
C
= 20V, 1nF
11
13.5
16
V
LOW Voltage Clamp
Measured at 10mA Output Current
0.6
0.8
V
Peak Current
V
C
= 20V, 1nF (Note 1)
1
A
UVL Leakage
V
C
= 20V, measured at 0V
-1
-50
A
RISE Time
Load = 1nF, 1V < GATE < 9V,
60
100
ns
V
C
= 20V, T
A
= 25C
FALL Time
Load = 1nF, 9V > GATE > 1V, V
C
= 20V
15
40
ns
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CS51021/22/23/24
4
Electrical Characteristics: Unless otherwise stated, specifications apply for -40C < T
A
< 85C, -40C < T
J
< 150C,
3V < V
C
< 20V, 8.2V < V
CC
< 20V, R
T
= 12k, C
T
= 390pF.
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
s
SLOPE Compensation
Charge Current
SLOPE = 2V
-63
-53
-43
A
COMP Gain
Fraction of slope voltage added
0.095
0.100
0.105
V/V
to I
SENSE
(Note 1)
Discharge Voltage
SYNC = 0V
0.1
0.2
V
s
Current Sense
OFFSET Voltage
(Note 1)
0.09
0.10
0.11
V
Blanking Time
55
160
ns
Blanking Disable Voltage
Adjust V
FB
1.8
2
2.2
V
Second Current Threshold Gain
1.21
1.33
1.45
V/V
I
SENSE
Input Resistance
5
k
Minimum On Time
GATE High to Low
30
70
110
ns
Gain
(Note 1)
0.78
0.80
0.82
V/V
s
OV & UV Voltage Monitors
OV Monitor Threshold
2.4
2.5
2.6
V
OV Hysteresis Current
-10
-12.5
-15
A
UV Monitor Threshold
1.38
1.45
1.52
V
UV Monitor Hysteresis
25
75
100
mV
s
SOFT START (SS)
Charge Current
SS = 2V
-70
-55
-40
A
Discharge Current
SS = 2V
250
1000
A
Charge Voltage, V
SS
4.4
4.7
5
V
Discharge Voltage, V
SS
0.25
0.27
0.30
V
Note 1: Guaranteed by Design, not 100% tested in production.
16L PDIP & SO Narrow
1
GATE
External power switch driver with 1.0A peak capability.
2
I
SENSE
Current sense amplifier input.
3
SYNC
Bi-directional synchronization. Locks to the highest frequency.
(CS51021/23)
3
SLEEP
Active high chip disable. In sleep mode, V
REF
and GATE are
(CS51022/24)
turned off.
4
SLOPE
Additional slope to the current sense signal. Internal current
source charges the external capacitor.
5
UV
Undervoltage protection monitor.
6
OV
Overvoltage protection monitor.
CS51021/22/23/24
5
Package Pin Description: continued
PACKAGE PIN #
PIN SYMBOL
FUNCTION
+
-
4.75V
V
REF
DISABLE
1.33
55
A
VREF = 5V
OSC
Discharge
Latch
2.5V
PWM
Comp
S
R
Q
+
E/A
+
START
STOP
+
-
I
SET
Clamp
SS
Clamp
12.5
A
OV
Monitor
UV
Monitor
+
0.1V
0.1
+
V
REF
53
A
2V
V
REF
_OK
Vcc_OK
SS
Monitor
V
FB
Monitor
+
1.45V
55ns
Blank
0.8
10k
20k
V
REF
13.5V
V
ISense
2.5V
4.3V
200ns
G1
F1
G2
D1
Q2
G3
FAULT
ZD1
D4
+
4.7V
D2
D3
SS
PGnd
V
C
GATE
I
SENSE
SLOPE
COMP
V
FB
OV
I
SET
V
REF
V
CC
LGnd
SYNC
R
T
C
T
UV
G4
SLEEP
2nd
Threshold
Figure 1: CS51021/22/23/24 Block Diagram
Block Diagram
16L PDIP & SO Narrow
7
R
T
C
T
Timing resistor R
T
and capacitor C
T
determine oscillator frequen-
cy and maximum duty cycle, D
MAX
.
8
I
SET
Voltage at this pin sets pulse-by-pulse overcurrent threshold, and
second threshold (1.33 times higher) with Soft Start retrigger (hic-
cup mode).
9
V
FB
Feedback voltage input. Connected to the error amplifier invert-
ing input.
10
COMP
Error amplifier output. Frequency compensation network is usu-
ally connected between COMP and V
FB
pins.
11
SS
Charging external capacitor restricts error amplifier output volt-
age during the start or fault conditions (hiccup).
12
LGnd
Logic ground.
13
V
REF
5.0V reference voltage output.
14
V
CC
Logic supply voltage.
15
PGnd
Output power stage ground connection.
16
V
C
Output power stage supply voltage.
6
CS51021/22/23/24
Circuit Description
Figure 2: Typical Waveforms
Powering the IC
The IC has two supply and two ground pins. V
C
and
PGnd pins provide high speed power drive for the exter-
nal power switch. V
CC
and LGnd pins power the control
portion of the IC. The internal logic monitors the supply
voltage, V
CC
. During abnormal operating conditions, the
output is held low. The CS51021/22/23/24 requires only
75A of startup current.
Voltage Feedback
The output voltage is monitored via the V
FB
pin and is
compared with the internal 2.5V reference. The error
amplifier output minus one diode drop is divided by 3
and connected to the negative input of the PWM compara-
tor. The positive input of the PWM comparator is connect-
ed to the modified current sense signal. The oscillator
turns the external power switch on at the beginning of
each cycle. When current sense ramp voltage exceeds the
reference side of PWM comparator, the output stage latch-
es off. It is turned on again at the beginning of the next
oscillator cycle.
Current Sense and Protection
The current is monitored at the I
SENSE
pin. The
CS51021/22/23/24 has leading edge blanking circuitry
that ignores the first 55ns of each switching period.
Blanking is disabled when V
FB
is less than 2V so that the
minimum on-time of the controller does not have an addi-
tional 55ns of delay time during fault conditions. For the
remaining portion of the switching period, the current
sense signal, combined with a fraction of the slope com-
pensation voltage, is applied to the positive input of the
PWM comparator where it is compared with the divided
by three error amplifier output voltage. The pulse-by-
pulse overcurrent protection threshold is set by the volt-
age at the I
SET
pin. This voltage is passed through the I
SET
Clamp and appears at the non-inverting input of the PWM
comparator, limiting its dynamic range according to the
following formula:
Overcurrent Threshold= 0.8 V
I(SENSE)
+0.1V + 0.1 V
SLOPE
where
V
I(SENSE)
is voltage at the I
SENSE
pin
and
V
SLOPE
is voltage at the SLOPE pin.
During extreme overcurrent or short circuit conditions,
the slope of the current sense signal will become much
steeper than during normal operation. Due to loop propa-
gation delay, the sensed signal will overshoot the pulse-
by-pulse threshold eventually reaching the second over-
current protection threshold which is 1.33 times higher
than the first threshold and is described by the following
equation:
2nd Threshold = 1.33 V
I(SET)
Exceeding the second threshold will reset the Soft Start
capacitor C
SS
and reinitiate the Soft Start sequence, repeat-
ing for as long as the fault condition persists.
Soft Start
During power up, when the output filter capacitor is dis-
charged and the output voltage is low, the voltage across
the Soft Start capacitor (V
SS
) controls the duty cycle. An
internal current source of 55A charges C
SS
. The maxi-
mum error amplifier output voltage is clamped by the SS
Clamp. When the Soft Start capacitor voltage exceeds the
error amplifier output voltage, the feedback loop takes
over the duty cycle control. The Soft Start time can be esti-
mated with the following formula:
t
SS
= 9 10
4
C
SS
The Soft Start voltage, V
SS
, charges and discharges
between 0.25V and 4.7V.
Slope Compensation
DC-DC converters with current mode control require a
current sense signal with slope compensation to avoid
instability at duty cycles greater than 50%. Slope capacitor
C
S
is charged by an internal 53A current source and is
discharged during the oscillator discharge time. The slope
compensation voltage is divided by 10 and is added to the
current sense voltage, V
I(SENSE)
. The signal applied to the
Theory of Operation
4.3V
200ns
0V
T
CH
T
DIS
V
IN
0V
0V
0V
V
SLOPE
IS + 0.1 SLOPE
IS
55ns Blanking
PWM COMP
SLOPE
R
T
C
T
SYNC
IS
V
DS
0V
0V
GATE
V
COMP
7
input of the PWM comparator is a combination of these
two voltages. The slope compensation,
, is calcu-
lated using the following formula:
= 0.1
It should be noted that internal capacitance of the IC will
cause an error when determining slope compensation
capacitance C
S
. This error is typically small for large val-
ues of C
S
, but increases as C
S
becomes small and compara-
ble to the internal capacitance. The effect is apparent as a
reduction in charging current due to the need to charge
the internal capacitance in parallel with C
S
. Figure 3 shows
a typical curve indicating this decrease in available charg-
ing current.
Figure 3: The slope compensation pin charge current reduces when a
small capacitor is used.
Undervoltage (UV) and Overvoltage (OV) Monitor
Two independent comparators monitor OV and UV con-
ditions. A string of three resistors is connected in series
between the monitored voltage (usually the input voltage)
and ground (see Figure 4). When voltage at the OV pin
exceeds 2.5V, an overvoltage condition is detected and
GATE shuts down. An internal 12.5A current source
turns on and feeds current into the external resistor, R
3
,
creating a hysteresis determined by the value of this resis-
tor (the higher the value, the greater the hysteresis). The
hysteresis voltage of the OV monitor is determined by the
following formula:
V
OV(HYST)
= 12.5A R
3
where R
3
is a resistor connected from the OV pin to ground.
When the monitored voltage is low and the UV pin is less
than 1.45V, GATE shuts down. The UV pin has fixed 75mV
hysteresis.
Both OV and UV conditions are latched until the Soft Start
capacitor is discharged. This way, every time a fault con-
dition is detected the controller goes through the power
up sequence.
Figure 4: UV/OV Monitor Divider
To calculate the OV/UV resistor divider:
1. Solve for R
3
, based on OV hysteresis requirements.
R
3
= '
where V
OV(HYST)
is the desired amount of overvoltage hys-
teresis, and V
MAX
is the input voltage at which the supply
will shut down.
2. Find the total impedance of the divider.
R
TOT
= R
1
+ R
2
+ R
3
=
3. Determine the value of R
2
from the UV threshold condi-
tions.
R
2
=
- R
3,
where V
MIN
is the UV voltage at which the supply will
shut down.
4. Calculate R
1
.
R
1
= R
TOT
- R
2
- R
3
5. The undervoltage hysteresis is given by:
V
UV(HYST)
=
Synchronization
A bi-directional synchronization is provided to synchro-
nize several controllers. When SYNC pins are connected
together, the converters will lock to the highest switching
frequency. The fastest controller becomes the master, pro-
ducing a 4.3V, 200ns pulse train. Only one, the highest fre-
quency SYNC signal, will appear on the SYNC line.
Sleep
The sleep input is an active high input. The CS51022/51024
is placed in sleep mode when SLEEP is driven high. In
sleep mode, the controller and MOSFET are turned off.
Connect to Gnd for normal operation. The sleep mode
operates at V
CC
15V.
Oscillator and Duty Cycle Limit
The switching frequency is set by R
T
and C
T
connected to
the R
T
C
T
pin. C
T
charges and discharges between 3V and
1.5V.
The maximum duty cycle is set by the ratio of the on time,
t
ON
, and the whole period, T = t
ON
+ t
OFF
. Because the
V
MIN
0.075
1.45
1.45 R
TOT
V
MIN
V
MAX
R
3
2.5
V
OV(HYST)
2.5V
V
MAX
12.5A
V
IN
V
UV
V
OV
R
3
R
2
R
1
60
55
50
45
40
35
30
25
20
10
100
1000
Charging Current (
A)
Compensation Cap (pF)
53A
C
S
dV
SLOPE
dt
dV
SLOPE
dt
Circuit Description: continued
CS51021/22/23/24
CS51021/22/23/24
8
timing capacitor's discharge current is trimmed, the maxi-
mum duty cycle is well defined. It is determined by the
ratio between the timing resistor R
T
and the timing capaci-
tor C
T
. Refer to figures 5 and 6 to select appropriate values
for R
T
and C
T.
f
SW
=
; T
SW
= t
CH
+ t
DIS
Figure 5: Frequency vs. R
T
for Discrete Capacitor Values.
Figure 6: Duty Cycle vs. R
T
for Discrete Capacitor Values.
90
80
70
60
50
40
10
15
20
25
30
35
5
40
45
50
Duty Cycle (%)
R
T
(k
)
2
3
4
5
6
7
8
55
100
1
1. C
T
= 47pF
2. C
T
= 100pF
3. C
T
= 150pF
4. C
T
= 220pF
5. C
T
= 390pF
6. C
T
= 470pF
7. C
T
= 560pF
8. C
T
= 680pF
2500
2000
1500
1000
500
0
10
15
20
25
30
35
5
40
45
50
Frequency (kHz)
R
T
(k
)
1
2
3
4
5
6
7
8
1. C
T
= 47pF
2. C
T
= 100pF
3. C
T
= 150pF
4. C
T
= 220pF
5. C
T
= 390pF
6. C
T
= 470pF
7. C
T
= 560pF
8. C
T
= 680pF
1
T
SW
Circuit Description: continued
CS51021/22/23/24
9
Part Number
Description
CS51021ED16
16L SO Narrow
CS51021EDR16
16L SO Narrow (tape & reel)
CS51022ED16
16L SO Narrow
CS51022EDR16
16L SO Narrow (tape & reel)
CS51023ED16
16L SO Narrow
CS51023EDR16
16L SO Narrow (tape & reel)
CS51024ED16
16L SO Narrow
CS51024EDR16
16L SO Narrow (tape & reel)
Rev. 2/22/99
Ordering Information
Package Specification
Thermal Data
16L SO Narrow
R
JC
typ
28
C/W
R
JA
typ
115
C/W
D
Lead Count
Metric
English
Max
Min
Max Min
16L SO Narrow
10.00
9.80
.394
.386
PACKAGE DIMENSIONS IN mm (INCHES)
PACKAGE THERMAL DATA
1999 Cherry Semiconductor Corporation
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
Surface Mount Narrow Body (D); 150 mil wide
1.27 (.050) BSC
0.51 (.020)
0.33 (.013)
6.20 (.244)
5.80 (.228)
4.00 (.157)
3.80 (.150)
1.57 (.062)
1.37 (.054)
D
0.25 (0.10)
0.10 (.004)
1.75 (.069) MAX
1.27 (.050)
0.40 (.016)
REF: JEDEC MS-012
0.25 (.010)
0.19 (.008)