1
Features
V
C
V
FB
CS
V
CC
V
GATE
Gnd
PGnd
C
OSC
CS51031
C
OSC
150pF
CS
0.1
mF
R
A
1.5k
W
R
B
2.5k
W
C
O
100
mF 2
D
1
MP
1
5V - 12V
L
4.7
mH
C
RR
0.1
mF
C
IN
47
mF
V
O
3.3V @ 3A
MBRS360
IRF7416
V
GATE
20
W
RV
CC
10
W
CV
CC
100
mF
.01
mF
100
s
1A Totem Pole Output
Driver
s
High Speed Oscillator
(700kHz max)
s
No Stability
Compensation Required
s
Lossless Short Circuit
Protection
s
V
CC
Monitor
s
2% Precision Reference
s
Programmable Soft Start
Package Options
CS51031
Fast PFET Buck Controller
Does Not Require Compensation
CS51031
Description
The CS51031 is a switching con-
troller for use in DC-DC converters.
It can be used in the buck topology
with a minimum number of exter-
nal components. The CS51031 con-
sists of a V
CC
monitor for control-
ling the state of the device, 1.0A
power driver for controlling the
gate of a discrete P-channel transis-
tor, fixed frequency oscillator, short
circuit protection timer, pro-
grammable soft start, precision ref-
erence, fast output voltage monitor-
ing comparator, and output stage
driver logic with latch.
The high frequency oscillator
allows the use of small inductors
and output capacitors, minimizing
PC board area and systems cost.
The programmable soft start
reduces current surges at start up.
The short circuit protection timer
significantly reduces the duty cycle
to approximately 1/30 of its cycle
during short circuit conditions.
The CS51031 is available in 8L SO
and 8L PDIP plastic packages.
Typical Application Diagram
1
V
GATE
PGnd
C
OSC
Gnd
V
C
CS
V
CC
V
FB
8 Lead SO Narrow & PDIP
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
A Company
Rev. 2/13/98
Power Supply Voltage, V
CC
........................................................................................................................................................20V
Driver Supply Voltage, V
C
..........................................................................................................................................................20V
Driver Output Voltage, V
GATE
...................................................................................................................................................20V
C
OSC
, CS, V
FB
(Logic Pins) ............................................................................................................................................................6V
Peak Output Current ................................................................................................................................................................. 1.0A
Steady State Output Current ................................................................................................................................................200mA
Operating Junction Temperature, T
J
..................................................................................................................................... 150C
Operating Temperature Range, T
A
............................................................................................................................-40 to 125C
Storage Temperature Range, T
S
...................................................................................................................................-65 to 150C
ESD (Human Body Model).........................................................................................................................................................2kV
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260C peak
Reflow (SMD styles only) ......................................................................................60 sec. max above 183C, 230C peak
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2
CS51031
Absolute Maximum Ratings
Electrical Characteristics: Specifications apply for 4.5 V
CC
16V, 3V V
C
16V,
-40C T
J
125C, unless otherwise specified.
s Oscillator
V
FB
= 1.2V
Frequency C
OSC
= 470pF
160
200
240
kHz
Charge Current
1.4V < V
COSC
< 2V
110
A
Discharge Current
2.7V > V
COSC
> 2V
660
A
Maximum Duty Cycle
1 (t
OFF
/t
ON
)
80.0
83.3
%
s Short Circuit Timer
V
FB
= 1.0V; CS = 0.1F; V
COSC
= 2V
Charge Current
1V < V
CS
< 2V
175
264
325
A
Fast Discharge Current
2.55V > V
CS
> 2.4V
40
66
80
A
Slow Discharge Current
2.4V > V
CS
> 1.5V
4
6
10
A
Start Fault Inhibit Time
0V < V
CS
< 2.5V
0.70
0.85
1.40
ms
Valid Fault Time
2.6V > V
CS
> 2.4V
0.2
0.3
0.45
ms
GATE Inhibit Time
2.4V > V
CS
> 1.5V
9
15
23
ms
Fault Duty Cycle
2.5
3.1
4.6
%
s CS Comparator
V
FB
= 1V
Fault Enable CS Voltage
2.5
V
Max. CS Voltage
V
FB
= 1.5V
2.6
V
Fault Detect Voltage
V
CS
when GATE goes high
2.4
V
Fault Inhibit Voltage
Minimum V
CS
1.5
V
Hold Off Release Voltage
V
FB
= 0V
0.4
0.7
1.0
V
Regulator Threshold
V
CS
= 1.5V
0.725
0.866
1.035
V
Voltage Clamp
s V
FB
Comparators
V
COSC
= V
CS
= 2V
Regulator Threshold Voltage T
J
= 25C (note 1)
1.225
1.250
1.275
V
T
J
= -40 to 125C
1.210
1.250
1.290
V
Fault Threshold Voltage
T
J
= 25C (note 1)
1.12
1.15
1.17
V
T
J
= -40 to 125C
1.10
1.15
1.19
V
Threshold Line Regulation
4.5V V
CC
16V
6
15
mV
Input Bias Current
V
FB
= 0V
1
4
A
Voltage Tracking
(Regulator Threshold Voltage -
70
100
120
mV
Fault Threshold Voltage)
Input Hysteresis Voltage
4
20
mV
CS51031
3
Electrical Characteristics: Specifications apply for 4.5 V
CC
16V, 3V V
C
16V, -40C T
J
125C,
unless otherwise specified.
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
8L SO Narrow & PDIP
1
V
GATE
Driver pin to gate of external PFET.
2
PGnd
Output power stage ground connection.
3
C
OSC
Oscillator frequency programming capacitor.
4
Gnd
Logic ground.
5
V
FB
Feedback voltage input.
6
V
CC
Logic supply voltage.
7
CS
Soft start and fault timing capacitor.
8
V
C
Driver supply voltage.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s Power Stage
V
CC
= V
C
= 10V; V
FB
= 1.2V
GATE DC Low Saturation
V
COSC
= 1V; 200mA Sink
1.2
1.5
V
Voltage
GATE DC High Saturation
V
COSC
= 2.7V; 200mA Source; V
C
= V
GATE
1.5
2.1
V
Voltage
Rise Time
C
GATE
= 1nF; 1.5V < V
GATE
< 9V
25
60
ns
Fall Time
C
GATE
= 1nF; 9V > V
GATE
> 1.5V
25
60
ns
s V
CC
Monitor
Turn On Threshold
4.200
4.400
4.600
V
Turn Off Threshold
4.085
4.300
4.515
V
Hysteresis
65
130
200
mV
s Current Drain
I
CC
4.5V < V
CC
< 16V, Gate switching
4.5
6.0
mA
I
C
3V < V
C
< 16V, Gate non-switching
2.7
4.0
mA
Shutdown I
CC
V
CC
= 4,
500
900
A
Note 1: Guaranteed by design not 100% tested in production.
CS51031
4
Block Diagram
G5
C
OSC
CS
V
REF
V
C
V
GATE
PGnd
V
FB
Gnd
R
S
2.5V
1.5V
1.25V
1.15V
Q
F2
G2
G1
A1
A6
RG
V
CC
3.3V
V
CC
OK
A3
2.4V
G3
V
REF
= 3.3V
A2
2.5V
1.5V
I
C
7I
C
V
REF
V
CC
+
-
I
T
+
Q
I
T
5
I
T
55
G4
Fault
Comp
+
-
+
-
+
-
A4
0.7V
2.3V
Q
R
Q
S
F1
Slow Discharge
Comparator
Slow Discharge
Flip-Flop
CS Charge
Sense
Comparator
CS
Comparator
Oscillator
Comparator
V
FB
Comparator
V
GATE
Flip-Flop
Hold
Off
Comp
Control Scheme
The CS51031 monitors and the output voltage to determine
when to turn on the PFET. If V
FB
falls below the internal
reference voltage of 1.25V during the oscillators charge
cycle, the PFET is turned on and remains on for the dura-
tion of the charge time. The PFET gets turned off and
remains off during the oscillators discharge time with the
maximum duty cycle to 80%. It requires 7mV typical, and
20mV maximum ripple on the V
FB
pin is required to oper-
ate. This method of control does not require any loop sta-
bility compensation.
Startup
The CS51031 has an externally programmable soft start fea-
ture that allows the output voltage to come up slowly, pre-
venting voltage overshoot on the output.
At startup, the voltage on all pins is zero. As V
CC
rises, the
V
C
voltage along with the internal resistor R
G
keeps the
PFET off. As V
CC
and V
C
continue to rise, the oscillator
capacitor (C
OSC
) and the Soft start/Fault Timing capacitor
(CS) charges via internal current sources. C
OSC
gets
charged by the current source I
C
and CS gets charged by
the I
T
source combination described by:
I
CS
= I
T
-
(
+
)
.
The internal Holdoff Comparator ensures that the external
PFET is off until V
CS
> 0.7V, preventing the GATE flip-flop
(F2) from being set. This allows the oscillator to reach its
operating frequency before enabling the drive output. Soft
start is obtained by clamping the V
FB
comparators (A6)
reference input to approximately 1/2 of the voltage at the
CS pin during startup, permitting the control loop and the
output voltage to slowly increase. Once the CS pin charges
above the Holdoff Comparator trip point of 0.7V, the low
feedback to the V
FB
Comparator sets the GATE flip-flop
during C
OSC
s charge cycle. Once the GATE flip-flop is set,
V
GATE
goes low and turns on the PFET. When V
CS
exceeds
I
T
5
I
T
55
Theory of Operation
Circuit Description
Figure 1: Block Diagram for CS51031
CS51031
5
2.4V, the CS charge sense comparator (A4) sets the V
FB
comparator reference to 1.25V completing the startup
cycle.
Lossless Short Circuit Protection
The CS51031 has lossless short circuit protection since
there is no current sense resistor required. When the volt-
age at the CS pin (the fault timing capacitor voltage ) reach-
es 2.5V during startup, the fault timing circuitry is enabled.
During normal operation the CS voltage is 2.6V. During a
short circuit or a transient condition, the output voltage
moves lower and the voltage at V
FB
drops. If V
FB
drops
below 1.15V, the output of the fault comparator goes high
and the CS51031 goes into a fast discharge mode. The fault
timing capacitor, CS, discharges to 2.4V. If the V
FB
voltage
is still below 1.15V when the CS pin reaches 2.4V, a valid
fault condition has been detected. The slow discharge
comparator output goes high and enables gate G5 which
sets the slow discharge flip flop. The Vgate flip flop resets
and the output switch is turned off. The fault timing
capacitor is slowly discharged to 1.5V. The CS51031 then
enters a normal startup routine. If the fault is still present
when the fault timing capacitor voltage reaches 2.5V, the
fast and slow discharge cycles repeat as shown in figure 2.
If the V
FB
voltage is above 1.15V when CS reaches 2.4V a
fault condition is not detected, normal operation resumes
and CS charges back to 2.6V. This reduces the chance of
erroneously detecting a load transient as a fault condition.
Figure 2. Voltage on start capacitor (V
GS
), the gate (V
GATE
), and in the
feedback loop (V
FB
), during startup, normal and fault conditions.
Buck Regulator Operation
Figure 3. Buck regulator block diagram.
A block diagram of a typical buck regulator is shown in
Figure 3. If we assume that the output transistor is initially
off, and the system is in discontinuous operation, the
inductor current I
L
is zero and the output voltage is at its
nominal value. The current drawn by the load is supplied
by the output capacitor C
O
. When the voltage across C
O
drops below the threshold established by the feedback
resistors R1 and R2 and the reference voltage V
REF
, the
power transistor Q1 switches on and current flows through
the inductor to the output. The inductor current rises at a
rate determined by (V
IN
-V
OUT
)/L. The duty cycle (or on
time) for the CS51031 is limited to 80%. If output voltage
remains higher than nominal during the entire C
OSC
change time, the Q1 does not turn on, skipping the pulse.
Control
Feedback
V
IN
L
D
1
R
1
R
2
R
LOAD
C
O
Q1
C
IN
2.5V
0V
FAULT
NORMAL OPERATION
START
T
START
td1
td2
t
FAULT
t
RESTART
t
FAULT
S2
S2
S2
S3
S3
S3
S3
S1
S1
S1
2.6V
2.4V
1.5V
0V
1.25V
1.15V
V
CS
V
GATE
V
FB
Circuit Description: continued
Applications Information
Specifications 12V to 5V, 3A Buck converter
V
IN
= 12V 20% (i.e. 14.4V max., 12Vnom., 9.6V min.)
V
OUT
= 5V 2%
I
OUT
= 0.3A to 3A
Output ripple voltage < 50mV max.
Efficiency > 80%
f
SW
= 200kHz
1) Duty cycle estimates
Since the maximum duty cycle D, of the CS51031 is limited
to 80% min., it is necessary to estimate the duty cycle for
the various input conditions over the complete operating
range.
The duty cycle for a buck regulator operating in a continu-
ous conduction mode is given by:
D =
V
OUT
+ V
F
V
IN
- V
SAT
CS51031 Design Example
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