Features

3.3V

SYNC

COMP2

PGnd

COMP1

ENABLE

LGnd

FB1

FB2

REF

GATE1

GATE2

R6
1k

CS5127

C12, C13

2 x 680

R9
2k

IRL3103S

R11

R2
27k

FFB1

FFB2

Q2
IRL3103S

C16
100

C8
1

R3
18k

1N5821

C15
100

C1, C2
2 x 680

330pF

2.8V

C10, C11
2 x 680

+5V

D1
1N5821

C14
330pF

1540

1270

R10

20k

0.1

R1
20k

Q1
FMMT2222ACT

12V

C4, C5

2 x 680

C17
330pF

20k

R7
2400

R8
1500

C9
0.1

Nonsynchronous Buck
Design

ª Control Topology

100ns Transient Loop
Response

Programmable Oscillator
Frequency

30ns Typical Gate Rise
and 10ns Fall Times
(No Load)

Frequency
Synchronization Input

ENABLE Input Controls
Channel 2 Gate Driver

5V/10mA Reference
Output

Package Option

CS5127

Dual Output Nonsynchronous Buck Controller

with Sync Function and Second Channel Enable

CS5127

Description

The CS5127 is a fixed frequency
dual output nonsynchronous buck
controller. It contains circuitry for
regulating two separate outputs.
Each output channel contains a
high gain error amplifier, a com-
parator and latch, and a totem-pole
output driver capable of providing
DC current of 100mA and peak cur-
rent in excess of 0.5A. A common
oscillator controls switching for
both channels, and a sync lead is
provided to allow parallel supply
operation or shifting of the switch-
ing noise spectrum. An on-chip 5V
reference is capable of providing as
much as 10mA of current for exter-
nal circuitry. The CS5127 also
contains two undervoltage lockout

circuits. The first lockout releases
when V

reaches 8.4V, while the

second lockout ensures that V

REF

higher than 3.6V. The outputs are
held in a low state until both lock-
outs have released. The controller is
configured to utilize the V

ª con-

trol method to achieve the fastest
possible transient response and
best overall regulation. This dual
controller is a cost-effective solu-
tion for providing V

CORE

and V

power solutions in computing
applications using a single con-
troller. The CS5127 will operate
over an input voltage range of 9.4V
to 20V and is available in a 16 lead
wide body surface mount package.

Applications Diagram

16 Lead SOIC Wide

SYNC

COMP2

PGND

COMP1

ENABLE

LGND

FB1

FB2

REF

GATE1

GATE2

FFB1

FFB2

12V, 5V to 2.8V @ 7A and 3.3V @ 7A for 233MHz Pentium

Processor with MMXª Technology

is a trademark of Switch Power, Inc.

Pentium is a registered trademark and MMX is a trademark of Intel Corporation

Rev. 11/3/98

Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786

Email: info@cherry-semi.com

Web Site: www.cherry-semi.com

A Company

CS5127

Absolute Maximum Ratings

Lead Symbol

Lead Name

MAX

MIN

SOURCE

SINK

Operating Junction Temperature, T

..................................................................................................................................... 150¡C

Storage Temperature Range, T

...................................................................................................................................-65 to 150¡C

ESD (Human Body Model).........................................................................................................................................................2kV
Lead Temperature Soldering: Reflow (SMD styles only).............................................60 sec. max above 183¡C, 230¡C peak

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Electrical Characteristics: 0¡C < T

< 70¡C; 0¡C < T

< 125¡C; 9.4V < V

< 20V; C

= 330 pF; R

= 27k½;

unless otherwise stated.

SYNC

Oscillator Synchronization Input

5.5V

-0.3V

5 mA

Oscillator Integrating Capacitor

5.5V

-0.3V

1mA

Oscillator Charge Current Resistor

5.5V

-0.3V

1mA

FB1

, V

FB2

Voltage Feedback Inputs

5.5V

-0.3V

N/A

COMP1, COMP2

Error Amplifier Outputs

7.5V

-0.3V

2mA

50mA

FFB1

, V

FFB2

PWM Ramp Inputs

5.5V

-0.3V

1mA

GATE1, GATE2

FET Gate Drive Outputs

20V

-0.3V DC,

200mA DC,

-2.0V for

1A peak

t < 50ns

(t < 100µs)

LGnd

Reference Ground and IC Substrate

25 mA

N/A

PGnd

Power Ground

1A Peak,

N/A

200mA DC

ENABLE

Channel 2 Enable

5.5V

-0.3V

1mA

N/A

REF

Reference Voltage Output

5.5V

-0.3V

150mA

5mA

(short circuit)

Power Supply Input

20V

-0.3V

N/A

200mA DC,

1A peak

(t < 100µs)

s Reference Section

REF

Output Voltage

Room Temperature,

4.9

5.0

5.1

VREF

= 1mA, V

= 12V

Line Regulation

Load Regulation

1 mA < I

VREF

< 10 mA

REF

Variation over Line, Load

4.85

5.15

and Temperature
Output Short Circuit Current

100

150

s Oscillator Section

Oscillator Frequency Variation

175

210

245

kHz

over Line and Temperature
Maximum Duty Cycle

Sync Threshold

0.8

1.6

2.4

Sync Bias Current

SYNC

= 2.4V

170

250

µA

SYNC

= 5.0V

430

750

Sync Propagation Delay

230

CS5127

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Electrical Characteristics: 0¡C < T

< 70¡C; 0¡C < T

< 125¡C; 9.4V < V

< 20V; C

= 330 pF; R

= 27k½;

unless otherwise stated.

s Error Amplifiers

Reference Voltage

COMP

= V

VFB

1.245

1.275

1.300

Input Bias Current

= 1.275V

0.1

1.0

µA

Open Loop Gain

Unity Gain Bandwidth

1.0

MHz

PSRR

f = 120Hz

COMP Source Current

COMP

= 3V, V

VFB

= 1.1V

0.9

1.3

2.0

COMP Sink Current

COMP

= 1.2V, V

VFB

= 1.45V

COMP Output Low Voltage

VFB

= 1.45V, I

COMP

= 0.3 mA

0.50

0.85

1.00

s PWM Comparators

FFB

Bias Current

FFB

= 0

2.0

µA

Propagation Delay

FFB

rising to V

GATE

falling

100

250

Common Mode

2.9

3.3

Maximum Input Voltage

s ENABLE Lead

ENABLE High Threshold

channel 2 enabled

1.5

2.5

3.5

ENABLE Bias Current

ENABLE

= 0

100

250

400

µA

s Gate Driver Outputs

Output Low Saturation Voltage

GATE

= 20 mA

0.1

0.4

GATE

= 100 mA

0.25

2.50

Output High Saturation Voltage

GATE

= 20 mA

1.5

2.0

GATE

= 100 mA

1.6

3.0

Output Voltage under Lockout

= 6V, I

GATE

= 1 mA

0.1

0.2

Output Rise Time

no load

Output Fall Time

no load

s Undervoltage Lockout

Turn On Threshold

7.4

8.4

9.4

Turn Off Threshold

6.8

7.8

8.8

s Supply Current

Start Up Current

= 6V

0.4

0.8

Operating Current

= 0V, no load

17.5

CS5127

Package Lead Description

PACKAGE LEAD #

LEAD SYMBOL

FUNCTION

16 Lead SO Wide

SYNC

A pulse train on this lead will synchronize the oscillator. Sync threshold level

is 2.4V. Synchronization frequency should be at least 10% higher than the reg-
ular operating frequency. The sync feature is level sensitive.

The oscillator integrating capacitor is connected to this lead.

The oscillator charge current setting resistor is connected to this lead.

FB1

The inverting input of the channel 1 error amplifier is brought out to this lead.
The lead is connected to a resistor divider which provides a measure of the
output voltage. The input is compared to a 1.275V reference, and channel 1
error amp output is used as the V

ª PWM control voltage.

COMP1

Channel 1 error amp output and PWM comparator input.

FFB1

This lead connects to the non-inverting input of the channel 1 PWM comparator.

GATE1

This lead is the gate driver for the channel 1 FET. It is capable of providing
nearly 1A of peak current.

LGND

This lead provides a ÒquietÓ ground for low power circuitry in the IC. This
lead should be shorted to the PGND lead as close as possible to the IC for best
operating results.

PGND

This lead is the power ground. It provides the return path for the FET gate dis-
charge. It should be shorted to the LGND lead as close as possible to the IC for
best operating results.

GATE2

This lead is the gate driver for the channel 2 FET. See GATE1 lead description
for more details.

FFB2

This lead connects to the non-inverting input of the channel 2 PWM comparator.

COMP2

Channel 2 error amp output and PWM comparator input.

FB2

Inverting input for the channel 2 error amp. See V

FBI

for more details.

ENABLE

The regulator controlled by channel 2 may be turned on and off selectively by
the user. Pulling the ENABLE lead above 3.5V will turn channel 2 on. Setting
the ENABLE lead voltage below 1.5V guarantees that channel 2 is off.

REF

This lead is the output of a ± 3% reference. This reference drives most of the
on-chip circuitry, but will provide a minimum of 10 mA to external circuitry if
needed. The reference is inherently stable and does not require a compensa-
tion capacitor, but use of a decoupling capacitor will reduce noise in the IC.

This lead is the power supply input to the IC. The maximum input voltage
that can be withstood without damage to the IC is 20V.

CS5127

Theory of Operation

The CS5127 is a dual power supply controller that utilizes
the V

ª control method. Two nonsynchronous V

ª buck

regulators can be built using a single controller IC. This IC
is a perfect choice for efficiently and economically provid-
ing core power and I/O power for the latest
high-performance CPUs. Both switching regulators
employ a fixed frequency architecture driven from a
common oscillator circuit.

The V

ª method of control uses a ramp signal generated

by the ESR of the output capacitors. This ramp is propor-
tional to the AC current in the inductor and is offset by the
DC output voltage. V

ª inherently compensates for varia-

tion in both line and load conditions since the ramp signal
is generated from the output voltage. This differs from tra-
ditional methods such as voltage mode control, where an
artificial ramp signal must be generated, and current mode
control, where a ramp is generated from inductor current.

Figure 1: V

ª control diagram.

The V

ª control method is illustrated in Figure 1. Both

the ramp signal and the error signal are generated by the
output voltage. Since the ramp voltage is defined as the
output voltage, the ramp signal is affected by any change
in the output, regardless of the origin of that change. The
ramp signal also contains the DC portion of the output
voltage, allowing the control circuit to drive the output
switch from 0% to about 90% duty cycle.
Changes in line voltage will change the current ramp in
the inductor, affecting the ramp signal and causing the
V

ª control loop to adjust the duty cycle. Since a change

in inductor current changes the ramp signal, the V

method has the characteristics and advantages of current
mode control for line transient response.
Changes in load current will affect the output voltage and
thus will also change the ramp signal. A load step will
immediately change the state of the comparator output
that controls the output switch. In this case, load transient
response time is limited by the comparator response time
and the transition speed of the switch. Notice that the reac-
tion time of the V

ª loop to a load transient is not

dependent on the crossover frequency of the error signal
loop. Traditional voltage mode and current mode methods
are dependent on the compensation of the error signal
loop.
The V

ª error signal loop can have a low crossover fre-

quency, since transient response is handled by the ramp
signal loop. The ÒslowÓ error signal loop provides DC
accuracy. Low frequency roll-off of the error amplifier
bandwidth will significantly improve noise immunity.
This also improves remote sensing of the output voltage,
since switching noise picked up in long feedback traces
can be effectively filtered.
V

ª line and load regulation are dramatically improved

because there are two separate control loops. A voltage

COMP

GATE

FFB

PWM
Comparator

Reference

Voltage

Error
Amplifier

Error Signal

Ramp Signal

ª Control Method

Block Diagram

SYNC

COMP2

COMP1

ENABLE

LGND

FB2

REF

GATE1

GATE2

FFB1

FFB2

PGND

Error
Amplifier

1.275V

PWM
Comparator

Channel 2

Gate Driver

Oscillator

Reference

Undervoltage

Lockout

Bandgap

Voltage

Reference

Undervoltage

Lockout

Channel 2

Gate Driver

Error
Amplifier

1.275V

FB1

PWM
Comparator

CS5127

Theory of Operation: continued

mode controller relies on a change in the error signal to
indicate a change in the line and/or load conditions. The
error signal change causes the error loop to respond with a
correction that is dependent on the gain of the error ampli-
fier. A current mode controller has a constant error signal
during line transients, since the slope of the ramp signal
will change in this case. However, regulation of load tran-
sients still requires a change in the error signal. V

control maintains a fixed error signal for both line and
load variation, since the ramp signal is affected by both.

The CS5127 can be operated in voltage mode if necessary.
For example, if very small values of output ripple voltage
are required, V

ª control may not operate correctly.

Details on how to choose the components for voltage
mode operation are provided in the section on V

FFB

com-

ponent selection.

As output line and load conditions change, the V

ª con-

trol loop modifies the switch duty cycle to regulate the
output voltage. The CS5127 uses a fixed frequency archi-
tecture. Both output channels are controlled from a
common oscillator. The CS5127 can typically provide a
maximum duty cycle of about 90%.

It is sometimes desirable to shift the switching noise spec-
trum to different frequencies. A pulse train applied to the
SYNC lead will terminate charging of the C

lead capacitor

and pull the C

lead voltage to ground for the duration of

the positive pulse level. This reduces the period of oscilla-
tion and increases the switching frequency.
Synchronization must always be done at a frequency
higher than the typical oscillator frequency. Using a lower
frequency will lead to erratic operation and poor regula-
tion. The SYNC pulse train frequency should be at least 10
% higher than the unsynchronized oscillator frequency.
Synchronizing the oscillator will also decrease the maxi-
mum duty cycle. If the nominal oscillator frequency is
200kHz, increasing the oscillator frequency by 10% (to
220kHz) will decrease the maximum duty cycle from a
typical of 90% to about 89%. Increasing the frequency by
25% (to 250kHz) will change the maximum duty cycle to
about 87%. A 50% increase (to 300kHz) gives a maximum
duty cycle of about 85%. The width of the SYNC pulse
should be slightly shorter than the duration of the falling
edge of the C

lead waveform (see Figure 2a) so the SYNC

pulse doesnÕt interfere with the oscillator function.

Figure 2a: Sync pulse duration vs. C

lead discharge time.

The best way to determine if the pulse width is sufficiently
short is to examine the C

lead waveform with an oscillo-

scope. If Òdead spotsÓ are observed in the C

lead waveform,

decreasing the SYNC pulse width should be considered.
Alternatively, the SYNC signal may be AC coupled through
a small capacitor. In this case, care must be taken to ensure
that current pulled out of the IC during the high-to-low tran-
sition of the SYNC signal is limited to less than 5mA.

Figure 2b: Capacitive coupling of the SYNC signal. The external diode
is used to clamp the IC substrate diode if I

SYNC

is greater than 5mA

during the negative portion of the input waveform.

The CS5127 has no on-board current limit circuitry. An
example current limit circuit is provided in the Additional
Application Circuits section of this data sheet.

Overcurrent Protection

Oscillator

SYNC

20k

2200p

Lead Waveform

Sync Lead Waveform

If the sync pulse is longer
than the C

lead discharge

time, a short Òdead spotÓ
will exist during which the
output driver is off.

Sync Function

Constant Frequency

Voltage Mode Control

The feedback (V

FB)

leads are connected to external resistor

dividers to set the output voltage. The on-chip error ampli-
fier is referenced to 1.275V, and the resistor divider values
are determined by selecting the desired output voltage
and the value of the divider resistor connected between
the V

lead and ground.

Resistor R1 is chosen first based on a design trade-off of
system efficiency vs. output voltage accuracy. Low values
of divider resistance consume more current which decreas-
es system efficiency. However, the V

lead has a 1µA

maximum bias current which can introduce errors in the
output voltage if large resistance values are used. The
approximate value of current sinking through the resistor
divider is given by

V(FB)

The output voltage error that can be expected due to the
bias current is given by

Error Percentage =

´ 100%

where R1 is given in ohms. For example, setting R1 = 5K
yields an output voltage error of 0.39% while setting the
feedback divider current at 255µA. Larger currents will
result in reduced error.

Figure 3: Feedback resistor divider.

R2 can be sized according to the following formula once
the desired output voltage and the value of R1 have been
determined:

R2 = R1

-1

There are many factors to consider when choosing the
inductor. Maximum load current, core losses, winding
losses, output voltage ripple, short circuit current, satura-
tion, component height, EMI/EMC and cost are all

variables the designer must consider. Inductance values
between 1µH and 50µH are suitable for use with the CS5127.
Low values within this range minimize the component size
and improve transient response, but larger values reduce
ripple current. Choosing the inductor value requires the
designer to make some choices early in the design. Output
current, output voltage and the input voltage range should
be known in order to make a good choice.
The input voltage range is bracketed by the maximum and
minimum expected values of V

. Most computer applica-

tions use a fairly well-regulated supply with a typical
output voltage tolerance on the order of ±5%. The values
of V

IN(MAX)

and V

IN(MIN)

are used to calculate peak current

and minimum inductance value, respectively. However, if
the supply is well-regulated, these calculations may both
be made using the typical input voltage value with very
little error.
Current in the inductor while operating in the continuous
current mode (CCM) is defined as the load current plus
the inductor ripple current:

= I

OUT

+ I

RIPPLE

The ripple current waveform is triangular, and the current
is a function of the voltage across the inductor, the switch
on-time and the inductor value. Switch on-time is the duty
cycle divided by the operating frequency, and duty cycle
can be defined as the ratio of V

OUT

to V

, such that

RIPPLE

The peak current can be described as the load current plus
half of the ripple current. Peak current must be less than
the maximum rated switch current. This limits the maxi-
mum load current that can be provided. It is also
important that the inductor can deliver the peak current
without saturating.

OUT(MAX)

= I

SWITCH(MAX)

Since the peak inductor current must be less than or equal
to the peak switch current, the minimum value of induc-
tance can be calculated:

MIN

The theoretical limit on load current transient response is a
function of the inductor value, the load transient and the
voltage across the inductor. In conventionally-controlled
regulators, the actual limit is the time required by the con-
trol loop. Conventional current-mode and voltage-mode
control loops adjust the switch duty cycle over many oscil-
lator periods, often requiring tens or even hundreds of

Load Current Transient Response

IN(MIN)

- V

OUT

´ V

IN(MIN)

´ I

SWITCH(MAX)

IN(MAX)

- V

OUT

´ L ´ V

IN(MAX)

- V

OUT

´ L ´ V

Selecting the Inductor

)

OUT

1.275

(

COMP

GATE

Output

Driver

1.275V

OUT

(1E - 6)

´ R1

1.275

1.275V

Selection of Feedback Lead Divider Resistor Values

CS5127

Applications Information

CS5127

Applications Information: continued

microseconds to return to a steady-state. V

ª control uses

the ripple voltage from the output capacitor and a ÒfastÓ
control loop to respond to load transients, with the result
that the transient response of the CS5127 is very close to
the theoretical limit. Response times are defined below.

RESPONSE(INCREASING)

RESPONSE(DECREASING)

Note that the response time to a load decrease is limited
only by the inductor value.

Inductor current rating is an important consideration. If
the regulated output is subject to short circuit or overcur-
rent conditions, the inductor must be sized to handle the
fault without damage. Sizing the inductor to handle fault
conditions within the maximum DC current rating helps to
ensure the coil doesnÕt overheat. Not only does this pre-
vent damage to the inductor, but it reduces unwanted heat
generated by the system and makes thermal management
easier.
Selecting an open core inductor will minimize cost, but
EMI/EMC performance may be degraded. This is a tough
choice, since there are no guidelines to ensure these com-
ponents will not prove troublesome.
Core materials influence the saturation current and satura-
tion characteristics of the inductor. For example, a slightly
undersized inductor with a powdered iron core may pro-
vide satisfactory operation because powdered iron cores
have a ÒsoftÓ saturation curve compared to other core
materials.
Small physical size, low core losses and high temperature
operation will also increase cost. Finally, consider whether
an alternate supplier is an important consideration. All of
these factors can increase the cost of the inductor.

For light load designs, the CS5127 will operate in discon-
tinuous current mode (DCM). In this regime, external
components can be smaller, since high power dissipation is
not an issue. In discontinuous mode, maximum output
current is defined as:

OUT(MAX)

where I

is the maximum current allowed in the switch

FET.

Output capacitors are chosen primarily on the value of
equivalent series resistance, because this is what deter-
mines how much output ripple voltage will be present.
Most polarized capacitors appear resistive at the typical
oscillator frequencies of the CS5127. As a rule of thumb,
physically larger capacitors have lower ESR. The capaci-
torÕs value in µF is not of great importance, and values
from a few tens of µF to several hundreds of µF will work
well. Tantalum capacitors serve very well as output capaci-
tors, despite their bad reputation for spectacular failure
due to excessive inrush current. This is not usually an issue
for output capacitors, because the failure is not associated
with discharge surges. Ripple current in the output capaci-
tor is usually small enough that the ripple current rating is
not an issue. The ripple current waveform is triangular,
and the formula to calculate the ripple current value is:

RIPPLE

and output ripple voltage due to inductor ripple current is
given by:

RIPPLE(ESR)

A load step will produce an instantaneous change in
output voltage defined by the magnitude of the load step,
capacitor ESR and ESL.

= (

´ ESD) +

ESL

A good practice is to first choose the output capacitor to
accommodate voltage transient requirements and then to
choose the inductor value to provide an adequate ripple
voltage.
Increasing a capacitorÕs value typically reduces its ESR, but
there is a limit to how much improvement can be had. In
most applications, placing several smaller capacitors in
parallel will result in acceptable ESR while maintaining a
small PC board footprint. A warning is necessary at this
point. The V

ª topology relies on the presence of some

amount of output ripple voltage being present to provide
the input signal for the ÒfastÓ control loop, and it is impor-
tant that some ripple voltage be present at the lightest load
condition in normal operation to avoid subharmonic oscil-
lation. Externally generated slope compensation can be
added to ensure proper operation.

The V

FFB

lead is tied to the PWM comparatorÕs non-invert-

ing input, and provides the connection for the
externally-generated artificial ramp signal that is required
whenever duty cycle is greater than 50%.

Selecting the V

FFB

Lead Components

- V

OUT

)

´ V

OUT

´ ESR

´ L ´ V

- V

OUT

´ L ´ V

Selecting the Output Capacitor

)

´ L(V

)

OUT

´ (V

IN(MAX)

- V

OUT

)

Operating in Discontinuous Current Mode

Other Inductor Selection Concerns

L(ÆI

OUT

)

OUT

L(ÆI

OUT

)

- V

OUT

)

´ 0.85

CS5127

Applications Information: continued

The DC voltage for the V

FFB

pin is usually provided from

the output voltage through an RC filter if V

OUT

is less than

3V. If V

OUT

is greater than 2.9V, a resistor divider from

OUT

is recommended for proper circuit bias due to the

common mode input range limitations of the PWM com-
parator. In most cases, the FB pin resistor divider can be
used for this purpose with very little error, but a separate
divider is recommended if high accuracy is required. The
filter network is typically composed of a 1K resistor (R

FFB

)

and a 330 pF capacitor (C

FFB

). This filter gives a 330 ns

time constant which is sufficient to remove switching
noise from the DC voltage. Note that in cases where a
resistor divider provides the ramp signal, the resistor
between V

OUT

and the V

FFB

pin serves as R

FFB

. An artificial

ramp signal is generated using an NPN transistor (Q1), a
small coupling capacitor (CC) and a second resistor (RR).
The NPN transistor collector is connected either to the
external 5V supply or to the ICÕs 5V on-chip reference. The
transistorÕs base is connected to the CT pin, and the ramp
on the CT pin is used to provide the artificial ramp. The
transistorÕs emitter is connected to the coupling capacitor.
The capacitor value should provide a low impedance at
the switching frequency. A 0.1 µF capacitor represents 6.4
ohms at 250 kHz. A resistor is placed in series between this
capacitor and the V

FFB

pin to set the amplitude of the ramp

signal.

Figure 4: Artificial ramp components CC, C

FFB

, RR and R

FFB

must be

provided for each channel if duty cycle for that channel exceeds 50%. Q1
and RE are common to both channels. DC voltage is shown supplied to
V

FFB

through the V

resistor divider.

The amount of artificial ramp is dependent on oscillator
frequency, output voltage, output capacitor equivalent
series resistance (ESR), and inductor value. It also assumes
very small voltage fluctuations on the COMP pin. If the
added ramp is too small, it will not be sufficient to prevent
subharmonic oscillation. If the ramp is too large, V

ª con-

trol will be defeated, and loop regulation will enter voltage
mode control. DC regulation will be adequate, but tran-
sient response will be degraded. However, this may be
desirable in cases where very low values of output ripple
voltage are desired.
The artificial ramp amplitude can be calculated as follows:

RAMP

if DC voltage is provided from the output, or

RAMP

if DC voltage is provided from a resistor divider as in
figure 5.

where R

ESR

is the equivalent series resistance in ohms of

the total output capacitance, V

OUT

is the output voltage in

volts and L

OUT

is the inductor value in Henries. The result

is V

RAMP

given in millivolts per oscillator period. This

value is the optimum amplitude for the artificial ramp.
Note that COMP pin voltage changes and output ripple
voltage must be added to the ramp amplitude for proper
operation.

Once the total ramp signal has been determined, the value
of the ramp resistor (RR) can be determined. The ramp
resistor and filter resistor R

FFB

create a resistor divider

between the output voltage and the artificial ramp voltage.
We can assume the output does not change, and that the
maximum input voltage to the divider is equal to the DC
output voltage plus the CT pin voltage swing of 2.1V. The
ramp amplitude on the filter capacitor is then the divider
output voltage:

RAMP

Rearranging, we have

RR = R

FFB

(

- 1

)

The schottky ÒcatchÓ diode must be capable of handling
the peak inductor current and must withstand a reverse
voltage at least equal to the value of V

. Since the catch

diode only conducts during switch off-time, the average
current through the catch diode is defined as:

CATCH

= I

OUT

Minimizing the diode on-voltage will improve efficiency.

The on-chip oscillator frequency is set by two external
components. R

sets the oscillator charge current. It is con-

nected to a voltage reference approximately equal to 2.5V.
The current generated in this fashion charges the C

capac-

itor between threshold levels of 1.5V and 3.6V. C

capacitor discharge is done by a saturating NPN, and the

Selecting Oscillator Components R

and C

)

- V

OUT

(

Selecting the Catch Diode

2.1V

RAMP

(2.1V) (R

FFB

)

(RR + R

FFB

)

ESR

) (V

OUT

)(R1)

2000 (L

OUT

) (R1 + R2)

ESR

) (V

OUT

)

2000 (L

OUT

)

OUT

FFB

GATE

discharge time is typically less than 10% of the charge
time. External components C

and R

allow the switching

frequency to be set by the user in the range between 10kHz
and 500kHz. C

can be chosen first based on size and cost

constraints. For proper operation over temperature, the
value of R

should be chosen within the range from 20k½

to 40k½. Any type of one-eighth watt resistor will be ade-
quate. Larger values of R

will decrease the maximum

duty cycle slightly. This occurs because the sink current on
the C

lead has an exponential relationship to the charge

current. Higher charge currents will discharge the C

lead

capacitor more quickly than lower currents, and a shorter
discharge time will result in a higher maximum duty
cycle.
Once the oscillator frequency and a value of C

have been

selected, the necessary value of R

can be calculated as fol-

lows:

where f

OSC

is the oscillator frequency in hertz, C

is given

in farads, and the value of R

is given in ohms. ESR effects

are negligible since the charge and discharge currents are
fairly small, and any type of capacitor is adequate for C

As previously noted, the error amplifier does not con-
tribute greatly to transient response, but it does influence
noise immunity. The fast feedback loop input is compared
against the COMP pin voltage. The DC bias to the V

FFB

may be provided directly from the output voltage, or
through a resistor divider if output voltage is greater than
2.9V. The desired percentage value of DC accuracy trans-
lates directly to the V

FFB

pin, and the minimum COMP pin

capacitor value can be calculated:

COMP

If f

OSC

= 200kHz, V

FFB

DC bias voltage is 2.8V and toler-

ance is 0.1%, C

COMP

= 28.6µF. This is the minimum value

of COMP pin capacitance that should be used. It is a good
practice to guard band the tolerance used in the calcula-
tion. Larger values of capacitance will improve noise
immunity, and a 100µF capacitor will work well in most
applications.
The type of capacitor is not critical, since the amplifier
output sink current of 16mA into a fairly large value or
wide range of ESR will typically result in a very small DC
output voltage error. The COMP pin capacitor also deter-
mines the length of the soft start interval.

The input bypass capacitors minimize the ripple current in
the input supply, help to minimize EMI, and provide a
charge reservoir to improve transient response. The capac-
itor ripple current rating places the biggest constraint on
component selection. The input bypass capacitor network

should conduct all the ripple current. RMS ripple current
can be as large as half the load current, and can be calcu-
lated as:

RIPPLE(RMS)

= I

OUT

Peak current requirement, load transients, ambient operat-
ing temperature and product reliability requirements all
play a role in choosing this component. Capacitor ESR and
the maximum load current step will determine the maxi-
mum transient variation of the supply voltage during
normal operation. The drop in the supply voltage due to
load transient response is given as:

ÆV = I

RIPPLE(RMS)

´ ESR

The type of capacitor is also an important consideration.
Aluminum electrolytic capacitors are inexpensive, but they
typically have low ripple current ratings. Choosing larger
values of capacitance will increase the ripple current
rating, but physical size will increase as well. Size con-
straints may eliminate aluminum electrolytics fro
consideration. Aluminum electrolytics typically have
shorter operating life because the electrolyte evaporates
during operation. Tantalum electrolytic capacitors have
been associated with failure from inrush current, and man-
ufacturers of these components recommended derating the
capacitor voltage by a ratio 2:1 in surge applications. Some
manufacturers have product lines specifically tested to
withstand high inrush current. AVX TPS capacitors are
one such product. Ceramic capacitors perform well, but
they are also large and fairly expensive.

At startup, output switching does not occur until two
undervoltage lockouts release. The first lockout monitors
the V

lead voltage. No internal IC activity occurs until

lead voltage exceeds the V

turn-on threshold. This

threshold is typically 8.4V. Once this condition is met, the
on-chip reference turns on. As the reference voltage begins
to rise, a second undervoltage lockout disables switching
until V

REF

lead voltage is about 3.5V. The GATE leads are

held in a low state until both lockouts are released.
As switching begins, the V

lead voltage is lower than the

output voltage. This causes the error amplifier to source
current to the COMP lead capacitor. The COMP lead volt-
age will begin to rise. As the COMP lead voltage begins to
rise, it sets the threshold level at which the rising V

FFB

lead

voltage will trip the PWM comparator and terminate
switch conduction. This process results in a soft start inter-
val. The DC bias voltage on V

FFB

will determine the final

COMP voltage after startup, and the soft start time can be
approximately calculated as:

SOFT START

FFB

´ C

COMP

COMP(SOURCE)

Startup

OUT

- V

OUT

)

Selecting the Input Bypass Capacitor

(16mA)(T

OSC

)

FFB

DC Bias Voltage)(tolerance)

Selecting the Compensation Capacitor

1.88

OSC

)(C

)

CS5127

Applications Information: continued

Applications Information: continued

where T

SOFT START

is given in seconds if C

COMP

is given in

farads, I

COMP(SOURCE)

in amperes, and V

FFB

in volts. Note

that a design trade off will be made in choosing the value
of the COMP lead capacitor. Larger values of capacitance
will result in better regulation and improved noise immu-
nity, but the soft start interval will be longer and capacitor
price may increase.

Figure 5: Measured performance of the CS5127 at start up.
C

COMP

=100µF, I

COMP(SOURCE)

=1.3mA, V

FFB

= 2.8V, T

SOFTSTART

= 0.22s.

During normal operation, the gate driver switching duty
cycle will remain approximately constant as the V

ª con-

trol loop maintains the regulated output voltage under
steady state conditions. Changes in supply line or output
load conditions will result in changes in duty cycle to
maintain regulation.

Voltage Mode Operation
There are two methods by which a user can operate the
CS5127 in voltage mode. The first method is simple, but
the transient response is typically very poor. This method
uses the same components as V

ª operation, but by

increasing the amplitude of the artificial ramp signal, V

control is defeated and the controller operates in voltage
mode. Calculate RR using the formula above and divide
the value obtained by 10. This should provide an ade-
quately large artificial ramp signal and cause operation
under voltage mode control. There may be some depen-
dence on board layout, and further optimization of the
value for RR may be done empirically if required.

Voltage mode control may be refined by removing the
COMP pin capacitor and adding a two pole, one zero com-
pensation network. Consider the system block diagram
shown in figure 6.

Figure 6: Voltage mode control equivalent circuit with two pole, one
zero compensation network.

is the switch supply voltage, R represents the load, RL

is the combined resistance of the FET RDS (on) and the
inductor DC resistance, L is the inductor value, C is the
output capacitance, RC is the output capacitor ESR, RA
and RB are the feedback resistors and VR is the peak to
peak amplitude of the artificial ramp signal at the V

FFB

pin. C1, C2, R1 and R2 are the components of the compen-
sation network. Based on the application circuit from page
1, values for the 2.8V output equivalent circuit are:

= 5V

R =

0.4½

RL = 0.02½
C =

1320µF

RC = 0.025½
RA = 1540½
RB = 1270½
L =

5µH

A resistor change is necessary to increase the artificial
ramp magnitude to V

FFB1

. Changing R10 from 20k to 2k

will give a peak to peak amplitude of about 2V. Thus, V

2V.

The transfer function from V

CONTROL

to V

OUT

Using the component values provided, this reduces to

´ V

´ (sCR

+ 1)

LC (R + R

) + s[L + R

C(R + R

) + RCR

] + R + R

OUT

CONTROL

PWM

1.275V

CONTROL

OUT

FFB

COMP

CONTROL

LOGIC

Voltage Mode Control

Normal Operation

CS5127

CS5127

Applications Information: continued

The zero frequency due to the output capacitor ESR is
given as

= 4.8 kHz.

The double pole frequency of the power output stage is

= 1.95 kHz.

The ESR zero approximately cancels one of the poles, and
the total phase shift is limited to 90. Bode plots are provid-
ed below.

Figure 7: Bode plot of gain response for V

OUT

CONTROL

Figure 8: Bode plot of phase response for V

OUT

CONTROL

This uncompensated system is stable, but the low gain will
result in poor DC accuracy, and the low cutoff frequency
will result in poor transient response. Note that we have
not yet included the gain factor from the feedback resistor

divider. This factor will further reduce the overall system
gain.

By adding the two pole, one zero compensation network
shown in figure 6, we can maximize the DC gain and push
out the crossover frequency. The transfer function for the
compensation network is

This can be rewritten in terms of pole and zero frequencies
and a gain constant A.

where

and A = R1 C2

Note that, due to the first s term in the denominator, a pole
is located at f = 0. This will provide the maximum DC
gain.
The optimum performance can be obtained by choosing f

equal to the output double pole frequency and setting f

approximately half of the switching frequency. Gain fac-
tors can be chosen somewhat arbitrarily.

Values between
1E-6½F and 20E-6½F are practical. We then have a set of
equations that can be solved for component values:

C1 R1 =

[

]

C1 R2 =

C2 =

Since there are only three equations, we must arbitrarily
choose one of the components. One option is to set the
value of R1 fairly large. This provides a high impedance
path between the V

pin and the COMP pin.

For our design, we have f

= the double pole frequency =

1.95 kHz and f

= f

OSC

/2 = 100kHz. LetÕs arbitrarily choose

R1 = 4.7K. Then we solve the first equation for C1 and
obtain C1 = 17nF. Use a standard value of 22 nF.

We next solve for R2. With C1 =22 nF, R2= 72½. Use a
standard value of 75½.
We can choose a gain factor from somewhere in the
middle of our range and solve for C2. If A = 10E-6½F, we
have
C2 = 2.1 nF. Use a standard value of 2.2 nF.

2¹f

2¹

2¹ C1R2

(2¹ C1 (R1 + R2))

s/(2¹f

+ 1)

-A s ((s/2f

) + 1)

CONTROL

s C1(R1 + R2) + 1

-s C2 R1(s C1 R2 + 1)

CONTROL

-270.0

Frequency (Hz)

Phase, (degree)

-90

-180

-60.0

Frequency (Hz)

Gain, (dB)

-20

-40

R + R

LC(R + R

)

(2¹)

(2¹CR

)

1 + s(3.3E-5)

(2.772E-9) + s(2.902E-5) + 0.42

Applications Information: continued

Now that we have the compensation components chosen,
we can put together a transfer function for the entire con-
trol loop. The transfer function is the product of the VOUT
to V

CONTROL

transfer function, the gain of the feedback

resistor divider and the negative inverse of the compensa-
tion loop transfer function. That is,

LOOP

= - (T

VC-VO

´ T

DIVIDER

´ T

COMPENSATION

)

LOOP

[

]

[ ]

[

]

[

]

Bode plots for this transfer function are shown below.

Figure 9: Bode plot of gain response for compensated voltage mode
system.

Figure 10: Bode plot of phase response for compensated voltage mode
system.

Entering the loop transfer function in a mathematics pro-
gram or a spreadsheet and evaluating the performance
from resulting Bode plots may help to further optimize the
compensation network component values.
Compensation may be further optimized by using a two
poleÐtwo zero compensation network as shown below.

Figure 11: Two poleÐtwo zero compensation network.

The two zeros are placed close to the resonant frequency of
the LC output circuit. That is,

The two poles are placed near half the switching frequen-
cy, or

The ENABLE lead controls operation of channel 2. Channel
2 operates normally if the ENABLE lead voltage is greater
than 3.5V. Setting the ENABLE lead voltage below 1.5V
will guarantee that channel 2 is disabled. In this case, the
GATE2 lead will be held low and no switching will occur.
This feature can be used to selectively power up or power
down circuitry that may not always need to be on. For
example, in a laptop computer, channel 1 could power the
microprocessor while channel 2 controlled the disk drive.
Channel 2 could be turned off if the drive was not in use.

Semiconductor components will deteriorate in high tem-
perature environments. It is necessary to limit the junction
temperature of control ICs, power MOSFETs and diodes in
order to maintain high levels of reliability. Most semicon-
ductor devices have a maximum junction temperature of
125¡C, and manufacturers recommend operating their
products at lower temperatures if at all possible.
Power dissipation in a semiconductor device results in the
generation of heat in the pin junctions at the surface of the

Thermal Management for Semiconductor Components

Channel 2 ENABLE Feature

2¹ R3 C2

2¹ C1 R1

2¹ R3 C3

2¹ C1 R2

2¹ LC

From V

OUT

COMP

-270.0

Frequency (Hz)

Phase, (degree)

-90

-180

-60.0

Frequency (Hz)

Gain, (dB)

-20

100

-100.0

sC1 (R1 + R2)+ 1

sC2 R1 (sC1 R2 + 1)

RA + RB

´ V

´ (sCR

+ 1)

LC (R + R

) + s[L + R

C(R + R

) + RCR

] + R + R

CS5127

Applications Information: continued

IC. This heat is transferred to the surface of the IC package,
but a thermal gradient exists due to the thermal properties
of the package molding compound. The magnitude of this
thermal gradient is denoted in manufacturerÕs data sheets
as

, or junction-to-air thermal resistance. The on-chip

junction temperature can be calculated if

, the air tem-

perature at the ICÕs surface and the on-chip power
dissipation are known:

= T

+ (

´ P)

and T

are given in degrees centigrade, P is IC power

dissipation in watts and

is thermal resistance in

degrees centigrade per watt. Junction temperature should
be calculated for all semiconductor devices to ensure they
are operated below the manufacturerÕs maximum junction
temperature specification. If any componentÕs temperature
exceeds the manufacturerÕs maximum specification, some
form of heatsink will be required.
Heatsinking will improve the thermal performance of any
IC. Adding a heatsink will reduce the magnitude of

providing a larger surface area for heat transfer to the sur-
rounding air. Typical heat sinking techniques include the
use of commercial heatsinks for devices in TO-220 pack-
ages, or printed circuit board techniques such as thermal
bias and large copper foil areas for surface mount pack-
ages.

When choosing a heatsink, it is important to break

into several different components.

where all components of

are given in ¡C/W.

is the thermal impedance from the junction to the sur-

face of the package case. This parameter is also included in
manufacturerÕs data sheets. Its value is dependent on the
mold compound and lead frames used in assembly of the
semiconductor device in question.
Q

is the thermal impedance from the surface of the case

to the heatsink. This component of the thermal impedance
can be modified by using thermal pads or thermal grease
between the case and the heat sink. These materials replace
the air gap normally found between heatsink and case with
a higher thermal conductivity path. Values of

are

found in catalogs published by manufacturers of heatsinks
and thermal compounds.
Finally,

is the thermal impedance from the heatsink to

ambient temperature.

is the important parameter

when choosing a heatsink. Smaller values of

allow

higher power dissipation without exceeding the maximum
junction temperature of the semiconductor device. Values
of

are typically provided in catalogs published by

heatsink manufacturers.
The basic equation for selecting a heatsink is

where P

is on-chip power dissipation in watts, T

is junc-

tion temperature in ¡C, T

is ambient temperature in¡C,

and thermal impedance

, and

are in¡C/W.

All these quantities can be calculated or obtained from data
sheets. The choice of a heatsink is based on the value of

required such that the calculated power dissipation

does not cause junction temperature to exceed the manu-
facturerÕs maximum specification.

Switching regulators generate noise a consequence of the
large values of current being switched on and off in normal
operation. Careful attention to layout of the printed circuit
board will usually minimize noise problems. Layout guide-
lines are provided in the next section. However, it may be
necessary in some cases to add filter inductors or bypass
capacitors to the circuitry to achieve the desired perfor-
mance.

The following guidelines should be observed in the layout
of PC boards for the CS5127:

1. Connect the PGND lead to the external ground with a

wide metal trace.

2. Connect both LGND and PGND together with a wide

trace as close to the IC as possible.

3. Make all ground connections to a common ground

plane with as few interruptions as possible. Breaks in
the ground plane metal should be made parallel to an
imaginary line between the supply connections and the
load.

4. Connect the ground side of the COMP lead capacitors

back to LGND with separate traces.

5. Place the V

FFB

lead capacitors as close to the V

FFB

leads

as possible.

6. Place the 5V line bypass capacitors as close to the

switch FETs as possible.

7. Place the output capacitor network as close to the load

as possible.

8. Route the GATE lead signals to the FET gates with a

metal trace at least 0.025 inches wide.

9. Use wide straight metal traces to connect between the

5V line and FETs, between FETs and inductors and
between inductors and loads to minimize resistance in
the high current paths. Avoid sharp turns, loops and
long lengths.

Layout Considerations

EMI Management

- T

CS5127

ENABLE 1

SIGNAL

6.3K

Q4
FMMT2222ACT

FMMT2907ACT

TO V

FFB1

TO COMP1

OUT

OVP OUT

24K

R4
10K

10K

FMMT2222ACT

FMMT2907ACT

OUT

PGOOD OUT

10K

FMMT2222ACT

18K

FMMT2222ACT

Figure 12: Example external over voltage protection circuit. If V

OUT

exceeds V

OVP

, OVP out goes high. Resistor values shown above pro-

vide a +10% tolerance for a 3.3V output.

Figure 13: Example external Power GOOD circuit. P

GOOD(OUT)

is low

until V

OUT

exceeds V

PGOOD

. V

PGOOD

is typically chosen to be 10%

below nominal V

OUT

. Resistor values above provide a -10% tolerance

on V

OUT

=3.3V.

Figure 14: An external circuit can be built to provide an enable func-
tion for channel 1. The circuit shown above connects to the V

FB1

and

COMP1 pins as indicated. If the ENABLE1 signal is left floating or is
pulled high, channel 1 is enabled. If the ENABLE1 pin is pulled
below 1V, Q1 will conduct, and mirror Q3 pulls V

FFB1

up at the same

time as Q2 and Q4 pull COMP1 low. This will force GATE1 to go low
and turn off the switch FET. The circuit above will provide about
1mA of additional drive to the V

FFB1

pin components. This additional

current must be sufficient to pull V

FFB1

up to about 1V in order to

guarantee GATE1 is held low.

Additional Application Circuits

OVP

(R1 + R2)(0.65V)

PGOOD

(R1 + R2)(0.65V)

CS5127

+5V

+12V

+5V

2.8V

3.3V

1540

C8
1

Q2
IRL3103S

C5
680

2400

CS5127

SYNC

FB1

COMP1

FFB1

GATE1

LGND

REF

ENABLE

FB2

COMP2

FFB2

GATE2

PGND

1N5821

IRL3103S

680

R8
1500

C11
680

C10
680

C3
1UF

R5
1270

C1
680

C2
680

1N5821

C13

680

C12
680UF

R7
10

R6
2K

C14
0.2

R65
18K

C15

0.01

R1
3.3K

R2
100K

390pF

R3
24K

7pF

C50

0.22

2N3906

R48
100K

C15
0.1

C24
0.01

Q7
2N3906

C16

0.22

R11

2.2K

R66

C17

0.2

R10

C52
7pF

+12V

2.8V

3.3V

R4
1540

330PF

C16

100

C17

330PF

R7
2400

CS5127

SYNC

FB1

COMP1

FFB1

GATE1

LGND

REF

ENABLE

FB2

COMP2

FFB2

GATE2

PGND

1N5821

IRL3103S

FMMT2222ACT

C2
680

C13

680

0.1

R9
2K

18K

C15
100

C14
330PF

C10
680

1270

R10
20K

L1 5

R6
1K

27k

IRL3103S

1N5821

R8
1500

C1
680

680

C5
680

C8
1

20K

C12
680

C11
680

R11
20K

0.1

1N5818

C18

0.1

50V

R12

D5
1N5248

Figure 15: CS5127 12V, 5V input to 2.8V @ 7A and 3.3V @ 7A Voltage Mode Control Application Circuit with External Soft Start.

Figure 16: CS5127 12V only to 2.8V @ 7A and 3.3V @ 7A Application Circuit.

Additional Application Circuits continued

CS5127

CS5127

Additional Application Circuits continued

+5V

3.3V

680

IRL3103S

680

C17

330PF

C12

CS5127

SYNC

FB1

COMP1

FFB1

GATE1

LGND

REF

ENABLE

FB2

COMP2

FFB2

GATE2

PGND

IRL3103S

FMMT2222ACT

R11

20K

R66

R71

10K

0.1

1.50K

R68
15k

C13

680

C14
330PF

C10

680

20K

1N5821

1.54K

R10

20K

R6
1K

330PF

1N5821

C16

100

1.27K

+12V

+5V

680

2.40K

18K

C15

100

RDROOP

2.8V

R75

R76

C25

0.1

R69
10K

2N2907

LM2903
U4A

LM2903
U4B

R72
20K

R74

R73
1K

R70
20K

C11

680

.008

R65

R67
15k

680

R77
15K

R78
15K

RDROOP

.008

C24
0.1

Figure 17: 200kHz, V

ª, 5V/12V input, 2.8V@ 7A and 3.3V @ 7A outputs with current limit.

2.8V

3.3V

R4
1540

330PF

C16

100

C17

330pF

R7
2400

CS5127

SYNC

FB1

COMP1

FFB1

GATE1

LGND

REF

ENABLE

FB2

COMP2

FFB2

GATE2

PGND

1N5821

IRL3103S

FMMT2222ACT

C2
680

C13

680

0.1

R9
2K

18K

C15
100

C14
330pF

C10
680

1270

R10
20K

L1 10

R6
1K

27K

IRL3103S

1N5821

R8
1500

C1
680

20K

C12
680

C11
680

R11
20K

0.1

+5V

+12V

2.5V

680

C5
680

+5V

C18

IRL3103S

R18
2400

R17
2400

C8
1

U2A
1/2 LM358

Figure 18: CS5127 12V, 5V input to 2.8V @7A and 3.3V @ 7A Switching Regulator with External 1A, 2.5V Linear Output for Vclock.

1.00E+06

5.00E+05

1.00E+05

5.00E+04

2.00E+04

1.00E+04

RT (k

Frequency (kHz)

2.00E+05

150pF

390pF

680pF

1.5nF

3.3nF

Figure 24: Oscillator Frequency vs R

= 12V, T = 25C)

130

120

110

100

Short Circuit Current (mA)

Temperature(C)

Figure 23: V

REF

Short Circuit Current vs Temperature.

Typical Performance Characteristics

5.005

5.004

5.003

5.002

5.001

5.000

4.999

Temperature (C)

REF

(V)

4.992

4.990

4.998

4.988

4.986

4.980

4.978

Temperature (C)

VREF (V)

Figure 19: V

REF

vs Temperature, 1mA Load.

Figure 21: V

REF

vs Temperature, 10mA Load.

Temperature (C)

Load Regulation (mV)

Temperature (C)

Line Regulation (mV)

Figure 20: Load Regulation vs Temperature 1mA to 10mA.

Figure 22: Line Regulation vs Temperature 9V to 20V.

CS5127

RT (k

Duty Cycle (%)

150pF

390pF

680pF

1.5nF

3.3nF

Figure 27: Oscillator Duty Cycle vs C

, R

= 12V, T = 25C).

91.5

91.0

89.5

89.0

88.5

Temperature (C)

Maximum Duty Cycle (%)

90.5

90.0

1.65

1.55

1.40

1.30

1.25

Temperature (C)

Sync Threshhold

(V)

1.60

1.50

1.45

1.35

1.20

Figure 25: Oscillator Maximum Duty Cycle vs Temperature.

Figure 28: SYNC Threshold vs Temperature.

Typical Performance Characteristics: continued

210

208

206

204

202

200

Temperature (C)

Oscillator Frequency (kHz)

Figure 26: Oscillator Frequency vs Temperature. C

= 330pF, R

=27k

CS5127

1.2785

1.2775

1.2765

1.2760

Temperature (C)

Reference V

oltage (V)

1.2780

1.2770

1.2755

Figure 30: V

Reference Voltage vs Temperature.

170

160

145

140

Temperature (C)

Sync Input Curernt (

165

155

150

Figure 29: SYNC Input Current vs Temperature (V

SYNC

= 2.4V).

0.85

0.75

Temperature (C)

Output Low V

oltage (V)

0.90

0.80

0.70

Figure 36: Error Amplifier Output Low Voltage (500µA) vs
Temperature.

1.305

1.295

1.285

1.280

Temperature (C)

Source Current (mA)

1.310

1.300

1.290

Figure 35: Error Amplifier Source Current vs Temperature.

0.105

0.101

0.097

Temperature (C)

Bias Current (

0.103

0.099

0.095

Figure 33: V

Bias Current vs Temperature.

-10

1.00E +00

Frequency (Hz)

Gain (dB)

-20

-30

1.00E +01 1.00E +02

1.00E +03 1.00E +04 1.00E +05

1.00E +06

1.00E +07

180

-45

1.00E+00

Frequency (Hz)

Phase (degrees)

225

135

1.00E+01 1.00E+02

1.00E+03

1.00E+04

1.00E+05 1.00E+06

1.00E+07

Figure 31: Error Amplifier Gain vs Frequency.

Figure 34: Error Amplifier Phase vs Frequency.

450

410

370

350

Temperature (C)

Input Curernt (

430

390

Figure 32: SYNC Input Current vs Temperature (V

SYNC

= 5V).

Typical Performance Characteristics: continued

CS5127

1.07

1.05

1.02

1.01

Temperature (C)

FFB

Bias (

1.06

1.04

1.03

1.00

0.99

Figure 39: V

FFB

Bias Current vs Temperature.

3.35

3.29

Temperature (C)

Maximum Common Mode V

oltage (V)

3.37

3.31

3.27

3.33

2.26

2.22

Temperature (C)

ENABLE Threshold

(V)

2.28

2.20

2.24

Figure 37: PWM Comparator Maximum Common Mode Input Voltage
vs Temperature.

Figure 40: ENABLE Threshold vs Temperature.

Typical Performance Characteristics: continued

17.0

16.0

15.0

14.5

Temperature (C)

Sink Current (mA)

17.5

16.5

15.5

Figure 38: Error Amplifier Sink Current vs Temperature.

CS5127

270

240

220

210

Temperature (C)

ENABLE Bias Current (

280

260

250

230

Figure 41: ENABLE Bias Current vs Temperature.

210

195

185

180

Temperature (C)

TE Low V

oltage (mV)

215

205

200

190

Figure 42: GATE Low Voltage (100mA) vs Temperature.

400

320

Temperature (C)

Start up Current (

340

360

300

380

Figure 48: Start-up Current vs Temperature.

8.615

8.607

Temperature (C)

Start up

Threshold (V)

8.609

8.611

8.613

8.605

Figure 47: V

Start-up Threshold vs Temperature.

Temperature (C)

TE Low V

oltage (mV)

Figure 44: GATE low voltage (20mA) vs Temperature.

1.55

1.40

1.30

1.25

Temperature (C)

TE High V

oltage (V)

1.60

1.50

1.45

1.35

1.20

Figure 45: GATE High Voltage (20mA) vs Temperature.

1.65

1.50

Temperature (C)

TE High V

oltage (mV)

1.40

1.55

1.60

1.70

1.45

17.0

15.5

Temperature (C)

Lockout V

oltage (mV)

18.0

15.0

16.0

16.5

17.5

Figure 43: GATE High Voltage (100mA) vs Temperature.

Figure 46: GATE Low Voltage (Lockout) vs Temperature.

Typical Performance Characteristics: continued

CS5127

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CS5127

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CS5127