The CS5151 is a 4-bit nonsyn-
chronous N-Channel buck con-
troller. It is designed to provide
unprecedented transient response
for today's demanding high-densi-
ty, high-speed logic. The regulator
operates using a proprietary control
method, which allows a 100ns
response time to load transients.
The CS5151 is designed to operate
over a 4.25-16V range (V
CC
) using
12V to power the IC and 5V as the
main supply for conversion.
The CS5151 is specifically designed
to power Pentium
processors with
MMXTM Technology and other high
performance core logic. It includes
the following features: on board,
4-bit DAC, short circuit protection,
1.0% output tolerance, V
CC
monitor,
and programmable soft start capa-
bility. The CS5151 is upwards com-
patible with the 5-bit CS5156, allow-
ing the mother board designer the
capability of using either the
CS5151 or the CS5156 with no
change in layout. The CS5151 is
available in 16 pin surface mount
and DIP packages.
Features
s
N-Channel Design
s
Excess of 1MHz Operation
s
100ns Transient Response
s
4-Bit DAC
s
Upward Compatible with
5-Bit CS5155/5156 and
Adjustable CS5120/5121
s
30ns Gate Rise/Fall Times
s
1% DAC Accuracy
s
5V & 12V Operation
s
Remote Sense
s
Programmable Soft Start
s
Lossless Short Circuit
Protection
s
V
CC
Monitor
s
Adaptive Voltage
Positioning
s
V
2
TM Control Topology
s
Current Sharing
s
Overvoltage Protection
Package Options
CPU 4-Bit Nonsynchronous Buck Controller
CS5151
Description
Application Diagram
1
V
ID0
V
ID1
V
ID2
V
ID3
SS
NC
C
OFF
V
FFB
V
FB
COMP
LGnd
V
CC1
NC
PGnd
V
GATE
V
CC2
16 Lead SO Narrow & PDIP
1
Switching Power Supply for core logic - Pentium
processor with MMXTM Technology
0.33F
V
ID0
V
ID1
V
ID2
V
ID3
V
ID0
V
ID1
V
ID2
V
ID3
V
CC1
SS
C
OFF
LGnd
V
FB
V
FFB
COMP
IRL3103
0.1F
12V
5V
2H
2.1V to 3.5V @ 13A
V
CC2
V
GATE
PGnd
1200F/16V x 3
AlEl
3.3k
0.1F
1200F/16V x 5
AlEl
100pF
330pF
CS5151
MBR735
3
1,2
V
2
is a trademark of Switch Power, Inc.
Pentium is a registered trademark and MMX is a trademark of Intel Corporation.
CS5151
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
A Company
Rev. 1/5/99
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Electrical Characteristics:
0C < T
A
< +70C; 0C < T
J
< +85C; 8V < V
CC1
< 14V; 5V < V
CC2
< 14V; DAC Code: V
ID2
= V
ID1
=
V
ID0
= 1; V
ID3
= 0; CV
GATE
= 1nF; C
OFF
= 330pF; C
SS
= 0.1F, unless otherwise specified.
2
Pin Name
Max Operating Voltage
Max Current
V
CC1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA DC/1.5A peak
V
CC2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA DC/1.5A peak
SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-100A
COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200A
V
FB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2A
C
OFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2A
V
FFB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2A
V
ID0
- V
ID3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-50A
V
GATE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA DC/1.5A peak
LGnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA
PGnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA DC/1.5A peak
Operating Junction Temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to 150C
Lead Temperature Soldering
Wave Solder (through hole styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 sec. max, 260C peak
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max above 183C, 230C peak
Storage Temperature Range, T
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to 150C
ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
CS5151
Absolute Maximum Ratings
s
Error Amplifier
V
FB
Bias Current
V
FB
= 0V
0.3
1.0
A
Open Loop Gain
1.25V < V
COMP
< 4V; Note 1
50
60
dB
Unity Gain Bandwidth
Note 1
500
3000
kH
COMP SINK Current
V
COMP
= 1.5V; V
FB
= 3V; V
SS
> 2V
0.4
2.5
8.0
mA
COMP SOURCE Current
V
COMP
= 1.2V; V
FB
= 2.7V; V
SS
= 5V
30
50
70
A
COMP CLAMP Current
V
COMP
= 0V; V
FB
= 2.7V
0.4
1.0
1.6
mA
COMP High Voltage
V
FB
= 2.7V; V
SS
= 5V
4.0
4.3
5.0
V
COMP Low Voltage
V
FB
=3V 160
600
mV
PSRR
8V < V
CC1
< 14V @ 1kHz; Note 1
60
85
dB
s
V
CC1
Monitor
Start Threshold
Output switching
3.75
3.90
4.05
V
Stop Threshold
Output not switching
3.70
3.85
4.00
V
Hysteresis
Start-Stop
50
mV
s
DAC
Input Threshold
V
ID0
, V
ID1
, V
ID2
, V
ID3
1.00
1.25
2.40
V
Input Pull Up Resistance
V
ID0
, V
ID1
, V
ID2
, V
ID3
25
50
100
k
Pull Up Voltage
4.85
5.00
5.15
V
Accuracy
Measure V
FB
= V
COMP
, 25C T
J
85C
1.0
%
V
ID3
V
ID2
V
ID1
V
ID0
1
1
1
1
1.2315
1.2440
1.2564
V
1
1
1
0
2.1186
2.1400
2.1614
V
1
1
0
1
2.2176
2.2400
2.2624
V
1
1
0
0
2.3166
2.3400
2.3634
V
1
0
1
1
2.4156
2.4400
2.4644
V
1
0
1
0
2.5146
2.5400
2.5654
V
1
0
0
1
2.6136
2.6400
2.6664
V
1
0
0
0
2.7126
2.7400
2.7674
V
0
1
1
1
2.8116
2.8400
2.8684
V
0
1
1
0
2.9106
2.9400
2.9694
V
0
1
0
1
3.0096
3.0400
3.0704
V
CS5151
3
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Electrical Characteristics:
0C < T
A
< +70C; 0C < T
J
< +85C; 8V < V
CC1
< 14V; 5V < V
CC2
< 14V; DAC Code: V
ID2
= V
ID1
=
V
ID0
= 1; V
ID3
= 0; CV
GATE
= 1nF; C
OFF
= 330pF; C
SS
= 0.1F, unless otherwise specified.
s
DAC: continued
V
ID3
V
ID2
V
ID1
V
ID0
0
1
0
0
3.1086
3.1400
3.1714
V
0
0
1
1
3.2076
3.2400
3.2724
V
0
0
1
0
3.3066
3.3400
3.3734
V
0
0
0
1
3.4056
3.4400
3.4744
V
0
0
0
0
3.5046
3.5400
3.5754
V
s
V
GATE
Out SOURCE Sat at 100mA
Measure V
CC2
V
GATE
1.2
2.0
V
Out SINK Sat at 100mA
Measure V
GATE
VPGnd;
1.0
1.5
V
Out Rise Time
1V < V
GATE
< 9V; V
CC1
= V
CC2
= 12V
30
50
ns
Out Fall Time
9V > V
GATE
> 1V; V
CC1
= V
CC2
= 12V
30
50
ns
Shoot-Through Current
Note 1
50
mA
V
GATE
Resistance
Resistor to LGnd
20
50
100
k
V
GATE
Schottky
LGnd to V
GATE
@ 10mA
600
800
mV
s
Soft Start (SS)
Charge Time
1.6
3.3
5.0
ms
Pulse Period
25
100
200
ms
Duty Cycle
(Charge Time/Pulse Period) 100
1.0
3.3
6.0
%
COMP Clamp Voltage
V
FB
= 0V; V
SS
= 0
0.50
0.95
1.10
V
V
FFB
SS Fault Disable
V
GATE
= Low
0.9
1.0
1.1
V
High Threshold
2.5
3.0
V
s
PWM Comparator
Transient Response
V
FFB
= 0 to 5V to V
GATE
= 9V to 1V;
100
125
ns
V
CC1
= V
CC2
= 12V
V
FFB
Bias Current
V
FFB
= 0V
0.3
A
s
Supply Current
I
CC1
No Switching
8.5
13.5
mA
I
CC2
No Switching
1.6
3.0
mA
Operating I
CC1
V
FB
= COMP = V
FFB
8
13
mA
Operating I
CC2
V
FB
= COMP = V
FFB
2
5
mA
s
C
OFF
Normal Charge Time
V
FFB
= 1.5V; V
SS
= 5V
1.0
1.6
2.2
s
Extension Charge Time
V
SS
= V
FFB
= 0
5.0
8.0
11.0
s
Discharge Current
C
OFF
to 5V; V
FB
>1V
5.0
mA
s
Time Out Timer
Time Out Time
V
FB
= V
COMP
; V
FFB
= 2V;
10
30
50
s
Record V
GATE
Pulse High Duration
Fault Mode Duty Cycle
V
FFB
= 0V
35
50
65
%
Note 1: Guaranteed by design, not 100% tested in production.
4
CS5151
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
16L SO Narrow & PDIP
1,2,3,4
V
ID0
V
ID3
Voltage ID DAC input pins. These pins are internally pulled up to 5V
providing logic ones if left open. The DAC range is 2.14V to 3.54V with
100mV increments. V
ID0
- V
ID3
select the desired DAC output voltage.
Leaving all 4 DAC input pins open results in a DAC output voltage of
1.244V, allowing for adjustable output voltage, using a traditional resis-
tor divider.
5
SS
Soft Start Pin. A capacitor from this pin to LGnd in conjunction with
internal 60A current source provides soft start function for the con-
troller. This pin disables fault detect function during Soft Start. When a
fault is detected, the soft start capacitor is slowly discharged by internal
2A current source setting the time out before trying to restart the IC.
Charge/discharge current ratio of 30 sets the duty cycle for the IC when
the regulator output is shorted.
6, 12
NC
No connection.
7
C
OFF
A capacitor from this pin to ground sets the time duration for the on
board one shot, which is used for the constant off time architecture.
8
V
FFB
Fast feedback connection to the PWM comparator. This pin is connected
to the regulator output. The inner feedback loop terminates on time.
9
V
CC2
Boosted power for the gate driver.
10
V
GATE
MOSFET driver pin capable of 1.5A peak switching current.
11
PGnd
High current ground for the IC. The MOSFET driver is referenced to this
pin. Input capacitor ground and the anode of the Schottky diode should
be tied to this pin.
13
V
CC1
Input power for the IC.
14
LGnd
Signal ground for the IC. All control circuits are referenced to this pin.
15
COMP
Error amplifier compensation pin. A capacitor to ground should be pro-
vided externally to compensate the amplifier.
16
V
FB
Error amplifier DC feedback input. This is the master voltage feedback
which sets the output voltage. This pin can be connected directly to the
output or a remote sense trace.
5
CS5151
Block Diagram
Q
V
ID1
V
CC1
SS
COMP
V
FB
V
ID0
LGnd
V
FFB
V
CC2
V
GATE
PGnd
V
ID2
V
ID3
-
+
4 BIT
DAC
C
OFF
Slow Feedback
Maximum
On-Time
Timeout
R
Q
S
COFF
One Shot
PWM
COMP
SS High
Comparator
FAULT
Latch
2.5V
Error
Amplifier
Fast Feedback
-
+
V
CC1
Monitor
Comparator
-
+
-
+
-
+
-
+
VFFB Low
Comparator
PWM
Comparator
SS Low
Comparator
R
Q
S
Q
R
Q
S
2A
5V
60A
Normal
Off-Time
Timeout
Extended
Off-Time
Timeout
Time Out
Timer
(30s)
Edge Triggered
Off-Time
Timeout
3.90V
3.85V
FAULT
FAULT
GATE = ON
GATE = OFF
PWM
Latch
1V
0.7V
Applications Information
V
2
TM Control Method
The V
2
TM method of control uses a ramp signal that is gen-
erated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is gen-
erated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
Figure 1: V
2
TM Control Diagram
The V
2
TM control method is illustrated in Figure 1. The out-
put voltage is used to generate both the error signal and the
ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regard-
less of the origin of that change. The ramp signal also con-
tains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V
2
TM
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V
2
TM control scheme has the
same advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this `slow' feedback loop is to provide
DC accuracy. Noise immunity is significantly improved,
since the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote sens-
Reference
Voltage
+
C
E
+
Ramp
Signal
Output
Voltage
Feedback
Error
Signal
V
GATE
Error
Amplifier
V
FFB
COMP
V
FB
PWM
Comparator
Theory of Operation
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