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Электронный компонент: CS5157H

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Features
s
Dual N-Channel Design
s
Excess of 1MHz Operation
s
100ns Transient Response
s
5-Bit DAC
s
Backward Compatible with
Adjustable CS5120/5121
s
30ns Gate Rise/Fall Times
s
1% DAC Accuracy
s
5V & 12V Operation
s
Remote Sense
s
Programmable Soft Start
s
Lossless Short Circuit
Protection
s
V
CC
Monitor
s
25ns FET Nonoverlap Time
s
V
2
TM
Control Topology
s
Current Sharing
s
Overvoltage Protection
Package Options
CPU 5-Bit Synchronous Buck Controller
CS5157H
Description
Application Diagram
1
V
ID0
V
ID1
V
ID2
V
ID3
SS
V
ID4
C
OFF
V
FFB
V
FB
COMP
LGnd
V
CC1
V
GATE(L)
PGnd
V
GATE(H)
V
CC2
16 Lead SO Narrow
1
0.33
F
V
ID0
V
ID1
V
ID2
V
ID3
V
ID0
V
ID1
V
ID2
V
ID3
V
CC1
SS
CS5157H
C
OFF
LGnd
V
FB
V
FFB
COMP
IRL3103
IRL3103
0.1
F
12V
5V
2
H
1.3V to 3.5V @ 13A
V
CC2
V
GATE(H)
V
GATE(L)
PGnd
1200
F/10V x 3
AlEl
3.3k
0.1
F
1200
F/10V x 5
AlEl
100pF
330pF
V
ID4
V
ID4
Pentium is a registered trademark of Intel Corporation.
A Company
V
2
is a trademark of Switch Power, Inc.
Rev. 1/27/99
CS5157H
The CS5157H is a 5-bit synchronous
dual N-Channel buck controller. It
is designed to provide unprece-
dented transient response for
today's demanding high-density,
high-speed logic. The regulator
operates using a proprietary control
method, which allows a 100ns
response time to load transients.
The CS5157H is designed to operate
over a 4.25-20V range (V
CC
) using
12V to power the IC and 5V or
12Vas the main supply for conver-
sion.
The CS5157H is specifically
designed to power Pentium
II pro-
cessors and other high performance
core logic. It includes the following
features: on board, 5-bit DAC, short
circuit protection, 1.0% output tol-
erance, V
CC
monitor, and pro-
grammable soft start capability. The
CS5157H is available in 16 pin sur-
face mount.
Switching Power Supply for core logic - Pentium
II processor
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CS5157H
Electrical Characteristics:
0C < T
A
< +70C; 0C < T
J
< +125C; 8V < V
CC1
< 14V; 5V < V
CC2
< 20V; DAC Code: V
ID4
= V
ID2
=
V
ID1
= V
ID0
= 1; V
ID3
= 0; CV
GATE(L)
and CV
GATE(H)
= 1nF; C
OFF
= 330pF; C
SS
= 0.1F, unless otherwise specified.
Absolute Maximum Ratings
Pin Name
Max Operating Voltage
Max Current
V
CC1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA DC/1.5A peak
V
CC2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA DC/1.5A peak
SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-100A
COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200A
V
FB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2A
C
OFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2A
V
FFB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2A
V
ID0
- V
ID4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-50A
V
GATE(H)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA DC/1.5A peak
V
GATE(L)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA DC/1.5A peak
LGnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA
PGnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA DC/1.5A peak
Operating Junction Temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to 150C
Lead Temperature Soldering
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max above 183C, 230C peak
Storage Temperature Range, T
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to 150C
ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
s
Error Amplifier
V
FB
Bias Current
V
FB
= 0V
0.3
1.0
A
Open Loop Gain
1.25V < V
COMP
< 4V; Note 1
50
60
dB
Unity Gain Bandwidth
Note 1
500
3000
kHz
COMP SINK Current
V
COMP
= 1.5V; V
FB
= 3V; V
SS
> 2V
0.4
2.5
8.0
mA
COMP SOURCE Current
V
COMP
= 1.2V; V
FB
= 2.7V; V
SS
= 5V
30
50
80
A
COMP CLAMP Current
V
COMP
= 0V; V
FB
= 2.7V
0.4
1.0
1.6
mA
COMP High Voltage
V
FB
= 2.7V; V
SS
= 5V
4.0
4.3
5.0
V
COMP Low Voltage
V
FB
=3V 160
600
mV
PSRR
8V < V
CC1
< 14V @ 1kHz; Note 1
60
85
dB
s
V
CC1
Monitor
Start Threshold
Output switching
3.75
3.90
4.05
V
Stop Threshold
Output not switching
3.70
3.85
4.00
V
Hysteresis
Start-Stop
50
mV
s
DAC
Input Threshold
V
ID0
, V
ID1
, V
ID2
, V
ID3
, V
ID4
1.00
1.25
2.40
V
Input Pull Up Resistance
V
ID0
, V
ID1
, V
ID2
, V
ID3
, V
ID4
25
50
100
k
Pull Up Voltage
4.85
5.00
5.15
V
Accuracy
(all codes except 11111)
Measure V
FB
= V
COMP
, 25C T
J
125C
1.0
%
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
0
1
1
1
1
1.2870
1.3000
1.3130
V
0
1
1
1
0
1.3365
1.3500
1.3635
V
0
1
1
0
1
1.3860
1.4000
1.4140
V
0
1 1
0
0
1.4355
1.4500
1.4645
V
0
1
0
1
1
1.4850
1.5000
1.5150
V
0
1
0
1
0
1.5345
1.5500
1.5655
V
0
1
0
0
1
1.5840
1.6000
1.6160
V
0
1 0
0
0
1.6335
1.6500
1.6665
V
0
0 1
1
1
1.6830
1.7000
1.7170
V
CS5157H
3
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Electrical Characteristics:
0C < T
A
< +70C; 0C < T
J
< +125C; 8V < V
CC1
< 14V; 5V < V
CC2
< 20V; DAC Code: V
ID4
= V
ID2
=
V
ID1
= V
ID0
= 1; V
ID3
= 0; CV
GATE(L)
and CV
GATE(H)
= 1nF; C
OFF
= 330pF; C
SS
= 0.1F, unless otherwise specified.
s
DAC: continued
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
0
0 1 1
0
1.7325
1.7500
1.7675
V
0
0 1
0
1
1.7820
1.8000
1.8180
V
0
0 1
0
0
1.8315
1.8500
1.8685
V
0
0
0
1
1
1.8810
1.9000
1.9190
V
0
0
0
1
0
1.9305
1.9500
1.9695
V
0
0
0
0
1
1.9800
2.0000
2.0200
V
0
0 0
0
0
2.0295
2.0500
2.0705
V
1
1
1
1
1
1.2191
1.2440
1.2689
V
1
1
1
1
0
2.0790
2.1000
2.1210
V
1
1
1
0
1
2.1780
2.2000
2.2220
V
1
1
1
0
0
2.2770
2.3000
2.3230
V
1
1
0
1
1
2.3760
2.4000
2.4240
V
1
1
0
1
0
2.4750
2.5000
2.5250
V
1
1
0
0
1
2.5740
2.6000
2.6260
V
1
1
0
0
0
2.6730
2.7000
2.7270
V
1
0
1
1
1
2.7720
2.8000
2.8280
V
1
0
1
1
0
2.8710
2.9000
2.9290
V
1
0
1
0
1
2.9700
3.0000
3.0300
V
1
0
1
0
0
3.0690
3.1000
3.1310
V
1
0
0
1
1
3.1680
3.2000
3.2320
V
1
0
0
1
0
3.2670
3.3000
3.3330
V
1
0
0
0
1
3.3660
3.4000
3.4340
V
1
0
0
0
0
3.4650
3.5000
3.5350
V
s
V
GATE(H)
and V
GATE(L)
Out SOURCE Sat at 100mA
Measure V
CC1
V
GATE(L),
;V
CC2
V
GATE(H)
1.2
2.0
V
Out SINK Sat at 100mA
Measure V
GATE(H)
V
PGnd
; 1.0
1.5
V
V
GATE(L)
V
PGnd
Out Rise Time
1V < V
GATE(H)
< 9V; 1V < V
GATE(L)
< 9V
30
50
ns
V
CC1
= V
CC2
= 12V
Out Fall Time
9V > V
GATE(H)
> 1V; 9V > V
GATE(L)
> 1V
30
50
ns
V
CC1
= V
CC2
= 12V
Delay V
GATE(H)
to V
GATE(L)
V
GATE(H)
falling to 2V; V
CC1
= V
CC2
= 8V
25
50
ns
V
GATE(L)
rising to 2V
Delay V
GATE(L)
to V
GATE(H)
V
GATE(L)
falling to 2V; V
CC1
= V
CC2
= 8V
25
50
ns
V
GATE(H)
rising to 2V
V
GATE(H)
, V
GATE(L)
Resistance
Resistor to LGnd (Note 1)
20
50
100
k
V
GATE(H)
, V
GATE(L)
Schottky
LGnd to V
GATE(H)
@ 10mA
600
800
mV
LGnd to V
GATE(L)
@ 10mA
s
Soft Start (SS)
Charge Time
1.6
3.3
5.0
ms
Pulse Period
25
100
200
ms
Duty Cycle
(Charge Time/Pulse Period) 100
1.0
3.3
6.0
%
COMP Clamp Voltage
V
FB
= 0V; V
SS
= 0
0.50
0.95
1.10
V
V
FFB
SS Fault Disable
V
GATE(H)
= Low; V
GATE(L)
= Low
0.9
1.0
1.1
V
High Threshold
2.5
3.0
V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4
CS5157H
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
Electrical Characteristics:
0C < T
A
< +70C; 0C < T
J
< +125C; 8V < V
CC1
< 14V; 5V < V
CC2
< 20V; DAC Code: V
ID4
= V
ID2
=
V
ID1
= V
ID0
= 1; V
ID3
= 0; CV
GATE(L)
and CV
GATE(H)
= 1nF; C
OFF
= 330pF; C
SS
= 0.1F, unless otherwise specified.
s
PWM Comparator
Transient Response
V
FFB
= 0 to 5V to V
GATE(H)
= 9V to 1V;
100
125
ns
V
CC1
= V
CC2
= 12V
V
FFB
Bias Current
V
FFB
= 0V
0.3
A
s
Supply Current
I
CC1
No Switching
8.5
13.5
mA
I
CC2
No Switching
1.6
3.0
mA
Operating I
CC1
V
FB
= COMP = V
FFB
8
13
mA
Operating I
CC2
V
FB
= COMP = V
FFB
2
5
mA
s
C
OFF
Normal Charge Time
V
FFB
= 1.5V; V
SS
= 5V
1.0
1.6
2.2
s
Extension Charge Time
V
SS
= V
FFB
= 0
5.0
8.0
11.0
s
Discharge Current
C
OFF
to 5V; V
FB
>1V
5.0
mA
s
Time Out Timer
Time Out Time
V
FB
= V
COMP
; V
FFB
= 2V;
10
30
65
s
Record V
GATE(H)
Pulse High Duration
Fault Mode Duty Cycle
V
FFB
= 0V
35
50
70
%
Note 1: Guaranteed by design, not 100% tested in production.
16L SO Narrow
1,2,3,4,6
V
ID0
V
ID4
Voltage ID DAC input pins. These pins are internally pulled up to 5V
providing logic ones if left open. V
ID4
selects the DAC range. When V
ID4
is High (logic one), the DAC range is 2.10V to 3.50V with 100mV incre-
ments. When V
ID4
is Low (logic zero), the DAC range is 1.30V to 2.05V
with 50mV increments. V
ID0
- V
ID4
select the desired DAC output volt-
age. Leaving all 5 DAC input pins open results in a DAC output voltage
of 1.2440V, allowing for adjustable output voltage, using a traditional
resistor divider.
5
SS
Soft Start Pin. A capacitor from this pin to LGnd in conjunction with
internal 60A current source provides soft start function for the con-
troller. This pin disables fault detect function during Soft Start. When a
fault is detected, the soft start capacitor is slowly discharged by internal
2A current source setting the time out before trying to restart the IC.
Charge/discharge current ratio of 30 sets the duty cycle for the IC when
the regulator output is shorted.
7
C
OFF
A capacitor from this pin to ground sets the time duration for the on
board one shot, which is used for the constant off time architecture.
8
V
FFB
Fast feedback connection to the PWM comparator. This pin is connected
to the regulator output. The inner feedback loop terminates on time.
9
V
CC2
Boosted power for the high side gate driver.
10
V
GATE(H)
High FET driver pin capable of 1.5A peak switching current. Internal cir-
cuit prevents V
GATE(H)
and V
GATE(L)
from being in high state simultane-
ously.
5
CS5157H
Block Diagram
Package Pin Description: continued
PACKAGE PIN #
PIN SYMBOL
FUNCTION
16L SO Narrow
11
PGnd
High current ground for the IC. The MOSFET drivers are referenced to
this pin. Input capacitor ground and the source of lower FET should be
tied to this pin.
12
V
GATE(L)
Low FET driver pin capable of 1.5A peak switching current.
13
V
CC1
Input power for the IC and low side gate driver.
14
LGnd
Signal ground for the IC. All control circuits are referenced to this pin.
15
COMP
Error amplifier compensation pin. A capacitor to ground should be
provided externally to compensate the amplifier.
16
V
FB
Error amplifier DC feedback input. This is the master voltage feedback
which sets the output voltage. This pin can be connected directly to the
output or a remote sense trace.
Q
V
ID1
V
CC1
SS
COMP
V
FB
V
ID0
LGnd
V
FFB
V
CC2
V
GATE(H)
PGnd
V
GATE(L)
V
ID2
V
ID3
-
+
5 BIT
DAC
C
OFF
Slow Feedback
Maximum
On-Time
Timeout
V
CC1
R
Q
S
COFF
One Shot
PWM
COMP
SS High
Comparator
FAULT
Latch
2.5V
Error
Amplifier
Fast Feedback
-
+
V
CC1
Monitor
Comparator
V
ID4
-
+
-
+
-
+
-
+
VFFB Low
Comparator
PWM
Comparator
SS Low
Comparator
R
Q
S
Q
R
Q
S
2
A
5V
60
A
Normal
Off-Time
Timeout
Extended
Off-Time
Timeout
Time Out
Timer
(30
s)
Edge Triggered
Off-Time
Timeout
3.90V
3.85V
FAULT
FAULT
GATE(H) = ON
GATE(H) = OFF
PGnd
PWM
Latch
1V
0.7V
CS5157H
Applications Information
6
V
2
TM
Control Method
The V
2
TM
method of control uses a ramp signal that is gen-
erated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is gen-
erated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
Figure 1: V
2
TM
Control Diagram
The V
2
TM
control method is illustrated in Figure 1. The out-
put voltage is used to generate both the error signal and the
ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regard-
less of the origin of that change. The ramp signal also con-
tains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V
2
TM
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V
2
TM
control scheme has the same
advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this `slow' feedback loop is to provide
DC accuracy. Noise immunity is significantly improved,
since the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote sens-
ing of the output voltage, since the noise associated with
long feedback traces can be effectively filtered.
Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to compen-
sate for a deviation in either line or load voltage. This
change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation. A
current mode controller maintains fixed error signal under
deviation in the line voltage, since the slope of the ramp
signal changes, but still relies on a change in the error sig-
nal for a deviation in load. The V
2
TM
method of control
maintains a fixed error signal for both line and load varia-
tion, since the ramp signal is affected by both line and load.
Constant Off Time
To maximize transient response, the CS5157H uses a con-
stant off time method to control the rate of output pulses.
During normal operation, the off time of the high side
switch is terminated after a fixed period, set by the C
OFF
capacitor. To maintain regulation, the V
2
TM
control loop
varies switch on time. The PWM comparator monitors the
output voltage ramp, and terminates the switch on time.
Constant off time provides a number of advantages. Switch
duty cycle can be adjusted from 0 to 100% on a pulse by
pulse basis when responding to transient conditions. Both
0% and 100% duty cycle operation can be maintained for
extended periods of time in response to load or line tran-
sients. PWM slope compensation to avoid sub-harmonic
oscillations at high duty cycles is avoided.
Switch on time is limited by an internal 25s timer, mini-
mizing stress to the power components.
Programmable Output
The CS5157H is designed to provide two methods for pro-
gramming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges.
The first range is 2.10V to 3.50V in 100mV steps, the second
is 1.30V to 2.05V in 50mV steps, depending on the digital
input code. If all five bits are left open, the CS5157H enters
adjust mode. In adjust mode, the designer can choose any
output voltage by using resistor divider feedback to the
V
FB
and V
FFB
pins, as in traditional controllers.
Start Up
Until the voltage on the V
CC1
supply pin exceeds the 3.9V
monitor threshold, the soft start and gate pins are held low.
The FAULT latch is reset (no Fault condition). The output
of the error amplifier (COMP) is pulled up to 1V by the
comparator clamp. When the V
CC1
pin exceeds the monitor
threshold, the GateH output is activated, and the soft start
capacitor begins charging. The GateH output will remain
on, enabling the NFET switch, until terminated by either
the PWM comparator, or the maximum on time timer.
If the maximum on time is exceeded before the regulator
output voltage achieves the 1V level, the pulse is terminat-
ed. The GateH pin drives low, and the GateL pin drives
high for the duration of the extended off time. This time is
set by the time out timer and is approximately equal to the
maximum on time, resulting in a 50% duty cycle. The
GateL pin will then drive low, the GateH pin will drive
high, and the cycle repeats.
When regulator output voltage achieves the 1V level pre-
sent at the COMP pin, regulation has been achieved and
normal off time will ensue. The PWM comparator termi-
Reference
Voltage
+
C
E
+
Ramp
Signal
Output
Voltage
Feedback
Error
Signal
V
GATE(H)
V
GATE(L)
Error
Amplifier
V
FFB
COMP
V
FB
PWM
Comparator
Theory of Operation
CS5157H
7
Applications Information: continued
nates the switch on time, with off time set by the C
OFF
capacitor. The V
2
TM
control loop will adjust switch duty
cycle as required to ensure the regulator output voltage
tracks the output of the error amplifier.
The soft start and COMP capacitors will charge to their
final levels, providing a controlled turn on of the regulator
output. Regulator turn on time is determined by the COMP
capacitor charging to its final value. Its voltage is limited
by the soft start COMP clamp and the voltage on the soft
start pin (see Figures 2 and 3).
Figure 2: CS5157H demonstration board startup in response to increas-
ing 12V and 5V input voltages. Extended off time is followed by normal
off time operation when output voltage achieves regulation to the error
amplifier output.
Figure 3: CS5157H demonstration board startup waveforms.
If the input voltage rises quickly, or the regulator output is
enabled externally, output voltage will increase to the level
set by the error amplifier output more rapidly, usually
within a couple of cycles (see Figure 4).
Figure 4: CS5157H demonstration board enable startup waveforms.
Normal Operation
During normal operation, switch off time is constant and
set by the C
OFF
capacitor. Switch on time is adjusted by the
V
2
TM
control loop to maintain regulation. This results in
changes in regulator switching frequency, duty cycle, and
output ripple in response to changes in load and line.
Output voltage ripple will be determined by inductor rip-
ple current working into the ESR of the output capacitors
(see Figures 5 and 6).
Figure 5: Peak-to-peak ripple on V
OUT
= 2.8V, I
OUT
= 0.5A (light load).
Trace 1 - Regulator Output Voltage (10mV/div.)
Trace 2 - Inductor Switching Node (5V/div.)
Trace 1 - Regulator Output Voltage (5V/div.)
Trace 2 - Inductor Switching Node (5V/div.)
Trace 1 - Regulator Output Voltage (1V/div.)
Trace 3 - COMP Pin (error amplifier output) (1V/div.)
Trace 4 - Soft Start Pin (2V/div.)
Ch1 High
2.80V
Trace 1 - Regulator Output Voltage (1V/div.)
Trace 2 - Inductor Switching Node (2V/div.)
Trace 3 - 12V input (V
CC1
and V
CC2
) (5V/div.)
Trace 4 - 5V Input (1V/div.)
Applications Information: continued
CS5157H
8
Figure 6: Peak-to-peak ripple on V
OUT
= 2.8V, I
OUT
= 13A (heavy load).
Transient Response
The CS5157H V
2
TM
control loop's 100ns reaction time pro-
vides unprecedented transient response to changes in input
voltage or output current. Pulse by pulse adjustment of
duty cycle is provided to quickly ramp the inductor current
to the required level. Since the inductor current cannot be
changed instantaneously, regulation is maintained by the
output capacitor(s) during the time required to slew the
inductor current.
For best transient response, a combination of a number of
high frequency and bulk output capacitors are usually
used.
If the maximum on time is exceeded while responding to a
sudden increase in load current, a normal off time occurs to
prevent saturation of the output inductor.
Figure 7: CS5157H demonstration board response to a 0.5 to 13A load
pulse (output set for 2.8V).
Figure 8: CS5157H demonstration board response to 13A load turn on
(output set for 2.8V). Upon completing a normal off time, the V
2
TM
con-
trol loop immediately connects the inductor to the input voltage, pro-
viding 100% duty cycle. Regulation is achieved in less than 20s.
Figure 9: CS5157H demonstration board response to 13A load turn off
(output set for 2.8V). V
2
TM
control topology immediately connects
inductor to ground, providing 0% duty cycle. Regulation is achieved in
less than 10s.
V
CC1
Monitor
To maintain predictable startup and shutdown characteris-
tics an internal V
CC1
monitor circuit is used to prevent the
part from operating below 3.75V minimum startup. The
V
CC1
monitor comparator provides hysteresis and guaran-
tees a 3.70V minimum shutdown threshold.
Protection and Monitoring Features
Trace1 - Regulator Output Voltage (100mV/div.)
Trace 2 - Inductor Switching Node (5V/div.)
Trace 3 - Output Current (13 to 0.5 Amps) (10A/div.)
Trace 1 - Regulator Output Voltage (100mV/div.)
Trace 2 - Inductor Switching Node (5V/div.)
Trace 3 - Output Current (0.5 to 13 Amps) (10A/div.)
Trace 1 - Regulator Output Voltage (100mV/div.)
Trace 3 - Regulator Output Current (10A/div.)
Trace1 - Regulator Output Voltage (10mV/div.)
Trace 2 - Inductor Switching Node (5V/div.)
CS5157H
Applications Information: continued
9
Short Circuit Protection
A lossless hiccup mode short circuit protection feature is
provided, requiring only the soft start capacitor to imple-
ment. If a short circuit condition occurs (V
FFB
< 1V), the V
FFB
low comparator sets the FAULT latch. This causes the top
MOSFET to shut off, disconnecting the regulator from it's
input voltage. The soft start capacitor is then slowly dis-
charged by a 2A current source until it reaches it's lower
0.7V threshold. The regulator will then attempt to restart nor-
mally, operating in it's extended off time mode with a 50%
duty cycle, while the soft start capacitor is charged with a
60A charge current.
If the short circuit condition persists, the regulator output
will not achieve the 1V low V
FFB
comparator threshold
before the soft start capacitor is charged to it's upper 2.5V
threshold. If this happens the cycle will repeat itself until the
short is removed. The soft start charge/discharge current
ratio sets the duty cycle for the pulses (2A/60A = 3.3%),
while actual duty cycle is half that due to the extended off
time mode (1.65%).
This protection feature results in less stress to the regulator
components, input power supply, and PC board traces
than occurs with constant current limit protection (see
Figures 10 and 11).
If the short circuit condition is removed, output voltage
will rise above the 1V level, preventing the FAULT latch
from being set, allowing normal operation to resume.
Figure 10: CS5157H demonstration board hiccup mode short circuit pro-
tection. Gate pulses are delivered while the soft start capacitor charges,
and cease during discharge.
Figure 11: Startup with regulator output shorted.
Overvoltage Protection
Overvoltage protection (OVP) is provided as result of the
normal operation of the V
2
TM
control topology and requires
no additional external components. The control loop
responds to an overvoltage condition within 100ns, causing
the top MOSFET to shut off, disconnecting the regulator
from it's input voltage. The bottom MOSFET is then acti-
vated, resulting in a "crowbar" action to clamp the output
voltage and prevent damage to the load (see Figures 12 and
13). The regulator will remain in this state until the over-
voltage condition ceases or the input voltage is pulled low.
The bottom FET and board trace must be properly
designed to implement the OVP function.
Figure 12: OVP response to an input-to-output short circuit by immedi-
ately providing 0% duty cycle, crow-barring the input voltage to
ground.
Trace 4 = 5V from PC Power Supply (5V/div.)
Trace1 = Regulator Output Voltage (1V/div.)
Trace 2 = Inductor Switching Node (5V/div.)
Trace 4 = 5V from PC Power Supply (2V/div.)
Trace 2 = Inductor Switching Node (2V/div.)
Trace 4 - 5V Supply Voltage (2V/div.)
Trace 3 - Soft Start Timing Capacitor (1V/div.)
Trace 2 - Inductor Switching Node (2V/div.)
Applications Information: continued
CS5157H
10
Figure 13: OVP response to an input-to-output short circuit by pulling
the input voltage to ground.
External Output Enable Circuit
On/off control of the regulator can be implemented
through the addition of two additional discrete compo-
nents (see Figure 14). This circuit operates by pulling the
soft start pin high, and the V
FFB
pin low, emulating a short
circuit condition.
Figure 14: Implementing shutdown with the CS5157H.
External Power Good Circuit
An optional Power Good signal can be generated through
the use of four additional external components (see Figure
15). The threshold voltage of the Power Good signal can be
adjusted per the following equation:
V
Power Good
=
This circuit provides an open collector output that drives
the Power Good output to ground for regulator voltages
less than V
Power Good
.
Figure 15: Implementing Power Good with the CS5157H.
Figure 16: CS5157H demonstration board during power up. Power Good
signal is activated when output voltage reaches 1.70V.
Selecting External Components
The CS5157H can be used with a wide range of external
power components to optimize the cost and performance of
a particular design. The following information can be used
as general guidelines to assist in their selection.
NFET Power Transistors
Both logic level and standard MOSFETs can be used. The
reference designs derive gate drive from the 12V supply
which is generally available in most computer systems and
utilize logic level MOSFETs. Multiple MOSFETs may be
paralleled to reduce losses and improve efficiency and ther-
mal management.
Voltage applied to the MOSFET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5V of ground
when in the low state and to within 2V of their respective
bias supplies when in the high state. In practice, the MOS-
FET gates will be driven rail to rail due to overshoot caused
by the capacitive load they present to the controller IC. For
the typical application where V
CC1
= V
CC2
= 12V and 5V is
Trace 3 = 12V Input (V
CC1
) and V
CC2
) (10V/div.)
Trace 4 = 5V Input (2V/div.)
Trace 1 = Regulator Output Voltage (1V/div.)
Trace 2 = Power Good Signal (2V/div.)
Ch 1 High
2.80V
V
OUT
CS5157H
R1
10k
R2
6.2k
R3
10k
Power Good
5V
PN3904
PN3904
(R1 + R2) 0.65V
R2
Shutdown
Input
5V
V
FFB
CS5157H
SS
5
8
IN4148
MMUN2111T1 (SOT-23)
Trace 4 = 5V from PC Power Supply (2V/div.)
Trace 1 = Regulator Output Voltage (1V/div.)
CS5157H
Applications Information: continued
11
used as the source for the regulator output current, the fol-
lowing gate drive is provided;
V
GATE(H)
= 12V - 5V = 7V, V
GATE(L)
= 12V (see Figure 17).
Figure 17: CS5157H gate drive waveforms depicting rail to rail swing.
The most important aspect of MOSFET performance is
RDS
ON
, which effects regulator efficiency and MOSFET
thermal management requirements.
The power dissipated by the MOSFETs may be estimated
as follows;
Switching MOSFET:
Power = I
LOAD
2
RDS
ON
duty cycle
Synchronous MOSFET:
Power = I
LOAD
2
RDS
ON
(1 - duty cycle)
Duty Cycle =
Off Time Capacitor (C
OFF
)
The C
OFF
timing capacitor sets the regulator off time:
T
OFF
= C
OFF
4848.5
When the V
FFB
pin is less than 1V, the current charging the
C
OFF
capacitor is reduced. The extended off time can be cal-
culated as follows:
T
OFF
= C
OFF
24,242.5.
Off time will be determined by either the T
OFF
time, or the
time out timer, whichever is longer.
The preceding equations for duty cycle can also be used to
calculate the regulator switching frequency and select the
C
OFF
timing capacitor:
C
OFF
= ,
where:
Period =
Schottky Diode for Synchronous MOSFET
A Schottky diode may be placed in parallel with the syn-
chronous MOSFET to conduct the inductor current upon
turn off of the switching MOSFET to improve efficiency.
The CS5157H reference circuit does not use this device due
to it's excellent design. Instead, the body diode of the syn-
chronous MOSFET is utilized to reduce cost and conducts
the inductor current. For a design operating at 200kHz or so,
the low non-overlap time combined with Schottky forward
recovery time may make the benefits of this device not
worth the additional expense (see Figure 6, channel 2). The
power dissipation in the synchronous MOSFET due to body
diode conduction can be estimated by the following equation:
Power = V
bd
I
LOAD
conduction time switching frequency
Where V
bd
= the forward drop of the MOSFET body diode.
For the CS5157H demonstration board as shown in Figure 6;
Power = 1.6V 13A 100ns 233kHz = 0.48W
This is only 1.3% of the 36.4W being delivered to the load.
Input and Output Capacitors
These components must be selected and placed carefully to
yield optimal results. Capacitors should be chosen to pro-
vide acceptable ripple on the input supply lines and regula-
tor output voltage. Key specifications for input capacitors
are their ripple rating, while ESR is important for output
capacitors. For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
Output Inductor
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the induc-
tor value will decrease output voltage ripple, but degrade
transient response.
Thermal Considerations for Power MOSFETs and Diodes
In order to maintain good reliability, the junction tempera-
ture of the semiconductor components should be kept to a
maximum of 150C or lower. The thermal impedance (junc-
tion to ambient) required to meet this requirement can be
calculated as follows:
Thermal Impedance =
T
JUNCTION(MAX)
- T
AMBIENT
Power
Thermal Management
1
switching frequency
Period (1 - duty cycle)
4848.5
V
OUT
+ (I
LOAD
RDS
ON OF SYNCH FET
)
V
IN
+ (I
LOAD
RDS
ON OF SYNCH FET
) - (I
LOAD
RDS
ON OF SWITCH FET
)
Trace 3 = V
GATE(H)
(10V/div.)
Math 1= V
GATE(H)
- 5V
IN
Trace 4 = V
GATE(L)
(10V/div.)
Trace 2 = Inductor Switching Node (5V/div.)
Applications Information: continued
CS5157H
12
A heatsink may be added to TO-220 components to reduce
their thermal impedance. A number of PC board layout
techniques such as thermal vias and additional copper foil
area can be used to improve the power handling capability
of surface mount components.
EMI Management
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional compo-
nents may be added to reduce noise emissions. These com-
ponents are not required for regulator operation and exper-
imental results may allow them to be eliminated. The input
filter inductor may not be required because bulk filter and
bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the cir-
cuit board and input power supply. Placement of the
power component to minimize routing distance will also
help to reduce emissions.
Figure 18: Filter components
Figure 19: Input Filter
Layout Guidelines
1. Place 12V filter capacitor next to the IC and connect
capacitor ground to pin 11 (PGnd).
2. Connect pin 11 (PGnd) with a separate trace to the
ground terminals of the 5V input capacitors.
3. Place fast feedback filter capacitor next to pin 8 (V
FFB
)
and connect it's ground terminal with a separate, wide
trace directly to pin 14 (LGnd).
4. Connect the ground terminals of the Compensation
capacitor directly to the ground of the fast feedback filter
capacitor to prevent common mode noise from effecting
the PWM comparator.
5. Place the output filter capacitor(s) as close to the load as
possible and connect the ground terminal to pin 14 (LGnd).
6. Connect the V
FB
pin directly to the load with a separate
trace (remote sense).
7. Place 5V input capacitors close to the switching MOSFET
and synchronous MOSFET.
Route gate drive signals V
GATE(H)
(pin 10) and V
GATE(L)
(pin 12 when used) with traces that are a minimum of 0.025
inches wide.
Figure 20: Layout Guidelines
15
To the negative terminal of the
input capacitors
100pF
V
FFB
11
8
OFF TIME
5
SOFTSTART
V
CC
0.1
F
To the negative terminal of the output capacitors
1.0
F
V
COMP
+
2
H
1200
F x 3/16V
33
1000pF
2
H
CS5157H
13
Additional Application Circuits
Figure 21: 5V to 3.3V/10A converter.
Figure 22: 5V to 3.3V/10A converter with current sharing.
Figure 23: 12V to 3.3V/5A converter with remote sense.
Figure 24: 3.3V to 2.5V/7A converter with 12V bias.
0.33
F
V
ID0
V
ID1
V
ID2
V
ID3
V
CC1
CS5157H
C
OFF
V
FB
V
FFB
COMP
Si9410
Si9410
12V
+
+
5
H
2.5V/7A
V
CC2
PGnd
3.3k
0.1
F
100
F/10V x 2
Tantalum
100pF
330pF
1
F
33
F/25V x 3
Tantalum
3.3V
SS
LGnd
V
GATE(H)
V
GATE(L)
V
ID4
0.33
F
V
ID0
V
ID1
V
ID2
V
ID3
V
CC1
SS
CS5157H
C
OFF
LGnd
V
FB
V
FFB
COMP
12V
+
+
1.1
H
3.3V/5A
V
CC2
V
GATE(H)
V
GATE(L)
PGnd
3.3k
0.1
F
100pF
330pF
1
F
0.1
F
V
ID4
1N4746
18V 1W
1
F
1N5818
1N5818
22
1/4W
FY10AAJ-
03
820
F/16V
4
Aluminum
Electrolytic
1200
F/10V
2
Aluminum
Electrolytic
FY10AAJ-
03
FY10AAJ-
03
+12V
0.33
F
V
ID0
V
ID1
V
ID2
V
ID3
V
CC1
CS5157H
C
OFF
V
FB
V
FFB
COMP
Si9410
Si4410
1
F
5V
+
+
3
H
3.3V/10A
V
CC2
PGnd
3.3k
0.1
F
100
F/10V x 3
Tantalum
100pF
330pF
0.1
F
1
F
MBRS120
MBRS120
100
F/10V x 3
Tantalum
10
Remote
Sense
Connect to
other circuits for
current sharing
SS
LGnd
V
GATE(H)
V
GATE(L)
V
ID4
MBRS
120
0.33
F
V
ID0
V
ID1
V
ID2
V
ID3
V
CC1
CS5157H
C
OFF
V
FB
V
FFB
COMP
Si9410DY
Si4410DY
1
F
5V
+
+
3
H
3.3V/10A
V
CC2
PGnd
3.3k
0.1
F
100
F/10V x 3
Tantalum
100pF
330pF
0.1
F
1
F
MBRS120
MBRS120
100
F/10V x 3
Tantalum
SS
LGnd
V
GATE(H)
V
GATE(L)
V
ID4
MBRS
120
14
1999 Cherry Semiconductor Corporation
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
Thermal Data
16L
SO Narrow
R
JC
typ
28
C/W
R
JA
typ
115
C/W
D
Lead Count
Metric
English
Max
Min
Max
Min
16L SO Narrow
10.00
9.80
.394
.386
CS5157H
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES)
PACKAGE THERMAL DATA
Rev. 1/27/99
Ordering Information
Part Number
Description
CS5157HGD16
16L SO Narrow
CS5157HGDR16
16L SO Narrow (tape & reel)
Surface Mount Narrow Body (D); 150 mil wide
1.27 (.050) BSC
0.51 (.020)
0.33 (.013)
6.20 (.244)
5.80 (.228)
4.00 (.157)
3.80 (.150)
1.57 (.062)
1.37 (.054)
D
0.25 (0.10)
0.10 (.004)
1.75 (.069) MAX
1.27 (.050)
0.40 (.016)
REF: JEDEC MS-012
0.25 (.010)
0.19 (.008)