ChipFind - документация

Электронный компонент: CS5166GDW16

Скачать:  PDF   ZIP
1
V
ID0
PWRGD
V
ID1
V
ID4
V
ID3
V
ID4
V
ID3
V
ID2
COMP
12V
5V
1.2H
GATE(H)
GATE(L)
PGnd
1200F/10V x 3
1F
SS
LGnd
330pF
0.1F
V
ID0
1200F
10V x 5
V
ID2
V
ID1
Pentium II
System
CS5166
V
FB
C
OFF
V
CC
PWRGD
I
SENSE
3.0m
1000pF
510
3.3K
0.1F
0.1F
Features
s
V
2
TM
Control Topology
s
Dual N-Channel Design
s
125ns Controller Transient Response
s
Excess of 1Mhz Operation
s
5-bit DAC with 1% Tolerance
s
Power-Good Output with Internal
Delay
s
Adjustable Hiccup Mode Over
Current Protection
s
Complete Pentium
II System
Requires just 21 Components
s
5V and 12V Operation
s
Adaptive Voltage Positioning
s
Remote Sense Capability
s
Current Sharing Capability
s
V
CC
Monitor
s
Overvoltage Protection (OVP)
s
Programmable Soft Start
s
200ns PWM Blanking
s
65ns FET Non-Overlap
s
40ns Gate Rise and Fall Times
(3.3nF load)
Package Options
CS5166
5-Bit Synchronous CPU Controller
with Power-Good and Current Limit
CS5166
Description
The CS5166 is a synchronous
dual NFET Buck Regulator
Controller. It is designed to pow-
er the core logic of the latest high
performance CPUs. It uses the
V
2
TM
control method to achieve
the fastest possible transient
response and best overall regula-
tion. It incorporates many addi-
tional features required to ensure
the proper operation and protec-
tion of the CPU and power sys-
tem. The CS5166 provides the
industry's most highly integrat-
ed solution, minimizing external
component count, total solution
size, and cost.
The CS5166 is specifically
designed to power Intel's
Pentium
II processor and
includes the following features:
5-bit DAC with 1% tolerance,
Power-Good output, adjustable
hiccup mode over-current pro-
tection, V
CC
monitor, Soft Start,
adaptive voltage positioning,
over-voltage protection, remote
sense and current sharing capa-
bility.
The CS5166 will operate over a
4.15 to 14V range and is available
in a 16 lead wide body surface
mount package.
Application Diagram
1
16 Lead SO WIDE
A Company
V
ID0
V
ID1
V
ID2
V
ID3
I
SENSE
C
OFF
SS
V
ID4
V
FB
COMP
LGnd
PWRGD
GATE(L)
PGnd
GATE(H)
V
CC
Pentium is a registered trademark of Intel Corporation.
5V to 2.8V @ 14.2A for 300MHz Pentium II
V
2
is a trademark of Switch Power, Inc.
Rev. 6/28/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
Absolute Maximum Ratings
Pin Symbol
Pin Name
V
MAX
V
MIN
I
SOURCE
I
SINK
2
PACKAGE PIN #
PIN SYMBOL
FUNCTION
Package Pin Description
CS5166
V
CC
IC Power Input
16V
-0.3V
N/A
1.5A Peak 200mA DC
SS
Soft Start Capacitor
6V
-0.3V
200A
10A
COMP
Compensation Capacitor
6V
-0.3V
10mA
1mA
V
FB
Voltage Feedback and Current
6V
-0.3V
1mA
1mA
Sense Comparator Input
C
OFF
Off-Time Capacitor
6V
-0.3V
1mA
50mA
V
ID0-4
Voltage ID DAC Inputs
6V
-0.3V
1mA
10A
GATE(H)
High-Side FET Driver
16V
-0.3V
1.5A Peak
1.5A Peak
200mA DC
200mA DC
GATE(L)
Low-Side FET Driver
16V
-0.3V
1.5A Peak
1.5A Peak
200mA DC
200mA DC
I
SENSE
Current Sense Comparator Input
6V
-0.3V
1mA
1mA
PWRGD
Power-Good Output
6V
-0.3V
10A
30mA
PGnd
Power Ground
0V
0V
1.5A Peak
N/A
200mA DC
LGnd
Logic Ground
0V
0V
100mA
N/A
1,2,3,4,6
V
IDO
V
ID4
Voltage ID DAC inputs. These pins are internally pulled up to 5V if left
open. V
ID4
selects the DAC range. When V
ID4
is high (logic one), the
Error Amp reference range is 2.125V to 3.525V with 100mV increments.
When V
ID4
is low (logic zero), the Error amp reference voltage is 1.325V
to 2.075V with 50mV increments.
5
SS
Soft Start Pin. A capacitor from this pin to LGnd sets the Soft Start and
fault timing.
7
C
OFF
Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets both the
normal and extended off time.
8
I
SENSE
Current Sense Comparator Inverting Input
9
V
CC
Input Power Supply Pin.
10
GATE(H)
High Side Switch FET driver pin.
11
PGnd
High Current ground for the GATE(H) and GATE(L) pins.
12
GATE(L)
Low Side Synchronous FET driver pin.
13
PWRGD
Power-Good Output. Open collector output drives low when V
FB
is out
of regulation.
14
LGnd
Reference ground. All control circuits are referenced to this pin.
15
COMP
Error Amp output. PWM Comparator reference input. A capacitor to
LGnd provides Error Amp compensation.
16
V
FB
Error Amp, PWM Comparator feedback input, Current Sense
Comparator Non-Inverting input, and PWRGD comparator input.
Operating Junction Temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 150C
Lead Temperature Soldering:
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Sec max. above 183C, 230C Peak
Storage Temperature Range, T
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C
CS5166
3
Electrical Characteristics: 0C < T
A
< 70C; 0C < T
J
< 125C; 8V < V
CC
< 14V; 2.0V DAC Code
(V
ID4
= V
ID3
= V
ID2
= V
ID1
=0, V
ID0
= 1), C
GATE(H
) = C
GATE(L)
= 3.3nF, C
OFF
= 330pF, C
SS
= 0.1F; Unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
V
CC
Supply Current
Operating 1V<V
FB
<V
DAC
(Max On-Time),
No Loads on GATE(H) and GATE(L)
12
20
mA
s
V
CC
Monitor
Start Threshold
GATE(H) Switching
3.75
3.95
4.15
V
Stop Threshold
GATE(H) not switching
3.65
3.87
4.05
V
Hysteresis
Start Stop
80
mV
s
Error Amplifier
V
FB
Bias Current
V
FB
= 0V
0.1
1.0
A
COMP Source Current
COMP = 1.2V to 3.6V; V
FB
= 1.9V
15
30
60
A
COMP CLAMP Voltage
V
FB
= 1.9V, Adjust COMP voltage
0.85
1.0
1.15
V
for Comp current = 60A
COMP Clamp Current
COMP = 0V
0.4
1.0
1.6
mA
COMP Sink Current
V
COMP
=1.2V; V
FB
=2.2V; V
SS
> 2.5V
180
400
800
A
Open Loop Gain
Note 1
50
60
dB
Unity Gain Bandwidth
Note 1
0.5
2
MHz
PSRR @ 1kHZ
Note 1
60
85
dB
s
GATE(H) and GATE(L)
High Voltage at 100mA
Measure V
CC
GATE
1.2
2.0
V
Low Voltage at 100mA
Measure GATE
1.0
1.5
V
Rise Time
1.6V < GATE < (V
CC
2.5V)
40
80
ns
Fall Time
(V
CC
2.5V) >GATE > 1.6V
40
80
ns
GATE(H) to GATE(L) Delay
GATE(H)<2V, GATE(L)>2V
30
65
100
ns
GATE(L) to GATE(H) Delay
GATE(L)<2V, GATE(H)>2V
30
65
100
ns
GATE pull-down
Resistance to PGnd (Note 1)
20
50
115
k
s
Over Current Detection
Current limit voltage
V
FB
= 0V to 3.5V
55
76
130
mV
8V < V
CC
< 12V + 10%
I
SENSE
Bias Current
I
SENSE
= 2.8V
13
30
50
A
s
Fault Protection
SS Charge Time
V
FB
= 3V, V
ISENSE
= 2.8V
1.6
3.3
5.0
ms
SS Pulse Period
V
FB
= 3V, V
ISENSE
= 2.8V
25
100
200
ms
SS Duty Cycle
(Charge Time/Period) 100
1.0
3.3
6.0
%
CS5166
4
Electrical Characteristics: 0C < T
A
< 70C; 0C < T
J
< 125C; 8V < V
CC
< 14V; 2.0V DAC Code
(V
ID4
= V
ID3
= V
ID2
= V
ID1
=0, V
ID0
= 1), C
GATE(H
) = C
GATE(L)
= 3.3nF, C
OFF
= 330pF, C
SS
= 0.1F; Unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
Fault Protection continued
SS Comp Clamp Voltage
V
FB
= 2.7V, V
SS
= 0V
0.50
0.95
1.10
V
V
FB
Low Comparator
Increase V
FB
till normal off-time
0.9
1.0
1.1
V
s
PWM Comparator
Transient Response
V
FB
= 1.2V to 5V 500ns after GATE(H)
115
175
ns
(after Blanking time) to
GATE(H) = (V
CC
1V)
to 1V
Minimum Pulse Width
Drive V
FB
1.2V to 5V upon GATE(H)
100
200
300
ns
(Blanking Time)
rising edge (> V
CC
1V), measure
GATE(H) pulse width
s
C
OFF
Normal Off-Time
V
FB
= 2.7V
1.0
1.6
2.3
s
Extended Off-Time
V
SS
= V
FB
= 0V
5.0
8.0
12.0
s
s
Time-Out Timer
Time-Out Time
V
FB
= 2.7V, Measure GATE(H)
10
30
50
s
Pulse Width
Fault Duty Cycle
V
FB
= 0V
30
50
70
%
s
Voltage Identification DAC
Accuracy
(all codes except 11111)
Measure V
FB
= COMP, (C
OFF
= Gnd)
-1.0
1.0
%
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
25C T
J
125C, V
CC
= 12V
1
0
0
0
0
3.489
3.525
3.560
V
1
0
0
0
1
3.390
3.425
3.459
V
1
0
0
1
0
3.291
3.325
3.358
V
1
0
0
1
1
3.192
3.225
3.257
V
1
0
1
0
0
3.093
3.125
3.156
V
1
0
1
0
1
2.994
3.025
3.055
V
1
0
1
1
0
2.895
2.925
2.954
V
1
0
1
1
1
2.796
2.825
2.853
V
1
1
0
0
0
2.697
2.725
2.752
V
1
1
0
0
1
2.598
2.625
2.651
V
1
1
0
1
0
2.499
2.525
2.550
V
1
1
0
1
1
2.400
2.425
2.449
V
1
1
1
0
0
2.301
2.325
2.348
V
1
1
1
0
1
2.202
2.225
2.247
V
1
1
1
1
0
2.103
2.125
2.146
V
0
0
0
0
0 2.054
2.075
2.095
V
0
0
0
0
1
2.004
2.025
2.045
V
0
0
0
1
0
1.955
1.975
1.994
V
0
0
0
1
1
1.905
1.925
1.944
V
CS5166
5
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THRESHOLD ACCURACY
LOWER THRESHOLD
UPPER THRESHOLD
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
% of Nominal V
ID
Code
-12
-8.5
-5
5
8.5
12
%
s
DAC CODE
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
1
0
0
0
0
3.102
3.225
3.348
3.701
3.824
3.948
V
1
0
0
0
1
3.014
3.133
3.253
3.596
3.716
3.836
V
1
0
0
1
0
2.926
3.042
3.158
3.491
3.607
3.724
V
1
0
0
1
1
2.838
2.950
3.063
3.386
3.499
3.612
V
1
0
1
0
0
2.750
2.859
2.968
3.281
3.390
3.500
V
1
0
1
0
1
2.662
2.767
2.873
3.176
3.282
3.388
V
1
0
1
1
0
2.574
2.676
2.778
3.071
3.173
3.276
V
1
0
1
1
1
2.486
2.584
2.683
2.966
3.065
3.164
V
1
1
0
0
0
2.398
2.493
2.588
2.861
2.956
3.052
V
1
1
0
0
1
2.310
2.401
2.493
2.756
2.848
2.940
V
1
1
0
1
0
2.222
2.310
2.398
2.651
2.739
2.828
V
Electrical Characteristics: 0C < T
A
< 70C; 0C < T
J
< 125C; 8V < V
CC
< 14V; 2.0V DAC Code
(V
ID4
= V
ID3
= V
ID2
= V
ID1
=0, V
ID0
= 1), C
GATE(H
) = C
GATE(L)
= 3.3nF, C
OFF
= 330pF, C
SS
= 0.1F; Unless otherwise stated.
Accuracy
(all codes except 11111)
Measure V
FB
= COMP, (C
OFF
= Gnd)
-1.0
1.0
%
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
0
0
1
0
0
1.856
1.875
1.893
V
0
0
1
0
1
1.806
1.825
1.843
V
0
0
1
1
0
1.757
1.775
1.792
V
0
0
1
1
1
1.707
1.725
1.742
V
0
1
0
0
0
1.658
1.675
1.691
V
0
1
0
0
1
1.608
1.625
1.641
V
0
1
0
1
0
1.559
1.575
1.590
V
0
1
0
1
1
1.509
1.525
1.540
V
0
1
1
0
0
1.460
1.475
1.489
V
0
1
1
0
1
1.410
1.425
1.439
V
0
1
1
1
0
1.361
1.375
1.388
V
0
1
1
1
1
1.311
1.325
1.338
V
1
1
1
1
1
1.219
1.247
1.269
V
Input Threshold
V
ID4
, V
ID3
, V
ID2
, V
ID1
, V
ID0
1.0
1.25
2.4
V
Input Pull-up Resistance
V
ID4
, V
ID3
, V
ID2
, V
ID1
, V
ID0
25
50
100
k
Input Pull-up Voltage
4.85
5.00
5.15
V
s
Power-Good Output
Low to High Delay
V
FB
= (0.8 V
DAC
) to V
DAC
30
65
110
s
High to Low Delay
V
FB
= V
DAC
to (0.8 V
DAC
)
30
75
120
s
Output Low Voltage
V
FB
= 2.4V, I
PWRGD
= 500A
0.2
0.3
V
Sink Current Limit
V
FB
= 2.4V, PWRGD = 1V
0.5
4.0
15.0
mA