The CS52845 provides all the nec-
essary features to implement off-
line fixed frequency current-mode
control with a minimum number
of external components.
The CS52845 incorporates a new
precision temperature-controlled
oscillator to minimize variations in
frequency. An internal toggle flip-
flop, which blanks the output
every other clock cycle, limits the
duty-cycle range to less than 50%.
An undervoltage lockout ensures
that V
REF
is stabilized before the
output stage is enabled. In the
CS52845 turn on is at 8.4V and
turn off at 7.6V.
Other features include low start-up
current, pulse-by-pulse current lim-
iting, and a high-current totem pole
output for driving capacitive loads,
such as gate of a power MOSFET.
The output is low in the off state,
consistent with N-channel devices.
1
Features
V
CC
Gnd
COMP
OSC
Sense
V
REF
V
REF
Undervoltage
Lockout
Internal
Bias
NOR
S
R
PWM
Latch
Current
Sensing
Comparator
R
2 R
1V
Error
Amplifier
-
+
2.50V
Set/
Reset
V
CC
Undervoltage Lock-out
34V
8.4V/7.6V
R
R
V
FB
V
CC
Pwr
V
OUT
Pwr Gnd
Oscillator
Toggle
Flip-Flop
5.0 Volt
Reference
s
Optimized for Off-line
Control
s
Temperature
Compensated Oscillator
s
50% Maximum Duty-cycle
Clamp
s
V
REF
Stabilized before
Output Stage is Enabled
s
Low Start-up Current
s
Pulse-by-pulse Current
Limiting
s
Improved Undervoltage
Lockout
s
Double Pulse Suppression
s
1% Trimmed Bandgap
Reference
s
High Current Totem Pole
Output
Package Options
CS52845
Current Mode PWM Control Circuit
with 50% Max Duty Cycle
CS52845
Description
Block Diagram
Absolute Maximum Ratings
Supply Voltage (I
CC
<30mA) ..........................................................Self Limiting
Supply Voltage (Low Impedance Source)...................................................30V
Output Current ...............................................................................................1A
Output Energy (Capacitive Load) .................................................................5J
Analog Inputs (V
FB
, V
SENSE
)...........................................................-0.3V to 5.5V
Error Amp Output Sink Current...............................................................10mA
Lead Temperature Soldering
Reflow (SMD styles only) ...........60 sec. max above 183C, 230C peak
10
7
14
13
12
8
1
2
3
4
5
6
11
9
COMP
NC
V
FB
NC
Sense
NC
OSC
V
REF
NC
V
CC
V
CC
Pwr
V
OUT
Pwr Gnd
Gnd
14L SO Narrow
1
7
8
2
3
4
5
6
COMP
V
FB
Sense
OSC
V
REF
V
CC
V
OUT
Gnd
8L SO Narrow
Rev. 3/4/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
A Company
2
Electrical Characteristics: -40 T
A
85C; V
CC
= 15V (Note 1); R
T
= 10k; C
T
= 3.3nF for sawtooth mode.unless otherwise stated.
CS52845
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
Reference Section
Output Voltage
T
J
=25C, I
REF
=1mA
4.95
5.00
5.05
V
Line Regulation
12V
CC
25V
6
20
mV
Load Regulation
1I
REF
20mA
6
25
mV
Temperature Stability
(Note 2)
0.2
0.4
mV/C
Total Output Variation
Line, Load, Temp. (Note 2)
4.90
5.10
V
Output Noise Voltage
10Hzf10kHz, T
J
=25C (Note 2)
50
V
Long Term Stability
T
A
=125C, 1000 Hrs. (Note 2)
5
25
mV
Output Short Circuit
T
A
=25C
-30
-100
-180
mA
s
Oscillator Section
Initial Accuracy
Sawtooth Mode, T
J
=25C
47
52
57
kHz
Voltage Stability
12V
CC
25V
0.2
1.0
%
Temperature Stability
Sawtooth Mode T
MIN
T
A
T
MAX
(Note 2)
5
%
Amplitude
V
OSC
(peak to peak)
1.7
V
s
Error Amp Section
Input Voltage
V
COMP
=2.5V
2.45
2.50
2.55
V
Input Bias Current
V
FB
=0V
-0.3
-1.0
A
A
VOL
2V
OUT
4V
65
90
dB
Unity Gain Bandwidth
(Note 2)
0.7
1.0
MHz
PSRR
12V
CC
25V
60
70
dB
Output Sink Current
V
FB
=2.7V, V
COMP
=1.1V
2
6
mA
Output Source Current
V
FB
=2.3V, V
COMP
=5V
-0.5
-0.8
mA
V
OUT
HIGH
V
FB
=2.3V, R
L
=15k to Gnd
5
6
V
V
OUT
LOW
V
FB
=2.7V, R
L
=15k to V
REF
0.7
1.1
V
s
Current Sense Section
Gain
(Notes 3 & 4)
2.85
3.00
3.15
V/V
Maximum Input Signal
V
COMP
=5V (Note 3)
0.9
1.0
1.1
V
PSRR
12V
CC
25V (Note 3)
70
dB
Input Bias Current
V
Sense
=0V
-2
-10
A
Delay to Output
T
J
=25C (Note 2)
150
300
ns
s
Output Section
Output Low Level
I
SINK
=20mA
0.1
0.4
V
I
SINK
=200mA
1.5
2.2
V
Output High Level
I
SOURCE
=20mA
13.0
13.5
V
I
SOURCE
=200mA
12.0
13.5
V
Rise Time
T
J
=25C, C
L
=1nF (Note 2)
50
150
ns
Fall Time
T
J
=25C, C
L
=1nF (Note 2)
50
150
ns
3
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
Electrical Characteristics: Unless otherwise stated, specifications apply for -40 T
A
85C; V
CC
= 15V (Note 1); R
T
= 10k;
C
T
= 3.3nF for sawtooth mode.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
Total Standby Current
Start-Up Current
0.5
1.0
mA
Operating Supply Current
V
FB
=V
Sense
=0V R
T
=10k, C
T
=3.3nF
11
17
mA
V
CC
Zener Voltage
I
CC
=25mA
34
V
s
PWM Section
Maximum Duty Cycle
46
48
50
%
Minimum Duty Cycle
0
%
s
Undervoltage Lockout Section
Start Threshold
7.8
8.4
9.0
V
Min. Operating Voltage
After Turn On
7.0
7.6
8.2
V
Notes:
1. Adjust V
CC
above the start threshold before setting at 15V.
3. Parameter measured at trip point of latch with V
FB
=0.
2.These parameters, although guaranteed, are not 100% tested in production.
4. Gain defined as: A =
; 0 V
Sense
0.8V.
V
COMP
V
Sense
8L
14L
SO Narrow
SO Narrow
1
1
COMP
Error amp output, used to compensate error amplifier.
2
3
V
FB
Error amp inverting input.
3
5
Sense
Noninverting input to Current Sense Comparator.
4
7
OSC
Oscillator timing network with Capacitor to Ground, resistor to V
REF
.
5
9
Gnd
Ground.
5
8
Pwr Gnd
Output driver Ground.
6
10
V
OUT
Output drive pin.
7
11
V
CC
Pwr
Output driver positive supply.
7
12
V
CC
Positive power supply.
8
14
V
REF
Output of 5V internal reference.
2,4,6,13
NC
No Connection.
Undervoltage Lockout
During Undervoltage Lockout (Figure 1), the output driv-
er is biased to sink minor amounts of current. The output
should be shunted to ground with a resistor to prevent
activating the power switch with extraneous leakage cur-
rents.
PWM Waveform
To generate the PWM waveform, the control voltage from
the error amplifier is compared to a current sense signal
which represents the peak output inductor current (Figure
2). An increase in V
CC
causes the inductor current slope to
increase, thus reducing the duty cycle. This is an inherent
feed-forward characteristic of current mode control, since
the control voltage does not have to change during
changes of input supply voltage.
When the power supply sees a sudden large output cur-
rent increase, the control voltage will increase allowing
the duty cycle to momentarily increase. Since the duty
cycle tends to exceed the maximum allowed to prevent
transformer saturation in some power supplies, the inter-
nal oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of OSC compo-
nents.
4
Figure 1: Startup voltage for the CS52845.
Circuit Description
Test Circuit Open Loop Laboratory Test Fixture
V
REF
V
CC
V
OUT
1k
1W
0.1
F
0.1
F
V
REF
V
CC
V
OUT
Gnd
V
FB
Sense
OSC
COMP
5k
100k
4.7k
1k
Error Amp
Adjust
4.7k
Sense
Adjust
R
T
2N2222
C
T
Gnd
A
V
CC
V
ON
= 8.4V
V
OFF
= 7.6V
ON/OFF Command
to reset of IC
<15mA
<1mA
V
ON
V
OFF
I
CC
V
CC
Setting the Oscillator
The times T
c
and T
d
can be determined as follows:
Grounding
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd in a single
point ground.
The transistor and 5k potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.
5
CS52845
V
upper
V
lower
t
on
t
off
t
c
t
d
t
on
=t
c
t
off
=t
c
+2t
d
Circuit Description:: continued
Substituting in typical values for the parameters in the
above formulas:
V
REF
= 5.0V, V
upper
= 2.7V, V
lower
= 1.0V, I
d
= 8.3mA,
then
t
c
0.5534R
T
C
T
t
d
= R
T
C
T
ln
For better accuracy R
T
should be 10k.
)
2.3 - 0.0083 R
T
4.0 - 0.0083 R
T
(
V
CC
I
O
V
O
Switch
Current
EA Output
Toggle
F/F Output
OSC
RESET
V
OSC
Figure 2: Timing Diagram
Figure 3: Duty Cycle parameters.
t
c
= R
T
C
T
ln
t
d
= R
T
C
T
ln
)
V
REF
- I
d
R
T
- V
lower
V
REF
- I
d
R
T
- V
upper
(
)
V
REF
- V
lower
V
REF
- V
upper
(
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