1
Features
+
-
+
-
V
REF
SYNC
Oscillator
Error
Amp 1
Error
Amp 2
Latching
PWM 2
Latching
PWM 1
V
REF
Undervoltage
Lockout
5.0V Ref
V
CC
Undervoltage
Lockout
V
CC
V
FB1
COMP
1
ENABLE
2
V
FB2
COMP
2
C
T
R
T
Gnd
Pwr Gnd
Sense
2
V
OUT2
Sense
1
V
OUT1
s
Oscillator has Precise
Duty Cycle
Limit and Frequency
Control
s
500kHz Current Mode
Operation
s
Automatic Feed Forward
Compensation
s
Separate Latching PWMs
for Cycle-By-Cycle
Current Limiting
s
Internally Trimmed
Reference with
Undervoltage Lockout
s
Switchable Second
Output
s
Two High Current Totem
Pole Outputs
s
Input Undervoltage
Lockout with Hysteresis
Package Options
16L PDIP & SO Wide
CS5651
High Performance Dual Channel
Current Mode Controller with ENABLE
1
SYNC
2
3
4
5
6
7
8
C
T
R
T
V
FB1
COMP
1
SENSE
1
V
OUT1
Gnd
16
15
14
13
12
11
10
9
V
CC
V
REF
ENABLE
2
V
FB2
COMP
2
Sense
2
V
OUT2
Pwr Gnd
CS5651
Description
The CS5651 is a high performance,
fixed frequency, dual current mode
controller specifically designed for
Off-Line and DC to DC converter
applications. It offers the designer a
cost effective solution with minimal
external components. This integrat-
ed circuit features a unique oscilla-
tor for precise duty cycle limit and
frequency control, a temperature
compensated reference, two high
gain error amplifiers, two current
sensing comparators, and two high
current totem pole outputs ideally
suited for driving power MOSFETs.
One of the outputs, V
OUT2
is switch-
able via the ENABLE
2
pin.
Also included are protective fea-
tures consisting of input and refer-
ence undervoltage lockouts, each
with hysteresis; cycle-by-cycle cur-
rent limiting; and a latch for single
pulse metering of each output.
The CS5651 is pin compatible with
the MC34065H.
Block Diagram
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
A Company
Rev. 3/9/99
2
Electrical Characteristics: V
CC
= 15V, R
T
= 8.2k, C
T
= 3.3nF, 0C T
A
70C [Note 2], unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Absolute Maximum Ratings
Output Current, Source or Sink (Note 1) ......................................................................................................................400mA
Output Energy (capacitive load per cycle) .......................................................................................................................5.0J
Current Sense, Enable and Voltage ......................................................................................................................-0.3 to +5.5V
Feedback Inputs
Sync Input
High State (Voltage).............................................................................................................................................5.5V
Low State (Reverse Current)..........................................................................................................................-5.0mA
Error Amp Output Sink Current......................................................................................................................................10mA
Storage Temperature Range ................................................................................................................................-65 to +150C
Operating Junction Temperature...................................................................................................................................+150C
Lead Temperature Soldering
Wave Solder (through hole styles only)..........................................................................10 sec. max, 260C peak
Reflow (SMD styles only)...........................................................................60 sec. max above 183C, 230C peak
CS5651
s
Reference Section
Reference Output Voltage,
I
OUT
= 1.0mA, T
J
= 25C
4.9
5.0
5.1
V
V
REF
Line Regulation
11V V
CC
15V
2.0
20.0
mV
Load Regulation
1.0mA I
OUT
10mA
3.0
25.0
mV
Total Output Variation over
4.85
5.15
V
Line, Load and Temperature
Output Short Circuit Current
30
100
mA
s
Oscillator and PWM Sections
Total Frequency Variation
11V V
CC
15V, T
low
T
A
T
high
46.5
49.0
51.5
kHz
over Line and Temperature
Frequency Change with
11V V
CC
15V
0.2
1.0
%
Voltage
Duty Cycle at each Output
Maximum
46.0
49.5
52.0
%
SYNC Current
High State V
IN
= 2.4V
170
250
A
Low State V
IN
= 0.8V
80
160
s
Error Amplifiers
Voltage Feedback Input
V
OUT
= 2.5V
2.42
2.50
2.58
V
Input Bias Current
V
FB
= 5.0V
-0.1
-1.0
A
Open-Loop Voltage Gain
2.0V V
OUT
4.0V
65
100
dB
Unity Gain Bandwidth
T
J
= 25C (Note 5)
0.7
1.0
MHz
Power Supply Rejection Ratio V
CC
= 11V to 15V
60
90
dB
Output Current
Source V
OUT
= 3.0V, V
FB
= 2.3V
-0.45
-1.00
mA
Sink V
OUT
= 1.2V, V
FB
= 2.7V
2.00
12.00
mA
Output Voltage Swing
High State R
L
= 15k to ground,
V
FB
= 2.3V
5.0
6.2
V
Low State R
L
= 15k to V
REF
,
V
FB
= 2.7V
0.8
1.1
V
3
CS5651
Electrical Characteristics: V
CC
= 15V, R
T
= 8.2k, C
T
= 3.3nF, 0C T
A
70C [Note 2], unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Note 1: Maximum package power dissipation limits must be
observed.
Note 2: Low duty cycle pulse techniques are used during test to
maintain junction temperature as close to ambient as
possible.
Note 3: This parameter is measured at latch trip point with
V
FB
= 0V.
Note 4: Comparator gain is defined as:
AV=
Note 5: These parameters are guaranteed by design but not
100% tested in production.
V Compensation
V Current Sense
s
Current Sense Section
Current Sense Input
(Notes 3 and 4)
2.75
3.00
3.25
V/V
Voltage Gain
Maximum Current Sense
(Note 3)
0.9
1.0
1.1
V
Input Threshold
Input Bias Current
-2.0
-30.0
A
Propagation Delay
Current Sense Input to Output (Note 5)
150
300
ns
s
Output 2 Enable Pin
Enable Pin Voltage
V
High State
ENABLE
2
enabled
3.5
V
REF
V
Low State
ENABLE
2
disabled
0.0
1.5
V
Low State Input Current
V
IL
= 0V
100
250
400
A
s
Drive Outputs
Output Voltage
Low State
I
SINK
= 20mA
0.1
0.4
V
I
SINK
= 200mA
1.6
2.5
V
High State
I
SOURCE
= 20mA
13.0
13.5
V
I
SOURCE
= 200mA
12.0
13.4
V
Output Voltage with
V
CC
= 6.0V, I
SINK
= 1.0mA
0.1
1.1
V
UVLO Activated
Output Voltage Rise Time
C
L
= 1.0nF (Note 5)
28
150
ns
Output Voltage Fall Time
C
L
= 1.0nF (Note 5)
25
150
ns
s
Undervoltage Lockout Section
Start-Up Threshold
13
14
15
V
Minimum Operating Voltage
9.0
10.0
11.0
V
Hysteresis
4.0
V
s
Total Device
Start-Up Current
V
CC
= 12V
0.6
1.0
mA
Operating Current
(Note 2)
20
25
mA
4
CS5651
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
Typical Performance Characteristics
100pF
1.0nF
10k
30k
50k
100k
300k
500k
1.0M
f
OSC
OSCILLATOR FREQUENCY (Hz)
4.0
6.0
8.0
10
12
14
16
R
T
TIMING RESIST
OR (K
)
T
A
=25
C
2.2nF
3.3nF
5.0nF
C
T
=10nF
V
CC
=
15V
220pF
330pF
500pF
10k
30k
50k
100k
300k
500k
1.0M
f
OSC
OSCILLATOR FREQUENCY (Hz)
38
40
42
44
46
48
50
MAXIMUM DUTY
CYCLE (%)
V
CC
= 15V
R
T
= 4.0k
to 16k
C
L
= 15pF
T
A
= 25
C
Max. Output Duty Cycle vs. Oscillator Frequency
Timing Resistor vs. Oscillator Frequency
10k
100k
1.0k
10k
100k
1.0M
10M
f, FREQUENCY (Hz)
-20
0
20
40
60
80
100
A
VOL
, OPEN-LOOP
VOL
T
AGE GAIN (dB)
V
CC
= 15V
V
O
= 1.5V TO 2.5V
R
L
= 100k
T
A
= 25
C
GAIN
PHASE
180
150
120
90
60
30
0
Phase Margin (DEGREES)
0
1.0
2.0
3.0
4.0
5.0
7.0
ERROR AMP OUTPUT VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1.0
1.2
Vth, CURRENT
SENSE
INPUT
THRESHHOLD
(V)
6.0
V
CC
= 15V
T
A
= 125
C
T
A
= 25
C
T
A
= -55
C
Current Sense Input Threshold vs. Error
Amp Output Voltage
Error Amp Open-Loop Gain & Phase vs. Frequency
16 L PDIP & SO Wide
1
SYNC
A positive going pulse applied to this input will synchronize the
oscillator. A DC voltage within the range of 2.4V to 5.5V will
inhibit the oscillator.
2
C
T
Timing capacitor C
T
connects pin to ground setting oscillator
frequency.
3
R
T
Resistor R
T
connects to ground setting the charge current for C
T
.
Its value must be between 4.0k and 16k.
4
V
FB1
The inverting input of error amplifier 1. Normally it is connect-
ed to the switching power supply output.
5
COMP
1
The output of error amplifier 1, for loop compensation.
6
Sense
1
Output 1 pulse by pulse current limit.
7
V
OUT1
Drives the power switch at output 1.
8
Gnd
Logic ground
9
Pwr Gnd
Power ground. Power device return is connected to this pin.
10
V
OUT2
Drives the power switch at output 2.
11
Sense
2
Output 2 pulse by pulse current limit.
12
COMP
2
Output of error amplifier 2, for loop compensation.
13
V
FB2
Inverting input of error amplifier 2. Normally it is connected to
the switching power supply output.
14
ENABLE
2
Output 2 disable. A logic low at this pin disables V
OUT2
.
15
V
REF
5.0V reference output. It can source current in excess of 30mA.
16
V
CC
The positive supply of the IC. The minimum operating voltage
range after start-up is 9V.
5
The CS5651 is a high performance, fixed frequency, dual
channel current mode PWM controller for Off-Line and
DC to DC converter applications. Each channel contains a
high gain error amplifier, current sensing comparator,
pulse width modulator latch, and totem pole output driv-
er. The oscillator, reference, and undervoltage lockout cir-
cuits are common to both channels.
The oscillator has both precise frequency and duty cycle
control. The oscillator frequency is programmed by the
timing components R
T
and C
T
. Capacitor C
T
is charged
and discharged by an equal magnitude internal current
source and sink, that generates a symmetrical 50 percent
duty cycle waveform at C
T
. The oscillator peak and valley
thresholds are 3.5V and 1.6V respectively. The source/
sink current is controlled by resistor R
T
. For proper opera-
tion over temperature range R
T
's value should be between
4.0k to 16k.
As C
T
charges and discharges, an internal blanking pulse
is generated that alternately drives the inputs of the upper
and lower NOR gates high. This, in conjunction with a
precise amount of delay time introduced into each chan-
nel, produces well defined non-overlapping output duty
cycles. Output 2 is enabled while C
T
is charging, and
Output 1 is enabled during the discharge. Even at 500kHz,
each output is capable of approximately 44% duty cycle,
making this controller suitable for high frequency power
conversion applications.
In noise sensitive applications it may be necessary to syn-
chronize the converter with an external system clock. This
can be accomplished by applying an external clock signal.
For reliable synchronization, the oscillator frequency
should be set about 10% slower than the clock frequency.
The rising edge of the clock signal applied to SYNC, termi-
nates the charging of C
T
and V
OUT2
conduction. By tailor-
ing the clock waveform symmetry, accurate duty cycle
clamping of either output can be achieved.
Each channel contains a fully-compensated error amplifier
with access to the output and inverting input. The amplifi-
er features a typical dc voltage gain of 100 dB, and a unity
gain bandwidth of 1.0 MHz with 71 degrees of phase mar-
gin. The non-inverting input is internally biased at 2.5V.
The converter output voltage is typically divided down
and monitored by the inverting input through a resistor
divider. The maximum input bias current is -1.0 A which
will cause an output voltage error that is equal to the
product of the input bias current and the equivalent input
divider resistance.
Its output voltage is offset by two diode drops (1.4V) and
divided by three before it connects to the inverting input
of the current sense comparator. This guarantees that both
Operating Description
CS5651
Typical Performance Characteristics: continued
0
20
40
60
80
100
120
I
ref
, REFERENCE SOURCE CURRENT (mA)
-24
-20
-16
-12
-8.0
-4.0
0
V
REF
, REFERENCE
V
oltage (mV)
V
CC
= 15V
T
A
= 55
C
T
A
= 125
C
T
A
=
25
C
-55
-25
0
25
50
75
100
125
T
A
, AMBIENT TEMPERATURE (
C)
I
SC
, REFERENCE
SHOR
T
CIRCUIT
CURRENT
(mA)
120
100
80
60
Reference Short Circuit Current vs. Temperature
Reference Voltage Change vs. Source Current
SOURCE SATURATION
(LOAD TO GROUND)
V
CC
=15V
80
S PULSED LOAD
120Hz RATE
T
A
=25
C
T
A
= 55
C
T
A
= 55
C
T
A
=25
C
SINK
SATURATION
(LOAD TO V
CC
)
GND
0
200
400
600
800
OUTPUT LOAD CURRENT (mA)
V
sat
, OUTPUT
SA
TURA
TION VOL
T
AGE (V)
V
CC
0
-1.0
-2.0
2.0
1.0
0
0
4.0
8.0
12
16
20
V
CC,
SUPPLY VOLTAGE (V) - CS-5651
0
8.0
16
24
32
R
T
=8.2k
C
T
=3.3nF
V
FB
1, 2=0V
CURRENT SENSE 1, 2=0V
T
A
=25
C
I
CC,
SUPPL
Y
CURRENT
(mA)
Supply Current vs. Supply Voltage
Output Saturation Voltage vs. Load Current
Oscillator
Error Amplifier
6
outputs are disabled when the error amplifier output is at
its lowest state (V
OUT(LOW)
). This occurs when the power
supply is operating at light or no-load conditions, or at the
beginning of a soft-start interval.
The minimum allowable error amplifier feedback resis-
tance is limited by the amplifier's source current capability
(0.5 mA) and the output voltage (V
OUT(High)
) required to
reach the current sense comparator 1.0V clamp level with
the error amplifier inverting input at ground. This condi-
tion happens during initial system start up or when the
sensed output is shorted:
R
F(min)
= 8.8k
The CS5651 operates as a current mode controller. Output
switch conduction is initiated by the oscillator and termi-
nated when the peak inductor current reaches the thresh-
old level established by the error amplifier output. The
error signal controls the peak inductor current on a cycle-
by-cycle basis. The current sense comparator-PWM Latch
combination ensures that only a single pulse appears at the
output during any given oscillator cycle. The current is
converted to a voltage by connecting sense resistor R
Sense
in
series with the source of output switch Q1 and ground.
This voltage is monitored via the Sense
1,2
pins and com-
pared to a voltage derived from the error amp output. The
peak current under normal operating conditions is con-
trolled by the voltage at COMP where:
I
pk
=
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage is too
high. Under these conditions, the current sense comparator
threshold will be internally clamped to 1.0V. Therefore the
maximum peak switch current is:
I
pk(max)
=
Erratic operation due to noise pickup can result if there is
an excessive reduction of the I
pk(max)
clamp voltage.
A narrow spike on the leading edge of the current wave-
form can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. The addition of an RC filter on the current sense
input reduces this spike to an acceptable level.
Two undervoltage lockout comparators have been incor-
porated to guarantee that the IC is fully functional before
the output stages are enabled. V
CC
and the reference out-
put V
REF
are monitored by separate comparators. Each
comparator has built-in hysteresis to prevent erratic output
behavior as their respective thresholds are crossed. The
V
CC
comparator upper and lower thresholds are 14V and
10V for the CS5651. The V
REF
comparator disables the out-
puts until the internal circuitry is functional. This compara-
tor has upper and lower thresholds of 3.6V and 3.4V. The
guaranteed minimum operating voltage after turn-on is
11V for CS5651.
Each channel contains a single totem-pole output stage
specifically designed for driving a power MOSFET. The
outputs have up to 1.0A peak current capability and have
a typical rise and fall time of 28ns with a 1.0nF load.
Internal circuitry has been added to keep the outputs in
active pull-down mode whenever undervoltage lockout is
active. An external pull-down resistor is not needed.
Cross-conduction current in the totem-pole output stage
has been minimized for high speed operation. The average
added power due to cross-conduction with V
CC
= 15V is
only 60mW at 500kHz.
Although the outputs were optimized for MOSFET's, they
can easily supply the negative base current required by
bipolar NPN transistors for enhanced turn-off. Because the
outputs do not contain internal current limiting circuitry,
an external series resistor may be required to prevent the
peak output current from exceeding the 1.0A maximum
rating. The sink saturation voltage (V
OL
) is less than 0.4V at
100mA.
A separate Power Ground pin is provided and will signifi-
cantly reduce the level of switching transient noise
imposed on the control circuitry. This becomes particularly
important when the I
pk(max)
clamp level is reduced.
This input is used to switch V
OUT2
. V
OUT1
can be used to
control circuitry that runs continuously; e.g. volatile mem-
ory, the system clock, or a remote controlled receiver. The
V
OUT2
output can control the high power circuitry that can
be turned off when not needed.
The 5.0V bandgap reference is trimmed to 2.0% tolerance.
The reference has short circuit protection and is capable of
sourcing 30mA for powering any additional external cir-
cuitry.
High frequency circuit layout techniques are imperative to
prevent pulse-width jitter. This is usually caused by exces-
sive noise pick-up imposed on the current sense or voltage
feed-back inputs. Noise immunity can be improved by
lowering circuit impedances at these points. The printed
circuit board layout should contain a ground plane with
low current signal and high current switch and output
grounds returning on separate paths back to the input fil-
1.0V
R
Sense
V
COMP
1.4V
3R
Sense
(3 x 1.0V) + 1.4V
0.5mA
Operating Description: continued
CS5651
Outputs and Power Ground
ENABLE
2
Voltage Reference
Undervoltage Lockout
Current Sense Comparator and PWM Latch
Design Considerations
7
ter capacitor. Ceramic bypass capacitors (0.1F) connected
directly to V
CC
and V
REF
may be required to improve noise
filtering. This provides a low impedance path for filtering
the high frequency noise. All high current loops should be
kept as short as possible using heavy copper runs. The
error amp compensation circuitry and the converter out-
put voltage-divider should be located close to the IC and
as far as possible from the power switch and other noise
generating components.
Operating Description: continued
CS5651
SYNC
Capacitor C
T
Latch 1
"Set" Input
COMP
1
Sense
1
V
OUT1
Latch 1
"Reset" Input
ENABLE
2
Latch 2
"Set" Input
COMP
2
Sense
2
Latch 2
"Reset" Input
V
OUT2
0V
Timing Diagram
+
-
+
-
+
-
+
+
+
+
-
+
-
+
-
R
T
C
T
V
FB
1
Reference
Regulator
V
REF
UVLO
3.4V
14V
2.5V
R
R
20k
V
REF
Sync
1.0V
REF
2R
1.0V
250
A
R
1.0mA
2R
Error
Amp 2
COMP
1
ENABLE
2
V
FB
2
COMP
2
Gnd
Pwr Gnd
R
1.0V
Current Sense
Comparator 2
Current Sense
Comparator 1
R
S
Q
R
S
R
PWM
Latch 2
PWM
Latch 1
V
CC
VIN
V
OUT
1
V
OUT
2
Sense
1
Q1
Q2
RSense1
Sense
2
RSense2
-
+
-
Error
Amp 1
V
OUT
1
V
OUT
2
C
OUT
2
C
OUT
1
5.0V
Q
Oscillator
Internal
Bias
CF1 +
L1
D1
L2
D2
+
+
CF2
R
FB
1
R
FB
2
R
FB
3
R
FB
4
V
OUT
2
V
OUT
1
Dual Boost Regulator
V
CC
UVLO
+
Typical Application Diagram
Part Number
Description
CS5651GN16
16L PDIP
CS5651GDW16
16L SO Wide
CS5651GDWR16
16L SO Wide (Tape & Reel)
8
Thermal Data
16 Lead
16 Lead
PDIP SO Wide
R
JC
typ
42
23
C/W
R
JA
typ
80
105
C/W
D
Lead Count
Metric
English
Max
Min
Max
Min
16 Lead PDIP
19.69
18.67
.775
.735
16 Lead SO Wide
10.50
10.10
.413
.398
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES)
Ordering Information
PACKAGE THERMAL DATA
Rev. 3/9/99
CS5651
1999 Cherry Semiconductor Corporation
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
Plastic DIP (N); 300 mil wide
0.39 (.015)
MIN.
2.54 (.100) BSC
1.77 (.070)
1.14 (.045)
D
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.
.203 (.008)
.356 (.014)
REF: JEDEC MS-001
3.68 (.145)
2.92 (.115)
8.26 (.325)
7.62 (.300)
7.11 (.280)
6.10 (.240)
.356 (.014)
.558 (.022)
Surface Mount Wide Body (DW); 300 mil wide
1.27 (.050) BSC
7.60 (.299)
7.40 (.291)
10.65 (.419)
10.00 (.394)
D
0.32 (.013)
0.23 (.009)
1.27 (.050)
0.40 (.016)
REF: JEDEC MS-013
2.49 (.098)
2.24 (.088)
0.51 (.020)
0.33 (.013)
2.65 (.104)
2.35 (.093)
0.30 (.012)
0.10 (.004)
PDF 
ZIP