5V, 100mA Low Dropout Linear Regulator
with Watchdog, RESET, & Wake Up
The CS8151C is a precision 5V, 100mA
micro-power voltage regulator with
very low quiescent current (400A typ-
ical at 200A load). The 5V output is
accurate within 1% and supplies 100
mA of load current with a typical
dropout voltage of 400mV.
Microprocessor control logic includes
Watchdog, Wake Up and
. This
unique combination of low quiescent
current and full microprocessor con-
trol makes the CS8151C ideal for use in
battery operated, microprocessor con-
trolled equipment.
The CS8151C Wake Up function brings
the microprocessor out of Sleep mode.
The microprocessor in turn, signals its
Wake Up status back to the CS8151C
by issuing a Watchdog signal.
The Watchdog logic function monitors
an input signal (WDI) from the micro-
processor. The CS8151C responds to
the falling edge of the Watchdog signal
which it expects at least once during
each wake-up period. When the cor-
rect Watchdog signal is received, a
falling edge is issued on the wake-up
signal line.
is independent of V
IN
and
operates correctly to an output voltage
as low as 1V. A
signal is issued
in any of three situations. During
power up the
is held low until
the output voltage is in regulation.
During operation if the output voltage
shifts below the regulation limits, the
toggles low and remains low
until proper output voltage regulation
is restored. And finally, a
signal
is issued if the regulator does not
receive a Watchdog signal within the
Wake Up period.
The
pulse width, Wake Up sig-
nal frequency, and Wake Up delay
time are all set by one external capaci-
tor C
Delay
.
The regulator is protected against
short circuit, over voltage, and thermal
runaway conditions. The device can
withstand 74 volt load dump tran-
sients, making it suitable for use in
automotive environments.
RESET
RESET
RESET
RESET
RESET
RESET
RESET
1
Features
Error
Amplifier
Thermal
Shutdown
V
IN
Bandgap
Reference
+ -
Current Limit
Sense
Current Source
(Circuit Bias)
RESET
Over
Voltage
Shutdown
Timing
Circuit
WATCHDOG
Circuit
Falling Edge
Detector
Sense
V
OUT
Gnd
Delay
WDI
RESET
Circuit
V
OUT
V
OUT
WAKE UP
WAKE UP
Circuit
s
5V 1% / 100 mA Output
Voltage
s
Micropower Compatible
Control Functions:
Wake Up
Watchdog
s
Low Dropout Voltage:
400mV @ 100mA
s
Low Sleep Mode Quiescent
Current (400A typ)
s
Protection Features:
Thermal Shutdown
Short Circuit
74V Load Dump
Reverse Transient (-50V)
RESET
Package Options
8 Lead PDIP
CS8151C
1
V
IN
WDI
WAKE UP
RESET
Delay
N/C
Gnd
V
OUT
CS8151C
Description
Block Diagram
A Company
Rev. 3/17/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Absolute Maximum Ratings
Power Dissipation.............................................................................................................................................Internally Limited
Output Current (V
OUT
,
, Wake Up) ...................................................................................................Internally Limited
Reverse Battery..........................................................................................................................................................................-15V
Maximum Load Dump Transient .........................................................................................................................................+74V
Maximum Negative Transient (t<2ms) .................................................................................................................................-50V
ESD Susceptibility (Human Body Model)..............................................................................................................................2kV
ESD Susceptibility (Machine Model).....................................................................................................................................200V
Logic Inputs/Outputs ................................................................................................................................................-0.3V to +6V
Storage Temperature Range ................................................................................................................................-55C to +150C
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260C peak
RESET
CS8151C
Electrical Characteristics: T
A
= 0C to 70C, 0C T
J
125C, 6V V
IN
26V, I
OUT
= 100A to 100mA,
C2 = 47F (ESR < 8), C
Delay
= 0.1F (unless otherwise noted)
s Output Section
Output Voltage, V
OUT
9V < V
IN
< 16V
4.95
5.00
5.05
V
6V < V
IN
< 26V, 0 < I
OUT
< 100mA
4.90
5.00
5.10
V
Dropout Voltage (V
IN
- V
OUT
)
I
OUT
= 100mA
400
600
mV
I
OUT
= 100A
100
150
mV
Load Regulation
V
IN
= 14V, 100A < I
OUT
< 100mA
10
50
mV
Line Regulation
I
OUT
= 1mA, 6V < V
IN
< 26V
10
50
mV
Ripple Rejection
7V < V
IN
< 17V @ f = 120Hz,
60
75
dB
I
OUT
= 100mA
Current Limit
V
OUT
= 4.5V
100
250
mA
Thermal Shutdown
150
180
210
C
Overvoltage Shutdown
V
OUT
< 1V
50
56
62
V
Quiescent Current
I
OUT
= 200A (Sleep)
0.40
0.75
mA
I
OUT
= 50mA
4
mA
I
OUT
= 100mA (Wake Up)
12
20
mA
Reverse Current
V
OUT
= 5V, V
IN
= 0V
1.0
1.5
mA
s
Threshold High (RTH)
RTH V
OUT
Increasing
V
OUT
- 0.3
V
OUT
- 0.04
V
Threshold Low (RTL)
RTL V
OUT
Decreasing
4.50
4.70
4.91
V
Hysteresis
RTH RTL
150
200
250
mV
Output
LOW
1V < V
OUT
< RTL, I
OUT
= 25A
0.2
0.8
V
HIGH
I
OUT
= 25A, V
OUT
> RTH
3.8
4.2
5.1
V
Current Limit
= 0V, V
OUT
> V
RTH
(sourcing)
0.025
0.50
1.30
mA
= 5V, V
OUT
> 1V (sinking)
0.1
12
80
mA
Delay Time
POR Mode
3
5
7
ms
RESET
RESET
RESET
Package Lead Description
Package Lead #
Lead Symbol
Function
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s Watchdog Input
Threshold
HIGH
1.4
2.0
V
LOW
0.8
1.3
V
Hysteresis
25
100
mV
Input Current
0 < WDI < 6V
-10
0
+10
A
Pulse Width
50% WDI falling edge to
5
s
50% WDI rising edge and
50% WDI rising edge to 50%
WDI falling edge (see Figure 1)
s Wake Up Output
Wake Up Period
see Figure 1a
30
40
50
ms
Wake Up Duty Cycle nominal
see Figure 1c
40
50
60
%
HIGH to Wake Up
50%
rising edge to
15
20
25
ms
Rising Delay Time
50% Wake Up edge
(see Figure 1)
Wake Up Response
50% WDI falling edge to
2
10
s
to Watchdog Input
50% Wake Up falling edge
Wake Up Response
50%
falling edge to
2
10
s
to
50% Wake Up falling edge
V
OUT
= 5V
4.5V
Output
LOW
I
OUT
= 25A(sinking)
0.2
0.8
V
HIGH
I
OUT
= 25A(sourcing)
3.8
4.2
5.1
V
Current Limit
Wake Up = 5V
0.025
1.00
7.00
mA
Wake Up = 0V
.05
3.50
mA
RESET
RESET
RESET
RESET
8 L PDIP
1
V
IN
Supply voltage to the IC.
2
WDI
CMOS/TTL compatible input lead. The watchdog function monitors
the falling edge of the incoming signal.
3
Wake Up
CMOS/TTL compatible output consisting of a continuously generated
signal used to Wake Up the microprocessor from sleep mode.
4
CMOS/TTL compatible output lead
goes low whenever V
OUT
drops by more than 6% from nominal, or during the absence of a cor-
rect watchdog signal.
5
Delay
Input lead from timing capacitor for
and Wake Up signal.
7
Gnd
Ground Connection
8
V
OUT
Regulated output voltage 5V 2%.
RESET
RESET
RESET
3
CS8151C
Electrical Characteristics: T
A
= 0C to 70C, 0C T
J
125C, 6V V
IN
26V, I
OUT
= 100A to 100mA,
C2 = 47F (ESR < 8), C
Delay
= 0.1F (unless otherwise noted)
4
______
RESET
WAKE UP
WDI
V
OUT
POWER DOWN
POR
POR
RTL
WATCHDOG Pulse Width
WAKE UP period
Timing Diagrams
Figure 1c. Power Down and Restart Sequence
______
RESET
WAKE UP
WDI
V
OUT
VIN
POR
______
RESET HIGH
to WAKE UP
DELAY TIME
______
RESET HIGH
to WAKEUP
DELAY TIME
______
RESET delay time
WAKE UP
period
Figure 1b. Error Condition: Watchdog remains LOW and a
is issued
RESET
______
RESET
WAKE UP
WDI
V
OUT
-
POR
V
IN
______
RESET High
to Wakeup
Delay Time
Power Up
Sleep Mode
Normal Operation with varying WATCHDOG Signal
WAKE UP Duty Cycle = 50%
Figure 1a. Power Up, Sleep Mode and Normal Operation
CS8151C
5
To reduce the drain on the battery a system can go into a
low current consumption mode when ever its not per-
forming a main routine. The Wake Up signal is generated
continuously and is used to interrupt a microcontroller
that is in sleep mode. The nominal output is a 5 volt
square wave with a duty cycle of 50% at a frequency that
is determined by a timing capacitor, C
Delay
.
When the microprocessor receives a rising edge from the
Wake Up output, it must issue a watchdog pulse and
check its inputs to decide if it should resume normal oper-
ations or remain in the sleep mode.
The first falling edge of the watchdog signal causes the
Wake Up to go low within 2s (typ) and remain low until
the next Wake Up cycle (see Figure 2). Other watchdog
pulses received within the same cycle are ignored (Figure
1).
During power up,
is held low until the output volt-
age is in regulation. During operation, if the output volt-
age shifts below the regulation limits, the RESET toggles
low and remains low until proper output voltage regula-
tion is restored. After the
delay,
returns
high.
The Watchdog circuitry continuously monitors the input
watchdog signal (WDI) from the microprocessor. The
absence of a falling edge on the Watchdog input during
one Wake Up cycle will cause a
pulse to occur at
the end of the Wake Up cycle. (see Figure 1b).
The Wake Up output is pulled low during a
regardless of the cause of the
. After the
returns high, the Wake Up cycle begins again (see Figures
1b).
The
pulse width, Wake Up signal frequency and
high to Wake Up delay time are all set by one
external capacitor C
Delay
.
Wake Up period=(4x10
5
)C
Delay
Delay Time=(5x10
4
)C
Delay
HIGH to Wake Up Delay Time =(2x10
5
)C
Delay
Capacitor temperature coefficient and tolerance as well as the
tolerance of the CS8151C must be taken into account in order
to get the correct system tolerance for each parameter.
Figure 2. Wake Up response to WDI
Figure 3. Wake Up response to
(Low Voltage)
RESET
WAKE UP
Response to
______
RESET
______
RESET
WAKE UP
WAKE UP
Response to
WDI
WAKE UP
WDI
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
Dropout Voltage:
The input-output voltage differential at which the cir-
cuit ceases to regulate against further reduction in
input voltage. Measured when the output voltage has
dropped 100mV from the nominal value obtained at
14V input, dropout voltage is dependent upon load
current and junction temperature.
Input Voltage:
The DC voltage applied to the input terminals with
respect to ground.
Line Regulation:
The change in output voltage for a change in the
input voltage. The measurement is made under con-
ditions of low dissipation or by using pulse tech-
niques such that the average chip temperature is not
significantly affected.
Load Regulation:
The change in output voltage for a change in load
current at constant chip temperature.
Quiescent Current:
The part of the positive input current that does not
contribute to the positive load current. The regulator
ground lead current.
Ripple Rejection:
The ratio of the peak-to-peak input ripple voltage to
the peak-to-peak output ripple voltage.
Current Limit:
Peak current that can be delivered to the output.
Definition of Terms
Circuit Description
CS8151C
Functional Description
The output stage is protected against overvoltage, short
circuit and thermal runaway conditions (see Figure 4).
Figure 4: Typical Circuit Waveforms for Output Stage Protection.
If the input voltage rises above 56V (e.g. load dump), the
output shuts down. This response protects the internal cir-
cuitry and enables the IC to survive unexpected voltage
transients.
Should the junction temperature of the power device
exceed 180C (typ) the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
The output or compensation capacitor C
2
(see Figure 5)
helps determine three main characteristics of a linear regu-
lator: start-up delay, load transient response and loop sta-
bility.
Figure 5. Test and application circuit showing output compensation.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum
or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instabili-
ty. The aluminum electrolytic capacitor is the least expen-
sive solution, but, if the circuit operates at low tempera-
tures (-25C to -40C), both the value and ESR of the
capacitor will vary considerably. The capacitor manufac-
turers data sheet usually provide this information.
The value for the output capacitor C
2
shown in the test
and applications circuit should work for most applica-
tions, however it is not necessarily the optimized solution.
To determine an acceptable value for C
2
for a particular
application, start with a tantalum capacitor of the recom-
mended value and work towards a less expensive
alternative part.
Step 1:
Place the completed circuit with a tantalum capac-
itor of the recommended value in an environmental cham-
ber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade
box outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2:
With the input voltage at its maximum value,
increase the load current slowly from zero to full load
while observing the output for any oscillations. If no oscil-
lations are observed, the capacitor is large enough to
ensure a stable design under steady state conditions.
Step 3:
Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that
cause the greatest oscillation. This represents the worst
case load conditions for the regulator at low temperature.
Step 4
: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage conditions.
Step 5:
If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger stan-
dard capacitor value.
Step 6:
Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7:
Remove the unit from the environmental chamber
and heat the IC with a heat gun. Vary the load current as
instructed in step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for
the tolerance of the capacitor and any variations in regula-
tor performance. Most good quality aluminum electrolytic
capacitors have a tolerance of 20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low tem-
peratures. The ESR of the capacitor should be less than
50% of the maximum allowable ESR found in step 3 above.
The maximum power dissipation for a single output regu-
lator (Figure 6) is:
P
D(max)
= {V
IN(max)
V
OUT(min)
}I
OUT(max)
+ V
IN(max)
I
Q
(1)
where:
V
IN(max)
is the maximum input voltage,
V
OUT(min)
is the minimum output voltage,
I
OUT(max)
is the maximum output current for the applica-
tion, and
I
Q
is the quiescent current the regulator consumes at
I
OUT(max)
.
Calculating Power Dissipation
in a Single Output Linear Regulator
CS8151C
V
OUT
R
RST
C
2
**
10
mF
V
IN
C
1
*
0.1
mF
RESET
Stability Considerations
I
OUT
V
OUT
V
IN
Load
Dump
Short
Circuit
Thermal
Shutdown
> 30V
Output Stage Protection
CS8151C
Application Notes
*C
1
required if regulator is located
far from the power supply filter.
**C
2
required for stability.
6
7
Once the value of P
D(max)
is known, the maximum permis-
sible value of R
QJA
can be calculated:
R
QJA
=
(2)
The value of R
QJA
can then be compared with those in
the package section of the data sheet. Those packages with
R
QJA
's less than the calculated value in equation 2 will
keep the die temperature below 150C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and
the outside environment will have a thermal resistance.
Like series electrical resistances, these resistances are
summed to determine the value of R
QJA
:
R
QJA
= R
QJC
+ R
QCS
+ R
QSA
(3)
where:
R
QJC
= the junctiontocase thermal resistance,
R
QCS
= the casetoheatsink thermal resistance, and
R
QSA
= the heatsinktoambient thermal resistance.
R
QJC
appears in the package section of the data sheet. Like
R
QJA
, it too is a function of package type. R
QCS
and R
QSA
are functions of the package type, heatsink and the inter-
face between them. These values appear in heat sink data
sheets of heat sink manufacturers.
150C - T
A
P
D
Application Diagram
CS8151C
Heat Sinks
V
IN
Smart
Regulator
V
OUT
I
OUT
I
IN
I
Q
Control
Features
}
Figure 6. Single output regulator with key performance parameters
labeled.
C
Delay
C
Delay
WAKE UP
______
RESET
WDI
V
OUT
V
IN
C
2
V
CC
I/O
I/O
BATTERY
Microprocessor
CS8151C
______
RESET
C
1
Gnd
Application Diagram
D
Lead Count
Metric
English
Max
Min
Max Min
8L PDIP
10.16
9.02 .400 .355
8
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES)
Ordering Information
PACKAGE THERMAL DATA
Rev. 3/17/99
Part Number
Description
CS8151CGN8
8 Lead PDIP
CS8151C
1999 Cherry Semiconductor Corporation
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
Thermal Data
8 Lead PDIP
R
QJC
typ
52
C/W
R
QJA
typ
100
C/W
Plastic DIP (N); 300 mil wide
0.39 (.015)
MIN.
2.54 (.100) BSC
1.77 (.070)
1.14 (.045)
D
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.
.203 (.008)
.356 (.014)
REF: JEDEC MS-001
3.68 (.145)
2.92 (.115)
8.26 (.325)
7.62 (.300)
7.11 (.280)
6.10 (.240)
.356 (.014)
.558 (.022)
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