FEATURES
Low Voltage Operation
- Dual read V
CC
ranges: 2.7 V to 3.6 V or 4.5 V to
5.5 V
- Program/Erase voltage: V
CC
- 2.7 V to 3.6 V and
V
PP
- 11.5 V to 12.5 V
High Performance Read
- 70 ns access time
Electrical Chip Erase and Byte Program
Using EPROM Programmer
- Maximum 20 s/byte programming
- Maximum 100 ms chip erase
- Do not require UV erase
Low Power Consumption
- Typical 5 mA active read current
- Typical 18 A CMOS standby current
Excellent Product Reliablity
- Guarantee minimum 1,000 program/erase cycles
- Minimum 20 years data retention
JEDEC Standard Byte-wide Flash Memory
Pin-out
Industrial Standard Packaging
- 32-pin PLCC
- 32-pin PDIP
- 32-pin VSOP
GENERAL DESCRIPTION
The Pm37LV512 is a 512 Kbit, Multiple-Cycle-Programmable Read-Only-Memory (MCP ROM) organized as 65,563
bytes of 8 bits each. The program and erase operation of device can be done on EPROM programmers by applying
3.0 Volt V
CC
and 12.0 Volt V
PP
to A9 and/or OE# pin. This eliminates the need of a UV-Source for erase operation
such as EPROM device. The read operation of device can be in 2.7 Volt to 3.6 Volt or 4.5 Volt - 5.5 Volt range
compatible to either 3.0 Volt or 5.0 Volt systems. The dual read operation ranges can greatly increase application
flexibility for users.
The device has a standard microprocessor interface as well as JEDEC single-power-supply Flash compatible pin-
out. For applications that do not require in-system-programming (ISP) function for firmwire upgrade, the Pm37LV512
offers a direct cost reduction path for Flash memory, i.e. Pm39LV512, without modifying the schematic and board
layout of system.
The Pm37LV512 is manufactured on PMC's advanced nonvolatile CMOS technology, P-FLASHTM. The device is
offered in 32-pin PLCC, VSOP and PDIP packages with access time of 70 ns.
PMC
512 Kbit (64K X 8) Dual-Voltage Multiple-Cycle-Programmable ROM
Programmable Microelectronics Corp.
Issue Date: Dec, 2002 Rev:1.3
Pm37LV512
1
Programmable Microelectronics Corp.
Issue Date: Dec, 2002 Rev: 1.3
PMC
Pm37LV512
CONNECTION DIAGRAMS
LOGIC SYMBOL
2
1 6
8
A 0 - A 1 5
I/O0-I/O7
C E #
O E #
W E #
32-Pin PLCC
2 0
1 9
1 8
1 7
1 6
1 5
1 4
5
6
7
8
9
1 0
1 1
1 2
1 3
1
2
3
4
3 2
3 1
3 0
A12
A15
NC
V
CC
WE#
NC
I/O1
GND
I/O2
I/O3
I/O4
I/O5
I/O6
I/O0
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
A 1 4
A 1 3
A 8
A 9
A 1 1
O E #
A 1 0
C E #
I/O7
NC
32-Pin PDIP
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
N C
N C
A 1 5
A 1 2
A 7
A 6
A 5
A 4
A 3
A 2
I/O0
I/O1
A 1
A 0
I/O2
G N D
V
C C
W E #
N C
A 1 4
A 1 3
A 8
A 9
O E #
A 1 0
A 1 1
C E #
I/O7
I/O6
I/O5
I/O4
I/O3
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
A 1 1
A 9
A 8
A 1 3
A 1 4
N C
W E #
V
C C
N C
N C
A 1 5
A 1 2
A 7
A 6
A 5
A 4
32-Pin VSOP
I/O4
O E #
A 1 0
C E #
I/O7
I/O6
I/O5
I/O3
G N D
I/O2
I/O1
I/O0
A 0
A 1
A 2
A 3
Programmable Microelectronics Corp.
Issue Date: Dec, 2002 Rev: 1.3
PMC
Pm37LV512
PRODUCT ORDERING INFORMATION
3
Pm37LV512 -70 J C
Temperature Range
C = Commercial (0C to +70C)
Package Type
J = 32-pin Plastic J-Leaded Chip Carrier (32J)
P = 32-pin Plastic DIP (32P)
V = 32-pin Thin Small Outline Package (32V)
Speed Option
PMC Device Number
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Programmable Microelectronics Corp.
Issue Date: Dec, 2002 Rev: 1.3
PMC
Pm37LV512
PIN DESCRIPTIONS
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Programmable Microelectronics Corp.
Issue Date: Dec, 2002 Rev: 1.3
PMC
Pm37LV512
BLOCK DIAGRAM
PRODUCT IDENTIFICATION
The hardware product identification mode can be used
by an EPROM programmer to identify the device and
manufacturer for selecting the right programming algo-
rithm
for the device. The product identification mode is
activated by applying 12.0 Volt on A9 pin. For details,
please see Bus Operation Modes in Table 1.
5
W E #
C E #
O E #
C O M M A N D
R E G I S T E R
C E , O E L O G I C
A 0 - A 1 5
I/O0-I/O7
I / O B U F F E R S
D A T A
L A T C H
S E N S E
A M P
Y - G A T I N G
M E M O R Y
A R R A Y
ADDRESS
LATCH
Y - D E C O D E R
X - D E C O D E R
BYTE PROGRAMMING
The Pm37LV512 is programmed by using an external
EPROM programmer. The programming mode is acti-
vated by applying 12.0 Volt on OE# pin and V
IL
on CE#
pin. The byte program operation is completed by assert-
ing WE# to low for 20 s. A chip erase operation is
required prior to program due to a data "0" can not be
programmed back to a "1" and only erase operation can
convert "0"s to "1"s. The entire chip can be programmed
byte-by-byte by using the byte program algorithmm. Re-
fer to Chart 1. Byte Programming Flowchart and Byte
Program Operations AC Waveforms.
DEVICE OPERATION
READ OPERATION
The access of Pm37LV512 is similar as that of EPROM
or Flash Memory. To obtain data at the outputs, three
control functions must be satisfied:
CE# is the chip enable and should be pulled low
( V
IL
).
OE# is the output enable and should be pulled
low ( V
IL
).
WE# is the write enable and should remains high
( V
IH
)
.
CHIP ERASE
The entire memory array can be erased through a chip
erase operation on an external EPROM programmer.
Pre-program the "1"s cells in the device is not required
prior to chip erase operation. The chip erase operation
is activated by applying 12.0 Volt to OE# and A9 pins
while CE# pin is low. All other address and data pins
are "don't care". Chip erase is completed by asserting
WE# pin to low for 100 ms. The falling edge of WE# will
start the chip erase operation. The device will return back
to standby mode after the completion of chip erase. Refer
to Chart 2. Chip Erase Flowchart and Chip Erase
Operations AC Waveforms.
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