Preliminary
CHRONTEL
201-0000-029 Rev 6.1, 8/2/99
1
CH7002D
Scalable VGA to NTSC/PAL Encoder
Features
Fully integrated solution for PC to TV display
TrueScale
TM
rendering engine supports underscan
operation for both 640x480 or 800x600 inputs
Advanced 3-line digital flicker filtering with
programmable algorithm selections
Fully programmable through I
2
C port or hardware
(pin-based) controls
Wide range of VGA software drivers for full
synchronization and image positioning
Auto-detection of TV presence
Programmable power management features three
power-down modes
Supports both NTSC and PAL (B, D, G, H, or I) TV
formats onto both composite and S-Video
Triple 8-bit ADC inputs and triple 8-bit DAC outputs
On-chip reference generation and loop filter
Offered in 44-pin PLCC package
General Description
Chrontel's CH7002 VGA to NTSC/PAL encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output. It accepts RGB analog inputs directly
from VGA controllers and converts them directly into NTSC
or PAL TV format, with simultaneous composite and
S-Video outputs.
This circuit integrates a digital NTSC/PAL encoder with 8-
bit ADC and DAC interfaces, a 3-line vertical filter, and low-
jitter phase-locked loop to create outstanding quality video.
Through Chrontel's TrueScale
TM
rendering technology, the
CH7002 supports full vertical and horizontal underscan
operation from either 640x480 or 800x600 input to either
NTSC or PAL outputs.
A high level of performance along with full programmability
makes the CH7002 ideal for system-level PC or Web
browser solutions. All features are software programmable,
through a standard I
2
C port, to enable fully integrated system
solutions by using a TV as the primary display device.
Patent number 5,781,241
Figure 1: Functional Block Diagram
ADC
ADC
ADC
DIGITAL
NTSC/PAL
ENCODER
DAC
DAC
DAC
PLL
OSC
SYSTEM CLOCK
R
G
B
Y
CVBS
C
RSET
RSET
SD
XI
XO
COLOR
SPACE
CONVERTER
I
2
C REGISTER & CONTROL
BLOCK
ADDR
SC
& FILTER
VREF
VREF1
VREF2
LINE
MEMORY
LINE RENDERING ENGINE
-SCALING
-DEFLICKERING
-SCAN CONVERSION
TIMING & SYNC GENERATOR
R
G
B
Y
U
V
Y
U
V
PMODE
L
E
F
R
I
G
H
T
U
P
D
O
W
N
XCLK
V
H
CLKOUT
CHRONTEL
CH7002D
2 201-0000-029 Rev6.1, 8/2/99
Figure 2: 44-pin PLCC
AGND
PMODE
ADDR/FF0
V
AVDD
DVDD
UP
RIGHT
DGND
DOWN
LEFT
H
DVDD
XCLK/SD3
DVDD
CLKOUT
DGND
XI
AVDD
DGND
SC/DM2
SD/DM1
A
G
N
D
R
E
D
G
R
E
E
N
A
G
N
D
B
L
U
E
A
V
D
D
V
R
E
F
1
A
G
N
D
A
G
N
D
V
R
E
F
2
A
V
D
D
X
O
/
F
I
N
N
C
N
C
Y
G
N
D
C
C
V
B
S
V
D
D
R
S
E
T
A
G
N
D
R
E
S
E
T
/
D
M
0
7
8
9
10
13
12
11
39
38
37
36
35
14
15
16
17
34
33
32
31
30
29
6
5
4
3
2
1
4
4
4
3
4
2
4
1
4
0
1
8
1
9
2
0
2
1
2
4
2
3
2
2
2
5
2
6
2
7
2
8
CHRONTEL
CH7002
CHRONTEL
CH7002D
201-0000-029 Rev 6.1, 8/2/99
3
Table 1. Pin Description
44-Pin
PLCC
Type
Symbol
Description
2, 4, 6, 27,
39,42
Power
AGND
Analog ground
These pins provide the ground reference for the analog section of CH7002,
and MUST be connected to the system ground to prevent latchup. Refer to
the Application Information section for information on proper supply
decoupling.
1, 3, 5
In
B, G, R
VGA Inputs
These pins should be terminated with 75 ohm resistors and isolated from
switching digital signals and video output pins. Refer to the Application
Information section for detailed technical guidance and alternative connection
techniques.
7, 37, 40,
44
Power
AVDD
Analog Supply Voltage
These pins supply the 5V power to the analog section of the CH7002. For
information on proper supply decoupling, refer to the Application Information
section.
15
Out
CLKOUT
Clock Output
This pin defaults to 14.31818 MHz upon power-up and remains active at all
times (including power-down).
8, 14, 33
Power
DVDD
Digital Supply Voltage
These pins supply the 5V power to the digital section of CH7002. For
information on proper supply decoupling, refer to the Application Information
section.
10, 16, 31
Power
DGND
Digital Ground
These pins provide the ground reference for the digital section of CH7002,
and MUST be connected to the system ground to prevent latchup. For
information on proper supply decoupling, refer to the Application Information
section.
17
In
XI
Crystal Input
A parallel resonance 14.31818 MHz ( 50 ppm) crystal should be attached
between XI and XO/FIN. However, if an external CMOS clock is attached to
XO/FIN, XI should be connected to ground.
18
In
XO/FIN
Crystal Output or External Fref
A 14.31818 MHz ( 50 ppm) crystal may be attached between XO/FIN and
XI. An external CMOS compatible clock can be connected to XO/FIN as an
alternative.
25
Power
VDD
DAC Power Supply
These pins supply power to CH7002's internal DACs. Refer to
the
Application
Information section for information on proper supply decoupling.
26
In
RSET
Reference Resistor
A 324
resistor with short and wide traces should be attached between
RSET and ground. No other connections should be made to this pin.
21
Power
GND
DAC Ground
These pins provide the ground reference for CH7002's internal DACs. For
information on proper supply decoupling, refer to the Application Information
section.
24
Out
Y
Luminance Output
A 75
termination resistor with short traces should be attached between Y
and ground for optimum performance. Use of additional filters is discussed in
the Application Information section.
23
Out
CVBS
Composite Output
A 75
termination resistor, with short traces, should be attached between
CVBS and ground for optimum performance. Use of additional filters is
discussed in the Application Information section.
CHRONTEL
CH7002D
4 201-0000-029 Rev6.1, 8/2/99
44-Pin
PLCC
Type
Symbol
Description
22
Out
C
Chrominance Output
A 75
termination resistor, with short traces, should be attached between C
and ground for optimum performance. Use of additional filters is discussed in
the Application Information section.
9, 11, 12,
13
In
UP,
DOWN,
LEFT,
RIGHT
Position Controls (low-to-high transition, internal pull-up)
UP, DOWN, LEFT, and RIGHT, allows the screen display position to be
moved incrementally, in each respective direction, for every toggle of this pin
to ground. An internal schmitt trigger minimizes switch bounce problems.
These pins may be connected directly to the power supply or ground.
28
In
RESET*/D
M0
Reset (active low) /Display Mode Select [0] (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), the RESET*/DM0 pin becomes
RESET*. In this mode, when RESET* is held high (default), the chip is in
operating state, and when RESET* is pulled low, the entire chip is reset and
initialized to its power-up state.
When the PMODE pin is pulled low, this pin becomes DM0, which combined
with DM1 and DM2, provides for pin-programming of the 7002 display mode.
The pin-programming is "mux-ed" with the Display Mode register selections.
All applicable modes are described in Application Information and Registers
and Programming sections.
29
In/Out
SD/DM1
Serial Data/Display Mode Select [1] (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes SD, the serial
data pin of the I
2
C interface port.
When the PMODE pin is pulled low, this pin becomes DM1, which combined
with DM0 and DM2, provides for pin-programming of the 7002 display mode.
The pin-programming is "mux-ed" with the Display Mode register selections.
All applicable modes are described under the programming section.
30
In
SC/DM2
Serial Clock/Display Mode Select [2] (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes SC, the serial
clock pin of the I
2
C interface port.
When the PMODE pin is pulled low, this pin becomes DM2, which combined
with DM0 and DM1, provides for pin-programming of the 7002 display mode.
The pin-programming is "mux-ed" with the Display Mode register selections.
All applicable modes are described in the Registers and Programming and
Application Information sections.
32
In
XCLK/SD3
External Clock/Sample Delay (bit 3) (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes XCLK or
external clock, which accepts an external pixel clock input.
When the PMODE pin is pulled low, this pin becomes SD3 or Sample Delay,
the function corresponding to bit 3 of the Sample Delay register, which
provides the following selection:
SD3 Sample Delay Selected
1 20 ns nominal delay
0 0 delay (default)
This pin-programming is "mux-ed" with the Sample Delay register (bit 3). All
related modes are described in the Registers and Programming section.
35
In
V
Vertical Sync Input
This pin accepts the vertical sync output from the VGA card. The capacitive
loading on this pin should be kept to a minimum.
34
In
H
Horizontal Sync Input
This pin accepts the horizontal sync output from the VGA card. The
capacitive loading on this pin should be kept to a minimum. Refer to the
Application Information section for PC Board layout considerations.
Table 1. Pin Description (continued)
CHRONTEL
CH7002D
201-0000-029 Rev 6.1, 8/2/99
5
Note: For complete information concerning external signal connections, terminations, and system design considerations,
refer to the Application Information section.
44-Pin
PLCC
Type
Symbol
Description
36
In
ADDR/FF0
I
2
C Address Select/Flicker Filter (bit 0)(internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes ADDR or I
2
C
Address Select, which corresponds to bits 1 and 0 of the I
2
C device address
(see the I
2
C Control Port Operation section for details), creating an address
selection as follows:
ADDR I
2
C Address Selected
1 1110101 = 75H = 117
0 1110110 = 76H = 118
When the PMODE pin is pulled low, this pin becomes FF0 or Flicker Filter
select, the function of which corresponds to bit 0 of the Flicker Filter register,
which selects between the following:
FF0 Flicker Filter Mode
0 0:1:0 No filtering
1 1:2:1 Moderate filtering (default)
This pin-programming is "mux-ed" with the Flicker Filter register (bit 0). All
related modes are described under the Registers and Programming section.
38
In
PMODE
Programming Mode (internal pull-up)
The PMODE pin selects between the two alternative programming modes for
the CH7002, which in turn alters the function of five additional pins
(RESET/DM0, SD/DM1, SC/DM2, XCLK/SD3, and ADDR/FF0). When
PMODE is kept high (default), the chip is placed in I
2
C programming mode.
When PMODE is pulled low, the chip is placed in direct pin programming
mode.
41
In
VREF2
Internal Voltage Reference
VREF2 provides a typical 2.5V reference that is used as an internal bias to
the ADCs. A 0.1
F decoupling capacitor should be connected between
VREF2 and ground.
43
In
VREF1
ADC Voltage Reference Input / Output
VREF1 provides a typical 1.235V reference that sets the RGB input full scale
at 0.75V. A 0.1
F decoupling capacitor should be connected between
VREF1 and ground. VREF1 may also be forced by external reference, where
(VFS is the full scale input voltage):
VFS ~ VREF1 * 0.75/1.235
19, 20
NC
NC
No Connect
Table 1. Pin Description (continued)
PDF 
ZIP