Features

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·

Compatible with CS5012, CS5012A,
CS5014, CS5016

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·

PC/

P-Compatible Header Connection

16-Bit Parallel Data
End-of-Conversion Output
CS, RD, and A0 Control Inputs

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·

DIP-Switch Selectable:

Unipolar/Bipolar Input Range
Burst & Interleave Calibration Modes
Continuous Conversion

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·

Adjustable Voltage Reference

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·

Serial Data and Clock BNC Connections

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·

Operation from Internally-Generated or
Externally-Supplied Master Clock

General Description

The CDB5012/4/6 is an evaluation board that eases the
laboratory characterization of any of the CS5012,
CS5012A, CS5014 and CS5016 A/D converters. The
board can be easily reconfigured to simulate any com-
bination of sampling, master clock, calibration, and input
range conditions.

The converter's parallel output data are available at a
40 pin strip header allowing easy interfacing to PC's or
microprocessor busses. Output data is also available in
serial form at SCLK and SDATA coaxial BNC connec-
tors.

Evaluation can also be performed over a wide range of
input spans using the on-board reference circuitry. Fur-
thermore, the CDB5012, CDB5012A, CDB5014,
CDB5016 features DIP-switch selectable unipolar/bipo-
lar input ranges and the interleave calibration mode.
Calibration can be initiated at any time by momentarily
depressing a reset pushbutton.

ORDERING INFORMATION: CDB5012, CDB5012A,
CDB5014, CDB5016

MAR '95

DS14DB11

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

Evaluation Board for CS5012, CS5012A, CS5014,

CS5016 ADC's

Semiconductor Corporation

CDB5012 CDB5012A

CDB5014 CDB5016

D0 - D15

EOC

E
A

SCLK

SDATA

RESET

AIN

CLKIN

HOLD

GND -5V

+5V

VOLTAGE

REFERENCE

A/D

Converter

CS5012A

CS5014
CS5016

CS5012

Crystal Semiconductor Corporation 1995

Analog Input

The analog input to the A/D converter is supplied
through the BNC coaxial connector labeled AIN.
Analog input polarity is controlled by the first
position switch on the DIP-switch, SW-1. If it is
on, the input is unipolar ranging from GND to
VREF. If the switch is off, the input range is bi-
polar with the magnitude of the reference voltage
defining both zero- and full-scale (

VREF).

The A/D converter's internal analog input buffer
requires a source impedance of less than 400

at 1MHz for stability. Acquisition and throughput
are specified assuming a dc source impedance of
less than 200

. Infinitely large dc source imped-

ances can be accommodated by adding capaci-
tance (typically 1000pF) from the analog input to
ground. However, high dc source resistances de-
grade acquisition time and consequently through-
put.

EOC

D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

2
3
4
5
6
7
8
9

12
13
14
15
16
17
18
19
38
21

22
23

VD-

VD+

VA-

VA+

C10

C11

SCLK
SDATA
AIN
CLKIN

39
40
26
20

VREF

RESET

31 TST

29 REFBUF

R10

SW2

VD+

Reset

VD+

R23 (optional)

VA-

C12

SW1-4

37 EOT

HOLD

+5V
-5V

VD+

VD-

VA+
VA-

VD+

BP/UP
CAL

INTLV

SW1-1
SW1-2
SW1-3

33 BW

R12

R13

R11

CS5012A
CS5014
CS5016

CS5012

Figure 1. CDB5012, CDB5012A, CDB5014, CDB5016 Schematic

(Reference Circuitry Appears in Figure 3)

CDB5012, CDB5012A, CDB5014, CDB5016

DS14DB11

Initiating Conversions

A negative transition on the converter's HOLD
pin places the device's analog input into the hold
mode and initiates a conversion cycle. On the
CDB5012, CDB5012A, CDB5014, CDB5016,
this input can be generated by one of two means.
First, it can be supplied through the BNC coaxial
connector appropriately labeled HOLD. Alterna-
tively, switch position 4 of the DIP-switch can be
placed in the on position, thus looping the con-
verter's EOT output back to HOLD. This results
in continuous conversions at a fraction of the
master clock frequency (see "synchronous opera-
tion" in the converter's data sheet).

The A/D converter's EOT output is an indicator
of its acquisition status; it falls when the analog
input has been acquired to the specified accuracy.
If an external sampling clock is applied to the
HOLD BNC connector, care must similarly be
taken to obey the converter's acquisition and
maximum sampling rate requirements. A more
detailed discussion of acquisition and throughput
can be found in the converter's data sheet.

T h e C D B 5 0 1 2 , C D B 5 0 1 2 A , C D B 5 0 1 4 ,
CDB5016 is shipped from the factory without the
HOLD BNC input terminated for operation with
an external sampling clock. However, location
R23 is reserved for the insertion of a 51

resis-

tor to eliminate reflections of the incoming clock
signal.

Voltage Reference Circuitry

T h e C D B 5 0 1 2 , C D B 5 0 1 2 A , C D B 5 0 1 4 ,
CDB5016 features an adjustable voltage refer-
ence which allows characterization over a wide
range of reference voltages. The circuitry consists
of a 2.5V voltage reference (1403) and an adjust-
able gain block with a discrete output stage (Figure
3). The output stage minimizes the output's head-
room requirements allowing the reference voltage to
come within 300mV of the positive supply.

The coarse and fine trim potentiometers are fac-
tory calibrated to a reference voltage of 4.5V (a
table of output code values for a reference volt-
age of 4.5V appears in the CS5012, CS5012A,
CS5014, CS5016 data sheets). When calibrating
the reference, the voltage should be measured di-
rectly at the VREF input (pin 28) or at the un-
grounded lead of decoupling capacitor C9.

Unipolar

Normal Operation

Interleaved Cal

Continuous Conversion

OFF

Bipolar

Burst Cal *

Normal

Position 1

Position 2

Position 3

Position 4

* NOTE: Use of BURST CAL is not recommended.

Figure 2. DIP-Switch Definitions

R14

C13

R15

R17

R16

C14

R18

VREF

VA+

Coarse
Adjust

OP-07

1403

R21

R22

R19

R20

Trim

Fine

Figure 3. Voltage Reference Circuitry

CDB5012, CDB5012A, CDB5014, CDB5016

3 DS14DB11

Reset/Self-Calibration Modes

The A/D converter will usually reset itself upon
power-up. Since this function is not guaranteed,
the converter must be reset upon power-up in
system operation. The converter can be reset on
the CDB5012, CDB5012A, CDB5014, CDB5016
board by momentarily depressing push-button
SW-2 thus initiating a full calibration cycle;
1,443,840 master clock cycles later the converter
is ready for normal operation.

The converters also feature two other calibration
modes: burst and interleave. The use of Burst
calibration is not recommended. Interleave can be
initiated by setting switch position 3 to the on
position. In the interleave mode (INTRLV low),
the converter appends one small portion of a cali-
bration cycle (20 master clock cycles) to each
conversion cycle. Thus, a full calibration cycle
completes every 72,192 conversion cycles. The
Interleave calibration mode should not be used
intermittently.

A more detailed discussion of the converters'
calibration modes and capabilities can be found
in their data sheets.

Parallel Output Data/Microprocessor Interface

The converter's outputs D0-D15, its CS, RD, and
A0 inputs, and its EOC output are available at
the 40 pin header. The CS and RD inputs are
pulled low through 10 k

resistors placing

the converter in a microprocessor-independent
mode. Control input A0 is pulled up, insuring the
converter's output word, rather than the status
register, appears at the header.

The converter's 3-state output buffers and micro-
processor interface can be exercised by driving
the CS and/or RD inputs at the header. Similarly,
the converter's 8-bit status register can be ob-
tained on D0-D7 by driving A0 low.

The converter's EOC and data outputs are not
b u f f e r e d o n t h e C D B 5 0 1 2 , C D B 5 0 1 2 A ,
CDB5014, CDB5016. Therefore, careful attention
should be paid to the load presented by any ca-
bling, especially if the 3-state output buffers are
to be exercised at speed. Twisted ribbon cable is
typically specified at 10pF/ft, so several feet can
generally be accommodated.

Serial Output Data

Serial output data is available at the two BNC
connections SCLK and SDATA. Data appears
MSB first, LSB last, and is valid on the rising
edge of SCLK.

Master Clock

The A/D converter operates from a master clock
which can either be internally-generated or exter-
nally-supplied. For operation with an external
clock, the BNC connector labeled CLKIN
should be driven with a TTL clock signal. The
CDB5012, CDB5012A, CDB5014, CDB5016 is
shipped from the factory with the CLKIN input

D0
D1
D2
D3
D4
D5
D6

D7
D8
D9

A0
RD

D10
D11
D12
D13
D14
D15
EOC

DGND

Figure 4. Header Pin Definitions

CDB5012, CDB5012A, CDB5014, CDB5016

DS14DB1 4

terminated by a 51

resistor to eliminate line

reflections of the incoming clock. If the CLKIN
BNC input is left floating, this resistor pulls the
converter's clock input down to ground, thus ac-
tivating its internal oscillator.

Decoupling

T h e C D B 5 0 1 2 , C D B 5 0 1 2 A , C D B 5 0 1 4 ,
CDB5016's decoupling scheme was designed to
insure accurate evaluation of the converter's per-

formance independent of the quality of the power
supplies. Each supply is decoupled at the con-
verter with a 10

F electrolytic capacitor to filter

low frequency noise and a 0.1

F ceramic capaci-

tor to handle higher frequencies. The auto-zero-
ing action of the converter's comparator provides
extremely good power supply rejection at low
frequencies. Depending on the quality of the sys-
tem's power supplies, the decoupling scheme
could be relaxed in actual use.

COMPONENT LIST

resistor

R1, R2

resistor

4.7

resistor

R18

1 k

resistor

R9, R14

560

resistor

R17

10 k

resistor

R4, R5, R6, R7, R8, R10, R11, R12, R13

2.43 k

resistor

R19, R20

3.3 k

resistor

R16

240 k

resistor

R21

50 k

potentiometer

R15

50 k

potentiometer

R22

0.068

F capacitor

C14

0.1

F capacitor

C1, C3, C5, C7, C9, C10, C12

F capacitor

C2, C4, C6, C8, C11, C13

CS501X/511X A/D converter

1403 2.5V reference

OP07 op amp

2N2907A transistor

4 pos. SPST DIP switch

SW1

N.O. SPST push-button

SW2

20 pin header

CON1

bulkhead BNC

CON2, CON3, CON4, CON5, CON6

red banana jack

CON7

black banana jack

CON8

green banana jack

CON9

1" 4-40 spacer

POST1, POST2, POST3, POST4, POST5, POST6

3/8" 4-40 screw

SC1, SC2, SC3, SC4, SC5, SC6

CDB5012, CDB5012A, CDB5014, CDB5016

5 DS14DB11

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CDB5014